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1. 发明公开

EP2656224A4 CONTINUOUS PAGE READ FOR MEMORY 有权
标题翻译： KONTINUIERLICHER LEITENLESEVORGANGFÜRSPEICHER
公开(公告)号：EP2656224A4
公开(公告)日：2014-06-11
申请号：EP10860986
申请日：2010-12-24
申请人： MICRON TECHNOLOGY INC
发明人： SHEN JUN , ZHANG YIHUA
IPC分类号： G06F12/00 , G06F12/02 , G06F12/08 , G11C16/00
CPC分类号： G06F12/0862 , G06F12/0215 , G06F2212/1016 , G06F2212/2022 , G06F2212/6022 , G06F2212/654 , G11C7/1039 , G11C8/04 , G11C16/26
摘要： Subject matter disclosed herein relates to techniques to read memory in a continuous fashion.
摘要翻译：本文公开的主题涉及以连续方式读取存储器的技术。

2. 发明公开

EP2454669A1 TLB PREFETCHING 审中-公开
标题翻译： TLB货物预报
公开(公告)号：EP2454669A1
公开(公告)日：2012-05-23
申请号：EP10734414.5
申请日：2010-07-12
申请人： Apple Inc.
发明人： WANG, James , CHEN, Zongjian
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F2212/6022 , G06F2212/6028 , G06F2212/654 , G06F2212/681 , G06F2212/684
摘要： In an embodiment, a memory management unit (MMU) is configured to retain a block of data that includes multiple page table entries. The MMU is configured to check the block in response to TLB misses, and to supply a translation from the block if the translation is found in the block without generating a memory read for the translation. In some embodiments, the MMU may also maintain a history of the TLB misses that have used translations from the block, and may generate a prefetch of a second block based on the history. For example, the history may be a list of the most recently used Q page table entries, and the history may show a pattern of access that are nearing an end of the block. In another embodiment, the history may comprise a count of the number of page table entries in the block that have been used.

3. 发明公开

EP2095243A2 CONFIGURABLE CACHE FOR A MICROPROCESSOR 有权
标题翻译：配置的缓存数据在微处理器
公开(公告)号：EP2095243A2
公开(公告)日：2009-09-02
申请号：EP07869282.9
申请日：2007-12-14
申请人： Microchip Technology Incorporated
发明人： PESAVENTO, Rodney J. , LAHTI, Gregg D. , TRIECE, Joseph W.
IPC分类号： G06F12/12
CPC分类号： G06F12/126 , G06F12/0862 , G06F2212/2022 , G06F2212/6022
摘要： A cache module for a central processing unit has a cache control unit coupled with a memory, and a cache memory coupled with the control unit and the memory wherein the cache memory has a plurality of cache lines, each cache line having a storage area for storing instructions to be issued sequentially and associated control bits, wherein at least one cache line of the plurality of cache lines has at least one branch trail control bit which when set provides for an automatic locking function of the cache line in case a predefined branch instruction has been issued.

4. 发明公开

EP2021928A1 VERFAHREN UND VORRICHTUNG ZUR BESCHLEUNIGUNG VON PROZESSOR-ZUGRIFFEN 有权
标题翻译：方法和设备加速处理器访问的
公开(公告)号：EP2021928A1
公开(公告)日：2009-02-11
申请号：EP06753213.5
申请日：2006-05-30
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： KAUER, Karl , MÖSSNER, Rudolf
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6022
摘要： The invention relates to a method and a device for increasing the access speed of a processor to data in a main memory by means of an interim memory, wherein the data requested by the processor are compared with the data in the interim memory, which are transmitted to the processor in case of a match with the requested data and further data are transmitted from the main memory to the interim memory in advance depending on the requested data. According to the invention, to store data from multiple prefetch processes in a prefetch memory, the data in the main memory that succeeds the requested data is stored in the interim memory as an entry in one area, the same area of the interim memory being used for data that succeeds requested data contained in the interim memory and a new area being created in the interim memory for data that succeeds requested data not contained in the interim memory. Data can be stored in at least two areas of the interim memory.

5. 发明公开

EP1756718A4 MEMORY HUB AND METHOD FOR MEMORY SEQUENCING 审中-公开
标题翻译： SPEICHER-HUB UND VERFAHREN ZUR SPEICHERSEGMENTIERUNG
公开(公告)号：EP1756718A4
公开(公告)日：2008-11-26
申请号：EP05746289
申请日：2005-05-04
申请人： MICRON TECHNOLOGY INC
发明人： JEDDELOH JOSEPH M
IPC分类号： G06F12/08 , G06F12/00 , G06F12/02
CPC分类号： G06F12/0215 , G06F12/0862 , G06F12/0888 , G06F2212/6022 , G06F2212/6026
摘要： A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics-for example, page hit rate, prefetch hits, and/or cache hit rate. The performance counter communicates with a memory sequencer that adjusts its operation based on the system metrics tracked by the performance counter.
摘要翻译：存储器模块包括耦合到若干存储器设备的存储器集线器。存储器集线器包括跟踪一个或多个系统度量的至少一个性能计数器 - 例如，页面命中率，预取命中和/或高速缓存命中率。性能计数器与内存序列器通信，内存序列器根据性能计数器跟踪的系统度量调整其操作。

6. 发明授权

EP0449540B1 Memory system and method with prefetch buffer 失效
标题翻译：存储器阵列和方法Vorausholungspuffer
公开(公告)号：EP0449540B1
公开(公告)日：2000-05-17
申请号：EP91302555.7
申请日：1991-03-25
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Jouppi, Norman P. , Eustace, Alan
IPC分类号： G06F12/08 , G06F9/38
CPC分类号： G06F12/0862 , F02B2075/027 , G06F2212/6022

7. 发明公开

EP0795820A2 Combination prefetch buffer and instructions cache 失效
标题翻译： Puffersteuerung zum Vorausholen von Befehlen
公开(公告)号：EP0795820A2
公开(公告)日：1997-09-17
申请号：EP97104937.4
申请日：1993-12-02
申请人： ADVANCED MICRO DEVICES INC.
发明人： Tran, Thang
IPC分类号： G06F9/38
CPC分类号： G06F9/3814 , G06F9/3802 , G06F9/3808 , G06F12/0862 , G06F2212/6022 , Y02D10/13
摘要： A cache memory system features a combination instruction cache and prefetch buffer, which obviates any requirement for a bus interconnecting the cache and buffer and which also effectively allows the instruction buffer to write data into the cache with improved utilization of prefetched instructions and with decreased use of power and silicon space.
摘要翻译：高速缓冲存储器系统具有组合指令高速缓存和预取缓冲器，其消除了将高速缓存和缓冲器互连的总线的任何要求，并且还有效地允许指令缓冲器将数据写入高速缓存中，同时改进了预取指令的利用率，电源和硅片空间。

8. 发明公开

EP0457403A2 Multilevel instruction cache, method for using said cache, method for compiling instructions for said cache and micro computer system using such a cache 失效
标题翻译：一种多级指令高速缓冲存储器，使用其的方法，用于使用所述高速缓冲存储器和微计算机系统与该高速缓冲存储器的指令进行编译的方法。
公开(公告)号：EP0457403A2
公开(公告)日：1991-11-21
申请号：EP91201135.0
申请日：1991-05-10
申请人： Philips Electronics N.V.
发明人： Chi, Chi-Hung
IPC分类号： G06F9/38 , G06F9/44 , G06F12/08
CPC分类号： G06F12/0897 , G06F9/3802 , G06F9/381 , G06F9/3814 , G06F9/383 , G06F12/0862 , G06F12/0888 , G06F2212/6022 , G06F2212/6028
摘要： A cache memory for use between a processing unit and a main memory includes a prefetch buffer, a use buffer, and a head buffer. The prefetched buffer is a FIFO or LRU register which prefetches instructions from contiguous memory locations after the address specified by the program counter. The head buffer is a FIFO or LRU register which is utilized to store instructions from the tops of the program blocks which are accessed from main memory following recent cache misses. The use buffer is a relatively large, inexpensive buffer, preferably a directly mapped buffer, which stores recent hits from the prefetched buffer as well as selected instructions from main memory following cache misses.
摘要翻译：为处理单元和主存储器之间使用的高速缓冲存储器包括一个预取缓冲器，缓冲器的使用，和头部缓冲器。预取缓冲器是FIFO或LRU寄存器，其从由程序计数器指定的地址之后连续的存储单元预取指令。头部缓冲器是FIFO或LRU注册所有这一切都被用来存储从从主存继最近高速缓存未命中访问的程序块的顶端指示。使用缓冲是比较大的，廉价的缓冲，最好是直接映射缓存，存储从预取缓冲的最近更新以及从主内存中继高速缓存未命中选定指令。

9. 发明公开

EP0449540A2 Data processing system and method with small fully-associative cache and prefetch buffers 失效
标题翻译：方法和用于与小全相联高速缓冲存储器和Vorausholungspuffern数据处理装置。
公开(公告)号：EP0449540A2
公开(公告)日：1991-10-02
申请号：EP91302555.7
申请日：1991-03-25
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Jouppi, Norman P. , Eustace, Alan
IPC分类号： G06F12/08 , G06F9/38
CPC分类号： G06F12/0862 , F02B2075/027 , G06F2212/6022
摘要： A memory system (10) utilizes miss caching by incorporating a small fully-associative miss cache (42) between a cache (18 or 20) and second-level cache (26). Misses in the cache (18 or 20) that hit in the miss cache have only a one cycle miss penalty, as opposed to a many cycle miss penalty without the miss cache (42). Victim caching is an improvement to miss caching that loads a small, fully associative cache (52) with the victim of a miss and not the requested line. Small victim caches (52) of 1 to 4 entries are even more effective at removing conflict misses than miss caching. Stream buffers (62) prefetch cache lines starting at a cache miss address. The prefetched data is placed in the buffer (62) and not in the cache (18 or 20). Stream buffers (62) are useful in removing capacity and compulsory cache misses, as well as some instruction cache misses. Stream buffers (62) are more effective than previously investigated prefetch techniques when the next slower level in the memory hierarchy is pipelined. An extension to the basic stream buffer, called multi-way stream buffers (62), is useful for prefetching along multiple intertwined data reference streams.
摘要翻译：一种存储器系统（10），通过将一个高速缓存（18或20）和第二级高速缓存（26）之间有小的全相联高速缓存未命中（42）利用高速缓存未命中。在缓存（18或20）在高速缓存未命中没有失误只有一个周期的命中损失，而不是一个多周期命中判罚没有高速缓存未命中（42）。受害者缓存是一种进步小姐缓存做负载小，全关联缓存（52）与未中的受害者，而不是请求的线。 1至4项小受害者高速缓存（52）甚至比小姐缓存删除冲突缺失更有效。流缓冲（62）预取缓存线起始于高速缓存未命中地址。预取的数据在缓冲器（62），而不是在高速缓存（18或20）放置。流缓冲器（62）在去除能力和强制缓存未命中，以及一些指令高速缓存未命中是有用的。流缓冲器（62）是更有效的比以前调查的预取技术当在存储器层次结构中的下一个较慢的电平被流水线化。基本数据流缓存器的延伸部，所谓的多路流缓冲器（62）是用于沿多个交织数据流参考预取有用的。

10. 发明授权

EP2457168B1 SIGNAL PROCESSING SYSTEM, INTEGRATED CIRCUIT COMPRISING BUFFER CONTROL LOGIC AND METHOD THEREFOR 有权
公开(公告)号：EP2457168B1
公开(公告)日：2018-09-26
申请号：EP09847522.1
申请日：2009-07-20
申请人： NXP USA, Inc.
发明人： ROBERTSON, Alistair , CIRCELLO, Joseph , Maiolani, Mark
IPC分类号： G06F12/127 , G06F12/0862 , G06F12/123 , G06F13/16 , G06F5/00 , G06F12/12 , G06F12/08 , G06F9/38
CPC分类号： G06F12/0862 , G06F9/3804 , G06F9/3814 , G06F12/123 , G06F12/127 , G06F2212/6022
摘要： A signal processing system comprising buffer control logic arranged to allocate a plurality of buffers for the storage of information fetched from at least one memory element. Upon receipt of fetched information to be buffered, the buffer control logic is arranged to categorize the information to be buffered according to at least one of: a first category associated with sequential flow and a second category associated with change of flow, and to prioritize respective buffers from the plurality of buffers storing information relating to the first category associated with sequential flow ahead of buffers storing information relating to the second category associated with change of flow when allocating a buffer for the storage of the fetched information to be buffered.

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