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1. 发明授权

EP0244628B1 Sense amplifier for a semiconductor memory device 失效
标题翻译：用于半导体存储器件的感测放大器
公开(公告)号：EP0244628B1
公开(公告)日：1990-12-27
申请号：EP87104661.1
申请日：1987-03-30
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Atsumi, Shigeru c/o Patent Division , Tanaka, Sumio c/o Patent Division , Otsuka, Nobuaki c/o Patent Division , Kamei, Takashi c/o Patent Division
IPC分类号： G11C7/06 , G11C11/34
CPC分类号： G11C16/3459 , G11C7/06 , G11C16/12 , G11C16/28 , G11C16/3454

2. 发明公开

EP0244628A1 Sense amplifier for a semiconductor memory device 失效
标题翻译： Leseverstärkerfüreine Halbleiter-Speicheranordnung。
公开(公告)号：EP0244628A1
公开(公告)日：1987-11-11
申请号：EP87104661.1
申请日：1987-03-30
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Atsumi, Shigeru c/o Patent Division , Tanaka, Sumio c/o Patent Division , Otsuka, Nobuaki c/o Patent Division , Kamei, Takashi c/o Patent Division
IPC分类号： G11C7/06 , G11C11/34
CPC分类号： G11C16/3459 , G11C7/06 , G11C16/12 , G11C16/28 , G11C16/3454
摘要： In a sense amplifier, the first input terminal of the differential amplifier (26) is connected to a first MOS transistor (23) operating as a transfer gate, a first floating gate transistor (22) operating as a memory cell, and a first load (24). The gates of the first MOS transistor (23) and the first floating gate transistor (22) are respectively connected to the column-select line (BL) and the word line (WL). The second input terminal of the differential amplifier (26) is connected to a second load (28), a second MOS transistor (31) operating as a transfer gate, and a second floating gate transistor (32) operating as a dummy cell. The second load (28) has the same characteristics as the first load (24). The second load (28) is composed of first and second load elements (28A, 28B). The second floating gate transistor (32) is constantly supplied with power voltage. When a shift in the thre shold voltage of the first floating gate transistor (22) is monitored, the first load element (28A) of the second load (28) is disconnected from the input terminal of the differential amplifier (26), and only the second load element (28B) remains connected to the input terminal. The gate of the second MOS transistor (31) is supplied with the high potential. A gradually increasing potential is applied to the gates of the first MOS transistor (23) and the first floating gate transistor (22). The potential is detected when the data of the first floating gate transistor changes from "0" to "1".
摘要翻译：在读出放大器中，差分放大器（26）的第一输入端连接到作为传输门工作的第一MOS晶体管（23），作为存储单元工作的第一浮栅晶体管（22）和第一负载（24）。第一MOS晶体管（23）和第一浮栅晶体管（22）的栅极分别连接到列选择线（BL）和字线（WL）。差分放大器（26）的第二输入端连接到第二负载（28），作为传输栅极工作的第二MOS晶体管（31）和作为虚设单元工作的第二浮栅晶体管（32）。第二负载（28）具有与第一负载（24）相同的特性。第二负载（28）由第一和第二负载元件（28A，28B）组成。第二浮栅晶体管（32）经常被供给电源电压。当监视第一浮栅晶体管（22）的输出电压的偏移时，第二负载（28）的第一负载元件（28A）与差分放大器（26）的输入端断开，只有第二负载元件（28B）保持连接到输入端子。第二MOS晶体管（31）的栅极被提供高电位。对第一MOS晶体管（23）和第一浮栅晶体管（22）的栅极施加逐渐增加的电位。当第一浮栅晶体管的数据从“0”变为“1”时，检测电位。

3. 发明公开

EP0324185A3 Input protecting circuit in use with a MOS semiconductor device 失效
标题翻译：使用MOS半导体器件的输入保护电路
公开(公告)号：EP0324185A3
公开(公告)日：1990-09-26
申请号：EP88121907.5
申请日：1988-12-30
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Atsumi, Shigeru c/o Patent Division , Yoshida, Toru c/o Patent Division , Kawahara, Yasuo c/o Patent Division , Tanaka, Fuminari c/o Patent Division
IPC分类号： H01L27/02
CPC分类号： H01L27/0251
摘要： A bipolar transistor (14) for clamping an excess input potential is provided near an input pad (11). A signal from the input pad (11) is supplied through a wire (12) to the gate of a MOS transistor (13) in the input stage. A diode (15) is provided near the gate of the MOS transistor (13). The diode absorbs a potential oscillation generated in the wire (12) near the gate of the transistor (13), which is due to action of an inductance (L) involved in the wire (12).

4. 发明公开

EP0279453A1 Reference potential generating circuit for a semiconductor device 失效
标题翻译： Schaltkreis zur Erzeugung von ReferenzspannungenfürHalbleitervorrichtung。
公开(公告)号：EP0279453A1
公开(公告)日：1988-08-24
申请号：EP88102448.3
申请日：1988-02-19
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Ohtsuka, Nobuaki c/o Patent Division , Tanaka, Sumio c/o Patent Division , Miyamoto, Junichi c/o Patent Division , Atsumi, Shigeru c/o Patent Division , Imamiya, Keniti c/o Patent Division
IPC分类号： H01L27/10 , G11C7/00
CPC分类号： H01L27/115
摘要： A plurality of dummy cells forming a dummy cell array is formed in the semiconductor chip (100). A dummy cell (32) surrounded by other dummy cells in the array is used for generating a reference potential. The contact (28₂) of Vss line for connecting the source of the dummy cell to the ground is located at the center portion of the dummy cell array. With such a layout, the cell pattern of the dummy cell is the same as that of the memory cells. Accordingly, the transistor characteristics of these cells may also be substantially identical to each other. Thus, the problem arising from the difference in the pattern geometry can be solved.
摘要翻译：在半导体芯片（100）中形成形成虚设单元阵列的多个虚拟单元。使用由阵列中的其他虚拟单元包围的虚拟单元（32）来产生参考电位。用于将虚拟单元的源连接到地的Vss线的触点（282）位于虚拟单元阵列的中心部分。通过这样的布局，虚拟单元的单元图案与存储单元的单元图案相同。因此，这些单元的晶体管特性也可以基本相同。因此，可以解决由图案几何形状的不同引起的问题。

5. 发明授权

EP0279453B1 Reference potential generating circuit for a semiconductor device 失效
标题翻译：用于半导体器件的参考电位发生电路
公开(公告)号：EP0279453B1
公开(公告)日：1992-08-05
申请号：EP88102448.3
申请日：1988-02-19
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Ohtsuka, Nobuaki c/o Patent Division , Tanaka, Sumio c/o Patent Division , Miyamoto, Junichi c/o Patent Division , Atsumi, Shigeru c/o Patent Division , Imamiya, Keniti c/o Patent Division
IPC分类号： H01L27/10 , G11C7/00
CPC分类号： H01L27/115

6. 发明授权

EP0251429B1 Non-volatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：EP0251429B1
公开(公告)日：1992-05-13
申请号：EP87302549.8
申请日：1987-03-24
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Atsumi, Shigeru c/o Patent Division , Tanaka, Sumio c/o Patent Division , Saito, Shinji c/o Patent Division , Otsuka, Nobuaki c/o Patent Division
IPC分类号： G11C29/00
CPC分类号： G11C29/50004 , G06F2201/81 , G11C16/04 , G11C16/34 , G11C29/50 , G11C29/50016
摘要： This invention provides a non-volatile semiconductor memory having a first node (12) and a second node (Vss), the second node having a ground potential, comprising: a plurality of non-volatile memory cells (16) each having a drain and a threshold potential, the cells (16) for storing data written into the cells (16) at a predetermined normal writing voltage; a plurality of bit lines (14), each memory cell (16) being connected to one of the bit lines (14) for transferring data to and from the memory cells (16); and a circuit (11, 12, 13, 19, 20, 21) connected to the bit lines (14) for simultaneously testing the memory cells (16) of all the bit lines (14) at the normal writing voltage to detect changes in the threshold potential. The circuit (11, 12, 13, 19, 20, 21) acts to reduce a writing supply voltage Vpp to the normal writing voltage by using a dummy memory cell (20), to simulate the voltage drop from Vpp which would be experienced in the normal write mode, so that the memory cells are not unduly stressed during testing.

7. 发明公开

EP0249903A2 Semiconductor memory device 失效
标题翻译： Halbleiterspeichergerät。
公开(公告)号：EP0249903A2
公开(公告)日：1987-12-23
申请号：EP87108508.0
申请日：1987-06-12
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Saito, Shinji c/o Patent Division , Atsumi, Shigeru c/o Patent Division , Tanaka, Sumio c/o Patent Division
IPC分类号： G11C29/00 , G06F11/20
CPC分类号： G11C29/781 , G11C29/24
摘要： A semiconductor memory device includes a main memory cell array (30A), a redundancy memory cell array (30B), bonding pads for receiving an address signal, a row decoder (32) for selecting a row of the main memory cell array (30A), in accordance with the row address signal, and an exchange controller (46) connected to receive the address signal, which is programmable to inhibit the selective operation of the row decoder (32) to select the row of the redundancy memory cell array (32B), in response to specific address signals. The semiconductor memory device further includes bonding pads each for receiving a test signal. The exchange controller (46) is connected to receive the test signal for inhibiting the selective operation of the row decoder (32) and selecting the row of the redundancy memory cell array (30B), in response to the test signal.
摘要翻译：一种半导体存储器件，包括主存储单元阵列（30A），冗余存储单元阵列（30B），用于接收地址信号的接合焊盘，用于选择主存储单元阵列（30A）行的行解码器（32），和根据行地址信号的交换控制器（46），以及连接以接收地址信号的交换控制器（46），其可编程为禁止行解码器（32）的选择性操作以选择冗余存储单元阵列（32B）的行），以响应具体的地址信号。半导体存储器件还包括用于接收测试信号的接合焊盘。交换控制器46被连接以响应于测试信号而接收用于禁止行解码器（32）的选择性操作并选择冗余存储单元阵列（30B）的行的测试信号。

8. 发明授权

EP0249903B1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：EP0249903B1
公开(公告)日：1992-05-13
申请号：EP87108508.0
申请日：1987-06-12
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Saito, Shinji c/o Patent Division , Atsumi, Shigeru c/o Patent Division , Tanaka, Sumio c/o Patent Division
IPC分类号： G11C29/00 , G06F11/20
CPC分类号： G11C29/781 , G11C29/24
摘要： A semiconductor memory device includes a main memory cell array (30A), a redundancy memory cell array (30B), bonding pads for receiving an address signal, a row decoder (32) for selecting a row of the main memory cell array (30A), in accordance with the row address signal, and an exchange controller (46) connected to receive the address signal, which is programmable to inhibit the selective operation of the row decoder (32) to select the row of the redundancy memory cell array (32B), in response to specific address signals. The semiconductor memory device further includes bonding pads each for receiving a test signal. The exchange controller (46) is connected to receive the test signal for inhibiting the selective operation of the row decoder (32) and selecting the row of the redundancy memory cell array (30B), in response to the test signal.
摘要翻译：一种半导体存储器件包括主存储单元阵列（30A），冗余存储单元阵列（30B），用于接收地址信号的接合焊盘，用于选择主存储单元阵列（30A）的行的行解码器（32），以及交换控制器（46），其被连接以接收地址信号，该地址信号是可编程的以禁止行解码器（32）的选择性操作来选择冗余存储单元阵列（32B）的行），以响应特定的地址信号。该半导体存储器件还包括用于接收测试信号的接合焊盘。响应于测试信号，交换控制器（46）被连接以接收用于禁止行解码器（32）的选择操作并选择冗余存储单元阵列（30B）的行的测试信号。

9. 发明公开

EP0249903A3 Semiconductor memory device 失效
公开(公告)号：EP0249903A3
公开(公告)日：1989-10-25
申请号：EP87108508.0
申请日：1987-06-12
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Saito, Shinji c/o Patent Division , Atsumi, Shigeru c/o Patent Division , Tanaka, Sumio c/o Patent Division
IPC分类号： G11C29/00 , G06F11/20
CPC分类号： G11C29/781 , G11C29/24
摘要： A semiconductor memory device includes a main memory cell array (30A), a redundancy memory cell array (30B), bonding pads for receiving an address signal, a row decoder (32) for selecting a row of the main memory cell array (30A), in accordance with the row address signal, and an exchange controller (46) connected to receive the address signal, which is programmable to inhibit the selective operation of the row decoder (32) to select the row of the redundancy memory cell array (32B), in response to specific address signals. The semiconductor memory device further includes bonding pads each for receiving a test signal. The exchange controller (46) is connected to receive the test signal for inhibiting the selective operation of the row decoder (32) and selecting the row of the redundancy memory cell array (30B), in response to the test signal.

10. 发明授权

EP0324185B1 Input protecting circuit in use with a MOS semiconductor device 失效
标题翻译：输入保护电路的MOS半导体器件。
公开(公告)号：EP0324185B1
公开(公告)日：1993-10-27
申请号：EP88121907.5
申请日：1988-12-30
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Atsumi, Shigeru c/o Patent Division , Yoshida, Toru c/o Patent Division , Kawahara, Yasuo c/o Patent Division , Tanaka, Fuminari c/o Patent Division
IPC分类号： H01L27/02
CPC分类号： H01L27/0251

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