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1. 发明授权

EP1224549B1 REDUNDANT DUAL BANK ARCHITECTURE FOR A SIMULTANEOUS OPERATION FLASH MEMORY 有权
标题翻译：冗余的双堤体结构的同时闪存
公开(公告)号：EP1224549B1
公开(公告)日：2003-08-27
申请号：EP00972043.4
申请日：2000-10-09
申请人： ADVANCED MICRO DEVICES INC. , FUJITSU LIMITED
发明人： KASA, Yasushi , WANG, Guowei
IPC分类号： G06F11/20
CPC分类号： G11C29/781 , G11C2216/22
摘要： The present invention discloses sector-based redundancy that is capable of making repairs using a plurality of redundant columns of memory cells in a dual bank memory device during simultaneous operation. The simultaneous operation memory device includes a plurality of redundant blocks (18) that can be configured to be located in an upper bank (20) or a sliding lower bank (22). The redundant blocks (18) are comprised of sectors (12) and each sectors (12) and each sector (12) contains columns of memory cells (26). During simultaneous operation, the memory device is capable of reading the columns of memory cells (26) in one bank and writing columns of memory cells (26) in the other bank at the same time. In addition, the simultaneous operation memory device uses sector-based redundancy to repair columns of memory cells (26) that are defective in one bank by electrically exchanging them with redundant columns of memory cells (34) and, at the same time, repair columns of memory cells (26) that are defective in the other bank. The dual bank sector-based redundancy includes a plurality of address CAM circuits (54) that are configurably associated with the redundant blocks (18) based on the blank location of the redundant blocks (18). The address CAM circuits (54) are configured by a redundancy CAM read drain decoder circuit (50).

2. 发明公开

EP1102168A2 Integrierter Speicher mit Speicherzellen und Referenzzellen 有权
公开(公告)号：EP1102168A2
公开(公告)日：2001-05-23
申请号：EP00124934.1
申请日：2000-11-15
申请人： Infineon Technologies AG
发明人： Pöchmüller, Peter
IPC分类号： G06F11/20
CPC分类号： G11C29/781
摘要： Der integrierte Speicher weist Referenzwortleitungen (WLREF, /WLREF), Wortleitungen (WLi) und redundante Wortleitungen (RWL1, RWL2) auf. Er hat eine programmierbare Aktivierungseinheit (AKT), von deren Programmierzustand abhängt, ob die redundante Wortleitung (RWL1, RWL2) mit den daran angeschlossenen redundanten Speicherzellen (RC) während des Betriebs des Speichers eine der Wortleitungen (WLi) mit den daran angeschlossenen Speicherzellen (MC) oder die Referenzwortleitung (WLREF, /WLREF) mit den daran angeschlossenen Referenzzellen (CREF) ersetzt.
摘要翻译：集成存储器具有布置在字线（WL1，...）和位线（BL1，...）的交点处的存储单元（MC），在至少一个参考字线的交点处的参考单元（CREF） WLREF），/ WLREF）和用于在访问存储器单元之一之前的位线上产生参考电位的位线，在冗余字线（RWL1，...）与交点处的冗余存储单元（RC）位线和可编程激活单元（AKT），用于确定是否连接冗余字线和存储单元。

3. 发明授权

EP0490680B1 A semiconductor memory with multiplexed redundancy 失效
标题翻译：半导体存储器具有冗余复
公开(公告)号：EP0490680B1
公开(公告)日：1996-10-02
申请号：EP91311571.3
申请日：1991-12-12
申请人： SGS-THOMSON MICROELECTRONICS, INC. (a Delaware corp.)
发明人： Coker, Thomas Allyn , McClure, David Charles
IPC分类号： G06F11/20
CPC分类号： G11C29/808 , G11C29/781 , G11C29/846
摘要： An integrated circuit memory is disclosed which includes redundant columns associated with a sub-array, and in which multiple input/output terminals are placed in communication with multiple columns in the sub-array in read and write cycles. The number of redundant columns per sub-array is less than the number of input/output terminals. A multiplexer connects the selected redundant column to a selected sense amplifier and write circuit for the input/output with which the replaced column was associated. The multiplexer includes pass gates connected to the bit lines of the redundant column, and fuses connected between each of the pass gates and each of the sense/write circuits selectable for the redundant column. Those of the fuses which are not associated with the selected input/output are opened, and the fuses associated with the selected input/output are left intact. Precharge transistors are connected to the fuse sides of the pass gates, for precharging each of the floating nodes after the pass gates are turned off. This precharging negates the effect of any charge which may be trapped on the fuse side of the pass gates for those lines where the fuses are opened, so that the access time for the next cycle will not be degraded.

4. 发明授权

EP0472209B1 Semiconductor memory device having redundant circuit 失效
标题翻译：具有冗余电路的半导体存储器件
公开(公告)号：EP0472209B1
公开(公告)日：1996-06-05
申请号：EP91114171.1
申请日：1991-08-23
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Ogihara, Masaki, c/o Intellectual Prop. Division
IPC分类号： G06F11/20
CPC分类号： G11C29/781
摘要： An output of a column redundant circuit (20) is supplied to one spare column selection line (SCDL). The spare column selection line (SCDL) is provided to select the spare column line. The column redundant circuit (20) includes four spare column decoders (21-1 to 21-4) of the same number as that of the memory cell arrays which can be selected by the column selection line supplied with an output of a partial column decoder (11), and an OR gate (22) for deriving the logical sum of outputs of the four spare column decoders (21-1 to 21-4) and supplying the same to the spare column selection line (SCDL). An output of the OR gate (22) is supplied to a logic circuit (12) together with an output of the partial column decoder (11).

5. 发明公开

EP0675441A1 Dispositif matriciel de fusibles de redondance pour mémoire intégrée et procédé de mise en oeuvre 失效
标题翻译：冗余熔丝阵列集成存储和它们的操作方法。
公开(公告)号：EP0675441A1
公开(公告)日：1995-10-04
申请号：EP95400607.8
申请日：1995-03-20
申请人： SGS-THOMSON MICROELECTRONICS S.A.
发明人： Rouy, Olivier , Gaultier, Jean-Marie
IPC分类号： G06F11/20
CPC分类号： G11C29/781
摘要： L'invention concerne les mémoires à circuits intégrés organisées en rangées et colonnes et, dans de telles mémoires, un dispositif de fusibles de redondance pour enregistrer les adresses des rangées et colonnes défectueuses et pour sélectionner un élément redondant de remplacement lorsqu'une adresse d'une rangée ou colonne défectueuse est détectée.
L'invention réside dans le fait que le code de l'adresse (A O , A n ) de chaque rangée ou colonne défectueuse est enregistrée dans une colonne de cellules de mémoire (ELF O , ELF M ) qui comprend deux cellules (C OO , CI OO ) par chiffre du code d'adresse enregistrant chacune soit le chiffre lui-même, soit son complément. Lors de la lecture, seule la colonne qui correspondra au code de l'adresse préalablement enregistrée ne sera parcourue par aucun courant, ce qui sélectionnera l'élément redondant associé.
摘要翻译：集成电路存储器被以行和列布置并且包括用于记录缺陷的行和列的地址，冗余熔丝器件。这是用来当检测到有缺陷的元件来选择冗余元件。每个有缺陷的行或列的地址码（A0，An）的被记录在存储器单元（ELFO，ELFm），其包括两个小区（COO，Cioo）重新编码的数量和它的补码的列。当存储器单元被读出，适当的细胞通过激活与当前所选择的，撇开那些已知为有缺陷的。

6. 发明公开

EP0472209A3 Semiconductor memory device having redundant circuit 失效
标题翻译：具有冗余电路的半导体存储器件
公开(公告)号：EP0472209A3
公开(公告)日：1992-12-23
申请号：EP91114171.1
申请日：1991-08-23
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Ogihara, Masaki, c/o Intellectual Prop. Division
IPC分类号： G06F11/20
CPC分类号： G11C29/781
摘要： An output of a column redundant circuit (20) is supplied to one spare column selection line (SCDL). The spare column selection line (SCDL) is provided to select the spare column line. The column redundant circuit (20) includes four spare column decoders (21-1 to 21-4) of the same number as that of the memory cell arrays which can be selected by the column selection line supplied with an output of a partial column decoder (11), and an OR gate (22) for deriving the logical sum of outputs of the four spare column decoders (21-1 to 21-4) and supplying the same to the spare column selection line (SCDL). An output of the OR gate (22) is supplied to a logic circuit (12) together with an output of the partial column decoder (11).

7. 发明授权

EP0087610B1 Random access memory arrangement with a word redundancy scheme 失效
标题翻译：随机访问存储器与WORD REDUNDANCY方案的布置
公开(公告)号：EP0087610B1
公开(公告)日：1989-05-31
申请号：EP83101060.8
申请日：1983-02-04
申请人： International Business Machines Corporation
发明人： Knepper, Ronald William , Ludlow, Peter Jason , Petrosky, Joseph Anthony, Jr.
IPC分类号： G06F11/20
CPC分类号： G11C29/781

8. 发明公开

EP0114763A2 Redundant rows in integrated circuit memories 失效
标题翻译：在存储器集成电路冗余行。
公开(公告)号：EP0114763A2
公开(公告)日：1984-08-01
申请号：EP84400068.7
申请日：1984-01-13
申请人： FAIRCHILD SEMICONDUCTOR CORPORATION
发明人： Venkateswaran, Kalyanasundaram
IPC分类号： G06F11/20
CPC分类号： G11C29/781
摘要： Decoding apparatus for an integrated circuit memory having normal rows of memory cells and at least one selectively connectable redundant second row of memory cells for being connected in place of one of the first rows, said apparatus including: a redundant decoder connected to each of the at least one redundant row, the redundant decoder including a plurality of selectable connections for creating an address for each of the at least one redundant row; a control signal generating circuit for generating a control signal of a first state until an address is supplied to the memory and of a second state if any of the at least one redundant row is selected by the address; and, another decoder connected to receive the control signal from the generating circuit for controlling the normal rows in response thereto.

9. 发明公开

EP1251525A1 Semiconductor memory device, system, and method of controlling accessing to memory 有权
标题翻译： Halbleiterspeicherbauelement， - 系统和Zugriffsverfahren
公开(公告)号：EP1251525A1
公开(公告)日：2002-10-23
申请号：EP02008850.6
申请日：2002-04-19
申请人： NEC CORPORATION
发明人： Shionoya, Shinichi
IPC分类号： G11C29/00
CPC分类号： G11C29/72 , G11C29/24 , G11C29/26 , G11C29/781
摘要： Test circuits 15 0 to 15 4 , which determine whether memory blocks 11 0 to 11 4 including at least one redundant block are defective, are included in the memory blocks, respectively, A decoding rule generating circuit 13 so generates a decoding rule that a defective block can not be accessed, and outputs the generated decoding rule as a decoding-rule signal RUL. Under the decoding rule, the redundant address decoder 14 decodes the address signal ADDR, to permit access to the memory blocks except the defective block(s).
摘要翻译：确定包括至少一个冗余块的存储器块110至114的故障的测试电路150至154分别被包括在存储块中。解码规则生成电路13因此生成缺陷块不能是的解码规则并且将所生成的解码规则作为解码规则信号RUL输出。在解码规则下，冗余地址解码器14解码地址信号ADDR，以允许访问除了有缺陷的块之外的存储块。

10. 发明授权

EP0675441B1 Dispositif matriciel de fusibles de redondance pour mémoire intégrée et procédé de mise en oeuvre 失效
标题翻译：冗余熔丝阵列用于它的操作集成存储器和方法
公开(公告)号：EP0675441B1
公开(公告)日：1999-06-02
申请号：EP95400607.8
申请日：1995-03-20
申请人： STMicroelectronics S.A.
发明人： Rouy, Olivier , Gaultier, Jean-Marie
IPC分类号： G06F11/20
CPC分类号： G11C29/781

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