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1. 发明授权

EP0333207B1 Mask rom with spare memory cells 失效
标题翻译：面膜有备用存储单元ROM
公开(公告)号：EP0333207B1
公开(公告)日：1997-06-11
申请号：EP89104787.0
申请日：1989-03-17
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Takizawa, Makoto c/o Patent Division , Iwase, Taira c/o Patent Division , Asano, Masamichi c/o Patent Division , Arime, Yasunori c/o Patent Division
IPC分类号： G06F11/20 , G11C7/00 , G11C17/10
CPC分类号： G11C29/822

2. 发明授权

EP0440265B1 Nonvolatile semiconductor memory device 失效
标题翻译：半导体只读存储器装置。
公开(公告)号：EP0440265B1
公开(公告)日：1994-09-07
申请号：EP91104554.0
申请日：1988-01-29
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Maruyama, Tadashi, c/o Patent Division , Wada, Yukio, c/o Patent Division , Shigematsu, Tomohisa, c/o Patent Division , Suzuki, Yasoji, c/o Patent Division , Yoshizawa, Makoto
IPC分类号： G11C16/04 , H01L27/115
CPC分类号： H01L27/115 , G11C16/0433

3. 发明授权

EP0230385B1 Semiconductor memory 失效
公开(公告)号：EP0230385B1
公开(公告)日：1993-12-29
申请号：EP87300389.1
申请日：1987-01-16
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Ogihara, Masaki c/o Patent Division , Okada, Yoshio c/o Patent Division , Fujii, Shuso c/o Patent Division
IPC分类号： G11C11/409 , G11C11/24
CPC分类号： G11C11/4094

4. 发明授权

EP0205104B1 Intermediate potential generation circuit 失效
标题翻译：中间电位发生电路
公开(公告)号：EP0205104B1
公开(公告)日：1991-12-18
申请号：EP86107643.8
申请日：1986-06-05
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Okada, Yoshio c/o Patent Division , Shimizu, Mitsuru
IPC分类号： H03H11/24 , G05F3/24
CPC分类号： G05F3/24 , H03H11/245

5. 发明授权

EP0280883B1 Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：EP0280883B1
公开(公告)日：1991-10-23
申请号：EP88101335.3
申请日：1988-01-29
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Maruyama, Tadashi c/o Patent Division , Wada, Yukio c/o Patent Division , Suzuki, Yasoji c/o Patent Division , Shigematsu, Tomohisa c/o Patent Division , Yoshizawa, Makoto c/o Patent Division
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/26 , G11C16/0433 , G11C16/10

6. 发明公开

EP0292641A3 Output buffer of MOS semiconductor integrated circuit 失效
标题翻译： MOS半导体集成电路的输出缓冲器
公开(公告)号：EP0292641A3
公开(公告)日：1991-01-09
申请号：EP88101710.7
申请日：1988-02-05
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Kinugasa, Masanori c/o Patent Division , Shimazaki, Kenichiro , Tanaka, Fuminari c/o Patent Division
IPC分类号： H01L27/02 , H01L23/52 , H03K19/094
CPC分类号： H03K19/00361 , H01L23/528 , H01L27/11898 , H01L2924/0002 , H03K5/133 , H03K2005/00221 , H01L2924/00
摘要： An output buffer of a MOS semiconductor integrated circuit includes MOSFETs (Q11 to Q1n; Q21 to Q2n) constituting at least one of a driving and a load circuit, a resistive region (43; 44) connected to the gate electrodes (15-1 to 15-n; 20-1 to 20-n) of the MOSFETs (Q11 to Q1n; Q21 to Q2n), an insulation layer (10) formed on the gate wiring layers (15-1 to 15-n; 20-1 to 20-n) and the resistive regions (43; 44), and a metal wiring layer (23A) for signal input, formed on the insulation layer (10) and connected to the resistive regions (43; 44) via a contact hole (45; 46) formed in the insulation layer (10). The width of the contact hole (45; 46) is set so as to be less than the interval between any adjacent two of the gate wiring layers (15-1 to 15-n; 20-1 to 20-n). The metal wiring layer (23A) to which an input signal is supplied is connected to part of the resistive region (43; 44), so that the gate wiring lengths from the metal wiring layer (23A) to the gate electrodes of the MOSFETs (Q11 to Q1n; Q21 to Q2n) will be set to different values. Thus, an input signal is supplied to the MOSFETs (Q11 to Q1n; Q21 to Q2n) with different delay times to operate the MOSFETs (Q11 to Q1n; Q21 to Q2n) at different timings, causing the variation of an output signal to be gentle.

7. 发明公开

EP0318929A3 Retriggerable multivibrator 失效
标题翻译：可重复的多功能一体机
公开(公告)号：EP0318929A3
公开(公告)日：1990-06-27
申请号：EP88119901.2
申请日：1988-11-29
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Fujii, Shinji c/o Patent Division , Tsuchiya, Ikuo , Kasai, Kazuhiko
IPC分类号： H03K3/033
CPC分类号： H03K3/033
摘要： A retriggable multivibrator is disclosed which comprises a first delay circuit (3) connected for delaying an input signal a predetermined time, a second delay circuit (5) connected to receive an output of the first delay circuit and having a set or a rest function, a flip-flop circuit (2) connected to be set or reset in accordance with an input signal and output signal which comes from the second delay circuit (5) and control circuit (6) connected to detect a reentry of an input signal within a predetermined delay time of the first and second delay circuits and to set or reset the second delay circuit.

8. 发明公开

EP0331206A2 Semiconductor integrated circuit device of multilayer interconnection structure 失效
标题翻译： Integrierte Schaltungshalbleiteranordnung mit Mehrschicht-Verbindungsstruktur。
公开(公告)号：EP0331206A2
公开(公告)日：1989-09-06
申请号：EP89103926.5
申请日：1989-03-06
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Kato, Toshiya , Enkaku, Motohiro
IPC分类号： H01L23/52 , H01L23/48
CPC分类号： H01L23/5286 , H01L23/5226 , H01L24/06 , H01L2224/05554 , H01L2924/14 , H01L2924/00
摘要： A semiconductor integrated circuit device of multilayer interconnection structure includes a pad (34) formed of a multilayer interconnection layer (52, 54). The power source pad (34) is connected to a power source interconnection layer (33) via a lead-out interconnection layer (35) which is formed of the same multilayer interconnection layer (52, 54) as that used to form the power source pad (34).
摘要翻译：多层互连结构的半导体集成电路器件包括由多层互连层（52,54）形成的焊盘（34）。电源焊盘（34）经由引出互连层（35）连接到电源互连层（33），引出互连层（35）由与用于形成电源的相同的多层互连层（52,54）形成垫（34）。

9. 发明公开

EP0209844A3 Flip-flop circuit 失效
标题翻译：触发器电路
公开(公告)号：EP0209844A3
公开(公告)日：1989-08-23
申请号：EP86109745.9
申请日：1986-07-16
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Magome, Koichi c/o Patent Division , Toda, Haruki c/o Patent Division , Koinuma, Hiroyuki c/o Patent Division , Sahara, Hiroshi c/o Patent Division , Suzuki, Kiminobu c/o Patent Division , Ohshima, Shigeo c/o Patent Division , Komatsu, Kenji c/o Patent Division
IPC分类号： H03K3/356 , G11C8/00
CPC分类号： H03K3/356026 , G11C8/06
摘要： A flip-flop circuit has a power terminal (VDD) set at 5 V, first and second output terminals (OUT, OUT ), a latch section (20) for charging one of the first and second terminals (OUT, OUT ) to 5 V and discharging the other one of the first and second terminals (OUT, OUT ) to 0 V in accordance with an input signal ( , - ), a first MOS transistor (Q6) having a current path connected between the power and first output terminals (VDD, OUT), a second MOS transistor (Q8) for charging the gate of the first MOS transistor (Q6) while the potential of the second terminal ( OUT ) is changed from 5 V to 0 V, and a capacitor (C4) for bootstrapping the gate potential of the first MOS transistor (Q6) to turn on the first MOS transistor. The flip-flop circuit further includes a third MOS transistor (Q10), having a current path connected between the gate of the first MOS transistor (Q6) and the first output terminal (OUT) and a gate connected to the first output terminal (OUT), for charging the gate of the first MOS transistor (Q6) when the gate potential of the first MOS transistor (Q6) is dropped a predetermined level in comparison with that of the first output terminal (OUT).
摘要翻译：触发器电路具有设定为5V的电源端子（VDD），第一和第二输出端子（OUT，OUT），用于对第一和第二端子（OUT，OUT）中的一个端子（5）充电的锁存部件（20） V，并且根据输入信号（， - ）将第一和第二端子（OUT，OUT）中的另一个放电至0V，第一MOS晶体管（Q6）具有连接在电源和第一输出端子（VDD，OUT）;第二MOS晶体管（Q8），用于在第二端子（OUT）的电位从5V变为0V的同时对第一MOS晶体管（Q6）的栅极充电;以及电容器（C4）用于引导第一MOS晶体管（Q6）的栅极电势以导通第一MOS晶体管。触发器电路还包括第三MOS晶体管（Q10），其具有连接在第一MOS晶体管（Q6）的栅极和第一输出端子（OUT）之间的电流路径以及连接到第一输出端子（OUT）的栅极），当第一MOS晶体管（Q6）的栅极电位与第一输出端子（OUT）的栅极电位相比下降预定电平时，用于给第一MOS晶体管（Q6）的栅极充电。

10. 发明公开

EP0325105A1 Multiport memory 失效
标题翻译：多端口，斯派克。
公开(公告)号：EP0325105A1
公开(公告)日：1989-07-26
申请号：EP89100100.0
申请日：1989-01-04
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Ohshima, Shigeo , Toda, Haruki , Ikawa, Tatsuo
IPC分类号： G11C7/00 , G11C8/00 , G06F12/00
CPC分类号： G11C7/1075
摘要： This invention provides a multiport memory including a storage section A having bit lines BL and BL , a word line WL, a data transfer gate φDT, and a dynamic memory cell Cs, and a serial port B having a serial access function in a column direction of the storage section, wherein the memory includes a circuit for disabling a word line signal WL for selecting one word line under the conditions that a row address strobe signal RAS is raised in a transfer cycle in which data held by the memory cell is transferred to the serial port, and that the data transfer to the serial port is completed by the data transfer gate φDT.
摘要翻译：本发明提供一种多端口存储器，其包括具有位线BL和BL的存储部分A，字线WL，数据传送门极DT和动态存储单元Cs，以及具有串行访问功能的串行端口B 存储部分的方向，其中存储器包括一个电路，用于禁止字线信号WL用于在传输周期中在存储单元保存的数据被传输的传输周期中提高行地址选通信号RAS的条件下选择一个字线到串行端口，并且数据传输到串行端口的数据传输门phi DT完成。

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