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1. 发明公开

EP0223994A2 Method of forming a sub-micrometer trench structure on a semiconductor substrate 失效
标题翻译：一种用于半导体衬底上制备亚微米严重结构的过程。
公开(公告)号：EP0223994A2
公开(公告)日：1987-06-03
申请号：EP86114062.2
申请日：1986-10-10
申请人： International Business Machines Corporation
发明人： Ogura, Seiki , Riseman, Jacob , Rovedo, Nivo , Schulz, Ronald Norman
IPC分类号： H01L21/00 , H01L21/76
CPC分类号： H01L21/0337 , H01L21/0332 , H01L21/31116 , Y10S438/945 , Y10S438/951
摘要： In the process of sidewall image transfer, a vertical step is etched in some material and then a conformal layer of some other material is deposited over the step. By reactive ion etching the conformal material can be anisotropically etched which results in a sidewall spacer of the second material on the vertical surfaces of the step material. By removing the step material, the free standing spacer can then be used as a mask. One area in which improvement is desired is in the selectivity of the etch of the spacer to the material immediately below it. Because of the limited number of materials and reactive ion etching gases it is difficult to avoid an etch in the underlying layer as the sidewall spacer is formed. A suitable etch stop is employed beneath the step material to avoid the problem. Because of the usual technology, the spacer material is plasma deposited silicon nitride and the step material is photoresist. Polysilicon, aluminum or similar metal is employed as an etch stop, since it is not affected by a CF₄ based gas which is used to form the spacer.

2. 发明公开

EP0577537A1 Confined water fixture for holding wafers undergoing chemical-mechanical polishing 失效
标题翻译：用于保持晶片水垫设备，所述化学机械抛光经受。
公开(公告)号：EP0577537A1
公开(公告)日：1994-01-05
申请号：EP93480043.4
申请日：1993-04-19
申请人： International Business Machines Corporation
发明人： Currie, James Edward , Schulz, Ronald Norman , Ticknor, Adam Dan
IPC分类号： B24B37/04 , B23Q3/08
CPC分类号： B24B37/30 , B23Q3/082
摘要： A wafer polishing fixture is disclosed containing a first liquid film (6) confined by a non-porous but flexible enclosure (2,8) for distributing evenly the applied polishing forces across the surface of a wafer (7) supported by the confined liquid (6).
The fixture comprises a flexible, non-porous template (2) with a pocket (5) for receiving a wafer (7) to be polished. A washer (4) is placed between a carrier (3) and the template pocket (5). A film of water (6) fills the bottom of the pocket (5) and is confined with the aid of the washer (4) and by an overlying porous pad (9) extending across the pocket (5) and having a non-porous sheath (8) facing the liquid (6). A second liquid film (10) saturates and covers the upper surface of the pad (9). The wafer (7) to be polished floats upon the second liquid film (10) within the pocket (5).
摘要翻译：由密闭液体的晶片抛光固定装置游离缺失盘用于跨晶片的表面均匀地分布在应用抛光力包含由非多孔，但柔性外壳（2.8）限制的第一液体成膜（6）（7）的支持（ 6）。该夹具包括具有凹部（5）的柔性，非多孔模板（2），用于接收晶片（7），以进行抛光。垫圈（4）的载体（3）和所述模板袋（5）之间放置。电影的水（6）填充槽（5）的底部，并且被限制与所述垫圈（4）的辅助下，并通过在覆多孔垫（9）延伸穿过槽（5）和具有非多孔面对液体护套（8）（6）。第二液体电影（10）的饱和物和覆盖所述衬垫（9）的上表面上。晶片（7），以在该容器内被研磨在第二液体电影（10）浮子（5）。

3. 发明公开

EP0148340A1 Ion etching process for deep trench etching multi-layer semiconductor substrates 失效
标题翻译：一种用于在多层半导体衬底的深沟槽的离子蚀刻法。
公开(公告)号：EP0148340A1
公开(公告)日：1985-07-17
申请号：EP84112632.9
申请日：1984-10-19
申请人： International Business Machines Corporation
发明人： Lai, Fang-shi Jordan , Schulz, Ronald Norman
IPC分类号： H01L21/306
CPC分类号： H01L21/3065
摘要： This invention relates to a process for forming deep trenches in semiconductor substrates by Reactive Ion Etching and more particularly relates to an etching process which prevents lateral etching or "blooming" in a heavily doped semiconductor region which is sandwiched by upper and lower lightly doped regions of semiconductor. Still more particularly it relates to an RIE process wherein the upper region is reactively ion etched in an atmosphere of CC 2 F 2 and argon to at least a portion of the thickness of the upper region and wherein any remaining thickness of the upper region, the heavily doped region and at least a portion of the lower region are reactively ion etched in an atmosphere of CCl 2 F 2 and oxygen to provide a trench with uniform sidewalls.

4. 发明授权

EP0570043B1 Bicmos SOI wafer having thin and thick SOI regions of silicon 失效
标题翻译：对于BICMOS SOI晶片具有薄和厚的SOI区域的硅
公开(公告)号：EP0570043B1
公开(公告)日：1996-07-24
申请号：EP93201175.2
申请日：1993-04-22
申请人： International Business Machines Corporation
发明人： Buti, Taqi Nasser , Hsu, Louis Lu-Chen , Jost, Mark Edwin , Ogura Seiki NMN , Schulz, Ronald Norman
IPC分类号： H01L21/82 , H01L21/76 , H01L27/06 , H01L21/304
CPC分类号： H01L21/76264 , H01L21/76275 , H01L21/76281 , H01L21/76286 , H01L21/8249 , H01L29/78657 , Y10S148/009 , Y10S438/959

5. 发明公开

EP0570043A3 Bicmos SOI wafer having thin and thick SOI regions of silicon 失效
标题翻译： BICMOS SOI薄膜有薄层和硅片硅层
公开(公告)号：EP0570043A3
公开(公告)日：1993-11-24
申请号：EP93201175.2
申请日：1993-04-22
申请人： International Business Machines Corporation
发明人： Buti, Taqi Nasser , Hsu, Louis Lu-Chen , Jost, Mark Edwin , Ogura Seiki NMN , Schulz, Ronald Norman
IPC分类号： H01L21/82 , H01L21/76 , H01L27/06 , H01L21/304
CPC分类号： H01L21/76264 , H01L21/76275 , H01L21/76281 , H01L21/76286 , H01L21/8249 , H01L29/78657 , Y10S148/009 , Y10S438/959
摘要： A SOI BiCMOS integrated circuit has CMOS devices formed in a thin epitaxial layer of 1000Å and bipolar devices formed in a thick epitaxial layer of 1µm, the two thicknesses being formed by a process in which a set of oxide islands are formed on a first wafer; an epitaxial layer is grown from bipolar silicon regions up and over the islands in a step that forms the bottom portion of the bipolar regions; the first wafer is inverted and oxide- bonded to a second wafer with the newly grown epitaxial layer below the islands so that the new top surface has a high quality epitaxial layer; excess silicon is removed from the new surface and the surface is polished to a thickness of 1000Å over the islands by use of a nitride polish stop layer, leaving a thick layer of epitaxial silicon of 1µm in the bipolar regions and a 1000Å thick layer of epitaxial silicon in the CMOS regions.

6. 发明授权

EP0148340B1 Ion etching process for deep trench etching multi-layer semiconductor substrates 失效
标题翻译：深层蚀刻多层半导体衬底的离子蚀刻工艺
公开(公告)号：EP0148340B1
公开(公告)日：1988-01-07
申请号：EP84112632.9
申请日：1984-10-19
申请人： International Business Machines Corporation
发明人： Lai, Fang-shi Jordan , Schulz, Ronald Norman
IPC分类号： H01L21/306
CPC分类号： H01L21/3065

7. 发明授权

EP0577537B1 Confined water fixture for holding wafers undergoing chemical-mechanical polishing 失效
标题翻译：水缓冲装置经受保持晶片，所述化学机械抛光
公开(公告)号：EP0577537B1
公开(公告)日：1996-06-26
申请号：EP93480043.4
申请日：1993-04-19
申请人： International Business Machines Corporation
发明人： Currie, James Edward , Schulz, Ronald Norman , Ticknor, Adam Dan
IPC分类号： B24B37/04 , B23Q3/08
CPC分类号： B24B37/30 , B23Q3/082

8. 发明公开

EP0570043A2 Bicmos SOI wafer having thin and thick SOI regions of silicon 失效
标题翻译： SOI-ScheibefürBICMOS mitdünnenund dicken SOI-Siliziumgebieten。
公开(公告)号：EP0570043A2
公开(公告)日：1993-11-18
申请号：EP93201175.2
申请日：1993-04-22
申请人： International Business Machines Corporation
发明人： Buti, Taqi Nasser , Hsu, Louis Lu-Chen , Jost, Mark Edwin , Ogura Seiki NMN , Schulz, Ronald Norman
IPC分类号： H01L21/82 , H01L21/76 , H01L27/06 , H01L21/304
CPC分类号： H01L21/76264 , H01L21/76275 , H01L21/76281 , H01L21/76286 , H01L21/8249 , H01L29/78657 , Y10S148/009 , Y10S438/959
摘要： A SOI BiCMOS integrated circuit has CMOS devices formed in a thin epitaxial layer of 1000Å and bipolar devices formed in a thick epitaxial layer of 1µm, the two thicknesses being formed by a process in which a set of oxide islands are formed on a first wafer; an epitaxial layer is grown from bipolar silicon regions up and over the islands in a step that forms the bottom portion of the bipolar regions; the first wafer is inverted and oxide- bonded to a second wafer with the newly grown epitaxial layer below the islands so that the new top surface has a high quality epitaxial layer; excess silicon is removed from the new surface and the surface is polished to a thickness of 1000Å over the islands by use of a nitride polish stop layer, leaving a thick layer of epitaxial silicon of 1µm in the bipolar regions and a 1000Å thick layer of epitaxial silicon in the CMOS regions.
摘要翻译： SOI BiCMOS集成电路具有形成在1000个ANGSTROM的薄外延层中的CMOS器件和形成在1μm的厚外延层中的双极器件，两个厚度通过其中一组氧化物岛形成在第一片; 在形成双极区域的底部的步骤中，从双极硅区域向上和在岛上生长外延层; 第一晶片被倒置并且氧化物结合到第二晶片，其中新生长的外延层在岛下方，使得新的顶表面具有高质量的外延层; 从新表面去除多余的硅，并且通过使用氮化物抛光停止层在岛上将表面抛光至1000的厚度，在双极性区域中留下1μm厚的外延硅的外延层，以及1000 ANGSTROM 在CMOS区域中厚的外延硅层。

9. 发明授权

EP0223994B1 Method of forming a sub-micrometer trench structure on a semiconductor substrate 失效
标题翻译：在半导体基板上形成副微结构的结构的方法
公开(公告)号：EP0223994B1
公开(公告)日：1993-03-17
申请号：EP86114062.2
申请日：1986-10-10
申请人： International Business Machines Corporation
发明人： Ogura, Seiki , Riseman, Jacob , Rovedo, Nivo , Schulz, Ronald Norman
IPC分类号： H01L21/00 , H01L21/76
CPC分类号： H01L21/0337 , H01L21/0332 , H01L21/31116 , Y10S438/945 , Y10S438/951

10. 发明公开

EP0223994A3 Method of forming a sub-micrometer trench structure on a semiconductor substrate 失效
标题翻译：防止非均衡蚀刻的方法在低分辨率范围内的图像转印
公开(公告)号：EP0223994A3
公开(公告)日：1989-10-25
申请号：EP86114062.2
申请日：1986-10-10
申请人： International Business Machines Corporation
发明人： Ogura, Seiki , Riseman, Jacob , Rovedo, Nivo , Schulz, Ronald Norman
IPC分类号： H01L21/00 , H01L21/76
CPC分类号： H01L21/0337 , H01L21/0332 , H01L21/31116 , Y10S438/945 , Y10S438/951
摘要： In the process of sidewall image transfer, a vertical step is etched in some material and then a conformal layer of some other material is deposited over the step. By reactive ion etching the conformal material can be anisotropically etched which results in a sidewall spacer of the second material on the vertical surfaces of the step material. By removing the step material, the free standing spacer can then be used as a mask. One area in which improvement is desired is in the selectivity of the etch of the spacer to the material immediately below it. Because of the limited number of materials and reactive ion etching gases it is difficult to avoid an etch in the underlying layer as the sidewall spacer is formed. A suitable etch stop is employed beneath the step material to avoid the problem. Because of the usual technology, the spacer material is plasma deposited silicon nitride and the step material is photoresist. Polysilicon, aluminum or similar metal is employed as an etch stop, since it is not affected by a CF₄ based gas which is used to form the spacer.

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