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1. 发明公开

EP3050103A1 NON-PLANAR I/O AND LOGIC SEMICONDUCTOR DEVICES HAVING DIFFERENT WORKFUNCTION ON COMMON SUBSTRATE 有权
标题翻译：具有不同功函数的非平面的I / O和逻辑半导体器件上的共用基板
公开(公告)号：EP3050103A1
公开(公告)日：2016-08-03
申请号：EP13894123.2
申请日：2013-09-27
申请人： Intel Corporation
发明人： OLAC-VAW, Roman W. , HAFEZ, Walid M. , JAN, Chia-Hong , LIU, Pei-Chi
IPC分类号： H01L27/00
摘要： Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.
摘要翻译：非平面I /描述了具有公共衬底上不同的功函数和制造非平面的I / O，并具有共同的基板上的不同的功函数的逻辑半导体器件的方法O和逻辑半导体器件。对于实施例，半导体结构包括一个以上的基板设置在第一半导体器件。所述第一半导体器件具有导电类型，并且包括具有第一功函数的栅极电极。因此，该半导体结构包括在基板上方设置的第二半导体器件。该第二半导体器件具有导电类型，并且包括具有第二的，不同的功函数的栅极电极。

2. 发明公开

EP3161872A1 MULTI-GATE TRANSISTOR WITH VARIABLY SIZED FIN 有权转让
标题翻译：多门式晶体管麻醉机变压器RIPEM
公开(公告)号：EP3161872A1
公开(公告)日：2017-05-03
申请号：EP14896232.7
申请日：2014-06-27
申请人： Intel Corporation
发明人： NIDHI, Nidhi , JAN, Chia-Hong , OLAC-VAW, Roman W. , CHANG, Hsu-Yu , DIAS, Neville L. , HAFEZ, Walid M. , RAMASWAMY, Rahul
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823412 , H01L21/26586 , H01L21/823418 , H01L21/823431 , H01L27/0886 , H01L29/0847 , H01L29/1037 , H01L29/42368 , H01L29/785 , H01L29/7851 , H01L29/7856
摘要： An embodiment includes an apparatus comprising: a non-planar transistor comprising a fin, the fin including a source region having a source region width and a source region height, a channel region having a channel region width and a channel region height, a drain region having a drain width and a drain height, and a gate dielectric formed on a sidewall of the channel region; wherein the apparatus includes at least one of (a) the channel region width being wider than the source region width, and (b) the gate dielectric including a first gate dielectric thickness at a first location and a second gate dielectric thickness at a second location, the first and second locations located at an equivalent height on the sidewall and the first and second gate dielectrics thicknesses being unequal to one another. Other embodiments are described herein.
摘要翻译：一个实施例包括一种装置，包括：非平面晶体管，包括鳍片，所述鳍片包括源极区域宽度和源极区域高度的源极区域，具有沟道区域宽度和沟道区域高度的沟道区域，漏极区域具有漏极宽度和漏极高度，以及形成在沟道区域的侧壁上的栅极电介质; 其中所述装置包括以下中的至少一个：（a）所述沟道区宽度宽于所述源极区宽度，以及（b）所述栅极电介质包括在第一位置处的第一栅极电介质厚度和在第二位置处的第二栅极电介质厚度位于侧壁上的等效高度的第一和第二位置以及第一和第二栅极电介质厚度彼此不相等。本文描述了其它实施例。

3. 发明公开

EP3161871A1 NON-LINEAR FIN-BASED DEVICES 有权
标题翻译：非线性基于FIN的器件
公开(公告)号：EP3161871A1
公开(公告)日：2017-05-03
申请号：EP14896226.9
申请日：2014-06-27
申请人： Intel Corporation
发明人： DIAS, Neville L. , JAN, Chia-Hong , HAFEZ, Walid M. , OLAC-VAW, Roman W. , CHANG, Hsu-Yu , CHANG, Ting , RAMASWAMY, Rahul , LIU, Pei-Chi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7853 , H01L21/823412 , H01L21/823431 , H01L21/845 , H01L27/0886 , H01L27/1211 , H01L29/0657 , H01L29/0847 , H01L29/1033 , H01L29/41791 , H03D7/1425 , H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D7/165
摘要： An embodiment includes an apparatus comprising: a non-planar fm having first, second, and third portions each having major and minor axes and each being monolithic with each other; wherein (a) the major axes of the first, second, and third portions are parallel with each other, (b) the major axes of the first and second portions are non-collinear with each other, (c) each of the first, second, and third portions include a node of a transistor selected from the group comprising source, drain, and channel, (e) the first, second, and third portions comprise at least one fmFET. Other embodiments are described herein.
摘要翻译：一个实施例包括一种装置，该装置包括：具有第一部分，第二部分和第三部分的非平面fm，每个部分具有长轴和短轴并且每个部分彼此是整体的; 其中（a）第一部分，第二部分和第三部分的长轴彼此平行，（b）第一部分和第二部分的长轴相互不共线，（c）第一部分，第二部分和第三部分包括从包括源极，漏极和沟道的组中选择的晶体管的节点，（e）第一部分，第二部分和第三部分包括至少一个fmFET。这里描述了其他实施例。

4. 发明公开

EP3832710A1 NON-PLANAR I/O AND LOGIC SEMICONDUCTOR DEVICES HAVING DIFFERENT WORKFUNCTION ON COMMON SUBSTRATE 有权
公开(公告)号：EP3832710A1
公开(公告)日：2021-06-09
申请号：EP20216602.1
申请日：2013-09-27
申请人： INTEL Corporation
发明人： OLAC-VAW, Roman W. , HAFEZ, Walid M. , JAN, Chia-Hong , LIU, Pei-Chi
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/84 , H01L21/28 , H01L29/66 , H01L27/088 , H01L27/12
摘要： Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

5. 发明授权

EP3050103B1 NON-PLANAR I/O AND LOGIC SEMICONDUCTOR DEVICES HAVING DIFFERENT WORKFUNCTION ON COMMON SUBSTRATE 有权
公开(公告)号：EP3050103B1
公开(公告)日：2020-03-18
申请号：EP13894123.2
申请日：2013-09-27
申请人： Intel Corporation
发明人： OLAC-VAW, Roman W. , HAFEZ, Walid M. , JAN, Chia-Hong , LIU, Pei-Chi
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/84 , H01L21/28 , H01L29/66 , H01L27/088 , H01L27/12

6. 发明公开

EP3454365A1 NON-PLANAR I/O AND LOGIC SEMICONDUCTOR DEVICES HAVING DIFFERENT WORKFUNCTION ON COMMON SUBSTRATE 有权
公开(公告)号：EP3454365A1
公开(公告)日：2019-03-13
申请号：EP18195368.8
申请日：2013-09-27
申请人： INTEL Corporation
发明人： OLAC-VAW, Roman W. , HAFEZ, Walid M. , JAN, Chia-Hong , LIU, Pei-Chi
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/84 , H01L21/28 , H01L29/66 , H01L27/088 , H01L27/12
摘要： Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

7. 发明授权

EP3161871B1 NON-LINEAR FIN-BASED DEVICES 有权
公开(公告)号：EP3161871B1
公开(公告)日：2020-07-22
申请号：EP14896226.9
申请日：2014-06-27
申请人： Intel Corporation
发明人： DIAS, Neville L. , JAN, Chia-Hong , HAFEZ, Walid M. , OLAC-VAW, Roman W. , CHANG, Hsu-Yu , CHANG, Ting , RAMASWAMY, Rahul , LIU, Pei-Chi
IPC分类号： H01L29/78 , H01L21/336 , H03D7/14 , H03D7/16 , H01L21/8234 , H01L27/088 , H01L21/84 , H01L29/417 , H01L27/12

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