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1. 发明公开

EP0902358A2 Division circuit and method 失效
标题翻译： Dividierschaltung und -verfahren
公开(公告)号：EP0902358A2
公开(公告)日：1999-03-17
申请号：EP98120014.0
申请日：1992-06-22
申请人： Hitachi, Ltd. , HITACHI ULSI ENGINEERING CORPORATION , HITACHI MICROCOMPUTER SYSTEM LTD.
发明人： Kawasaki, Shumpei , Sakakibara, Eiji , Fukada, Kaoru , Yamazaki, Takanaga , Akao, Yasushi , Baba, Shiro , Kihara, Toshimasa , Kurakazu, Keiichi , Tsukamoto, Takashi , Masumura, Shigeki , Tawara, Yasuhiro , Kashiwagi, Yugo , Fujita, Shuya , Ishida, Katsuhiko , Sawa, Noriko , Asano, Yoichi , Chaki, Hideaki , Sugawara, Tadahiko , Kainaga, Masahiro , Noguchi, Kouki B-11, Hitachitennouueshataku , Watabe, Mitsuru
IPC分类号： G06F7/52
CPC分类号： G06F7/535 , G06F9/30 , G06F9/3001 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/322 , G06F9/324 , G06F9/3557 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3867 , G06F2207/5352
摘要： A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting an instruction format of a fixed length of 2 n bits which is smaller than the length of the maximum data word fed to instruction execution means. The control of the coded division is executed by noting the code bits.
摘要翻译：采用通用寄存器方法的微型计算机MCU能够使用效率低的系统成本具有小的程序容量或高程序存储器，同时具有简化指令解码的优点，如具有固定长度指令格式的RISC机器通过采用小于馈送到指令执行装置的最大数据字的长度的2 个固定长度的指令格式。编码分割的控制是通过注意码位执行的。

2. 发明公开

EP0902361A2 Single-chip CPU and microcomputer 失效
标题翻译：单片机
公开(公告)号：EP0902361A2
公开(公告)日：1999-03-17
申请号：EP98120015.7
申请日：1992-06-22
申请人： Hitachi, Ltd. , HITACHI ULSI ENGINEERING CORPORATION , HITACHI MICROCOMPUTER SYSTEM LTD.
发明人： Kawasaki, Shumpei , Sakakibara, Eiji , Fukada, Kaoru , Yamazaki, Takanaga , Akao, Yasushi , Baba, Shiro , Kihara, Toshimasa , Kurakazu, Keiichi , Tsukamoto, Takashi , Masumura, Shigeki , Tawara, Yasuhiro , Kashiwagi, Yugo , Fujita, Shuya , Ishida, Katsuhiko , Sawa, Noriko , Asano, Yoichi , Chaki, Hideaki , Sugawara, Tadahiko , Kainaga, Masahiro , Noguchi, Kouki B-11, Hitachitennouueshataku , Watabe, Mitsuru
IPC分类号： G06F9/38 , G06F15/78
CPC分类号： G06F7/535 , G06F9/30 , G06F9/3001 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/322 , G06F9/324 , G06F9/3557 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3867 , G06F2207/5352
摘要： A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting an instruction format of a fixed length of 2 n bits which is smaller than the length of the maximum data word fed to instruction execution means. The control of the coded division is executed by noting the code bits.

3. 发明公开

EP0525375A3 Microcomputer and divider circuit 失效
标题翻译：微型计算机和分路器电路
公开(公告)号：EP0525375A3
公开(公告)日：1993-04-21
申请号：EP92110517.7
申请日：1992-06-22
申请人： HITACHI, LTD. , HITACHI ULSI ENGINEERING CORPORATION , HITACHI MICROCOMPUTER SYSTEM LTD.
发明人： Kawasaki, Shumpei , Sakakibara, Eiji , Fukada, Kaoru , Yamazaki, Takanaga , Akao, Yasushi , Baba, Shiro , Kihara, Toshimasa , Kurakazu, Keiichi , Tsukamoto, Takashi , Masumura, Shigeki , Tawara, Yasuhiro , Kashiwagi, Yugo , Fujita, Shuya , Ishida, Katsuhiko , Sawa, Noriko , Asano, Yoichi , Chaki, Hideaki , Sugawara, Tadahiko , Kainaga, Masahiro , Noguchi, Kouki , Watabe, Mitsuru
IPC分类号： G06F9/38
CPC分类号： G06F7/535 , G06F9/30 , G06F9/3001 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/322 , G06F9/324 , G06F9/3557 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3867 , G06F2207/5352
摘要： RISC-type microprocessor has a fixed struction lenght of 2 n bits, whilst the data use size is 2 m bits,where m is greater than or equal to n.

4. 发明公开

EP0525375A2 Microcomputer and divider circuit 失效
标题翻译： Mikrocomputer和Teilerschaltung。
公开(公告)号：EP0525375A2
公开(公告)日：1993-02-03
申请号：EP92110517.7
申请日：1992-06-22
申请人： HITACHI, LTD. , HITACHI ULSI ENGINEERING CORPORATION , HITACHI MICROCOMPUTER SYSTEM LTD.
发明人： Kawasaki, Shumpei , Sakakibara, Eiji , Fukada, Kaoru , Yamazaki, Takanaga , Akao, Yasushi , Baba, Shiro , Kihara, Toshimasa , Kurakazu, Keiichi , Tsukamoto, Takashi , Masumura, Shigeki , Tawara, Yasuhiro , Kashiwagi, Yugo , Fujita, Shuya , Ishida, Katsuhiko , Sawa, Noriko , Asano, Yoichi , Chaki, Hideaki , Sugawara, Tadahiko , Kainaga, Masahiro , Noguchi, Kouki , Watabe, Mitsuru
IPC分类号： G06F9/38
CPC分类号： G06F7/535 , G06F9/30 , G06F9/3001 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/322 , G06F9/324 , G06F9/3557 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3867 , G06F2207/5352
摘要： RISC-type microprocessor has a fixed struction lenght of 2 n bits, whilst the data use size is 2 m bits,where m is greater than or equal to n.
摘要翻译： RISC型微处理器的固定结构长度为2 n位，数据使用大小为2 m，m大于或等于n。

5. 发明公开

EP0740254A3 Microprocessor and method for setting up its peripheral functions 失效
标题翻译：微处理器和设置其外设功能的方法
公开(公告)号：EP0740254A3
公开(公告)日：1996-11-20
申请号：EP96112686.9
申请日：1990-12-07
申请人： HITACHI, LTD. , HITACHI ULSI ENGINEERING CORPORATION
发明人： Akao, Yasushi , Baba, Shiro , Miwa, Yoshiyuki , Sawase, Terumi , Sato, Yuji , Masumura, Shigeki
IPC分类号： G06F13/12 , G06F9/38 , G06F15/78
CPC分类号： G06F13/124 , G06F15/7814
摘要： A single chip microprocessor 1 comprises a CPU 2 and a sub-processor 5 for implementing peripheral functions of the microprocessor 1 by software. The sub-processor 5 includes electrically writable internal storage devices called a microprogram memory unit 13 and a sequence control memory unit 62 for storing the software. Peripheral functions to be implemented by the sub-processor 5 can be defined or modified by writing software into the memory units 13 and 62. Accordingly, the time it takes to define or modify the peripheral functions is the same as the time it takes to program the memory units 13 and 62. The sub-processor 5 also includes an execution unit 16 for executing a plurality of tasks and an address control circuit 14 for providing addresses to the microprogram memory unit 13 in addition to the microprogram memory unit 13 for providing microinstructions to the execution unit 16. The sequence control memory unit 62 is part of the address control circuit 14 which also includes a plurality of address registers MAR0 to MAR11. The sequence control memory unit 62 is used for storing information on what order the multiple address registers MAR0 to MAR11 are to be selected in sequentially. One of the address registers MAR0 to MAR11 is selected at every read cycle performed on the sequence control memory unit 62. A microaddress stored in the selected one of the address registers MAR0 to MAR11 is then supplied to the microprogram memory unit 13. Task null information can also be stored in the sequence control memory unit 62. The selection of one of the address registers MAR0 to MAR11 at every read cycle allows the sub-processor 5 to operate on an event driven basis.
摘要翻译：单片微处理器1包括一个CPU2和一个用于通过软件实现微处理器1的外围功能的子处理器5。子处理器5包括称为微程序存储单元13的电可写内部存储设备和用于存储软件的顺序控制存储单元62。可以通过将软件写入存储器单元13和62来定义或修改要由子处理器5实现的外围功能。因此，定义或修改外围功能所花费的时间与编程所花费的时间相同存储器单元13和62.子处理器5还包括用于执行多个任务的执行单元16和用于向微程序存储单元13提供地址给微程序存储单元13以提供微指令的地址控制电路14 到执行单元16.序列控制存储器单元62是地址控制电路14的一部分，其也包括多个地址寄存器MAR0到MAR11。序列控制存储单元62用于存储多个地址寄存器MAR0至MAR11将按顺序选择的顺序的信息。在序列控制存储器单元62上执行的每个读取周期中选择地址寄存器MAR0至MAR11中的一个。然后，将存储在选择的地址寄存器MAR0至MAR11中的微型地址提供给微程序存储器单元13.任务空值信息也可以存储在序列控制存储单元62中。在每个读取周期中选择地址寄存器MAR0至MAR11中的一个允许子处理器5以事件驱动为基础进行操作。

6. 发明授权

EP0431641B1 Microprocessor and method for setting up its peripheral functions 失效转让
标题翻译：微处理器和程序编制及其外设
公开(公告)号：EP0431641B1
公开(公告)日：1998-05-27
申请号：EP90123577.0
申请日：1990-12-07
申请人： HITACHI, LTD. , HITACHI ULSI ENGINEERING CORPORATION
发明人： Akao, Yasushi , Baba, Shiro , Miwa, Yoshiyuki , Sawase, Terumi , Sato, Yuji , Masumura, Shigeki
IPC分类号： G06F13/12 , G06F13/00 , G06F15/78
CPC分类号： G06F13/124 , G06F15/7814

7. 发明授权

EP0315139B1 Microprocessor 失效转让
标题翻译：微处理器
公开(公告)号：EP0315139B1
公开(公告)日：1998-03-04
申请号：EP88118235.6
申请日：1988-11-02
申请人： HITACHI, LTD. , HITACHI MICROCOMPUTER SYSTEM LTD. , Hitachi VLSI Engineering Corporation
发明人： Noguchi, Kouki , Tsuchiya, Fumio , Tsukamoto, Takashi , Masumura, Shigeki , Nakamura, Hideo , Baba, Shiro , Hagiwara, Yoshimune
IPC分类号： G06F9/30 , G06F9/22
CPC分类号： G06F9/30178 , G06F9/261 , G06F9/30145 , G06F9/30156

8. 发明公开

EP0315139A3 Microprocessor 失效转让
标题翻译：微处理器
公开(公告)号：EP0315139A3
公开(公告)日：1991-03-20
申请号：EP88118235.6
申请日：1988-11-02
申请人： HITACHI, LTD. , HITACHI MICROCOMPUTER SYSTEM LTD. , Hitachi VLSI Engineering Corporation
发明人： Noguchi, Kouki , Tsuchiya, Fumio , Tsukamoto, Takashi , Masumura, Shigeki , Nakamura, Hideo , Baba, Shiro , Hagiwara, Yoshimune
IPC分类号： G06F9/30 , G06F9/22
CPC分类号： G06F9/30178 , G06F9/261 , G06F9/30145 , G06F9/30156
摘要： In a microprocessor, a minimum instruction code length is set to a predetermined number of bits (e.g. one byte) length, an instruction set which can expand the instruction code length at a unit of the predetermined number of bits is used, an operand addressing mode and a type of operation for an operand are designated by separate predetermined number of code bits which are coded in a common coding scheme so that an instruction decoder is shared by those codes.
摘要翻译：在微处理器中，最小指令代码长度被设置为预定数量的位（例如一个字节）长度，使用可以以预定位数为单位扩展指令代码长度的指令集，操作数寻址模式并且通过以公共编码方案编码的单独预定数量的码位来指定操作数的操作类型，使得指令解码器被这些码共享。

9. 发明公开

EP0740254A2 Microprocessor and method for setting up its peripheral functions 失效
标题翻译： Mikroprozessor und Verfahren zur Aufstellung seiner Peripheriefunktionen
公开(公告)号：EP0740254A2
公开(公告)日：1996-10-30
申请号：EP96112686.9
申请日：1990-12-07
申请人： HITACHI, LTD. , HITACHI ULSI ENGINEERING CORPORATION
发明人： Akao, Yasushi , Baba, Shiro , Miwa, Yoshiyuki , Sawase, Terumi , Sato, Yuji , Masumura, Shigeki
IPC分类号： G06F13/12 , G06F9/38 , G06F15/78
CPC分类号： G06F13/124 , G06F15/7814
摘要： A single chip microprocessor 1 comprises a CPU 2 and a sub-processor 5 for implementing peripheral functions of the microprocessor 1 by software. The sub-processor 5 includes electrically writable internal storage devices called a microprogram memory unit 13 and a sequence control memory unit 62 for storing the software. Peripheral functions to be implemented by the sub-processor 5 can be defined or modified by writing software into the memory units 13 and 62. Accordingly, the time it takes to define or modify the peripheral functions is the same as the time it takes to program the memory units 13 and 62.
The sub-processor 5 also includes an execution unit 16 for executing a plurality of tasks and an address control circuit 14 for providing addresses to the microprogram memory unit 13 in addition to the microprogram memory unit 13 for providing microinstructions to the execution unit 16. The sequence control memory unit 62 is part of the address control circuit 14 which also includes a plurality of address registers MAR0 to MAR11. The sequence control memory unit 62 is used for storing information on what order the multiple address registers MAR0 to MAR11 are to be selected in sequentially. One of the address registers MAR0 to MAR11 is selected at every read cycle performed on the sequence control memory unit 62. A microaddress stored in the selected one of the address registers MAR0 to MAR11 is then supplied to the microprogram memory unit 13. Task null information can also be stored in the sequence control memory unit 62. The selection of one of the address registers MAR0 to MAR11 at every read cycle allows the sub-processor 5 to operate on an event driven basis.
摘要翻译：单片微处理器1包括用于通过软件实现微处理器1的外围功能的CPU 2和子处理器5。子处理器5包括称为微程序存储单元13的电可写内部存储装置和用于存储软件的顺序控制存储单元62。可以通过将软件写入存储器单元13和62来定义或修改由子处理器5实现的外设功能。因此，定义或修改外设功能所花费的时间与编程所需的时间相同子处理器5还包括用于执行多个任务的执行单元16和用于向微程序存储单元13提供地址的地址控制电路14，除了用于提供微指令的微程序存储单元13 序列控制存储器单元62是还包括多个地址寄存器MAR0至MAR11的地址控制电路14的一部分。顺序控制存储器单元62用于存储关于要顺序地选择多地址寄存器MAR0至MAR11的顺序的信息。在顺序控制存储器单元62上执行的每个读取周期选择地址寄存器MAR0至MAR11中的一个。然后将存储在所选择的一个地址寄存器MAR0至MAR11中的微地址提供给微程序存储单元13.任务空信息也可以存储在顺序控制存储器单元62中。在每个读取周期选择地址寄存器MAR0至MAR11之一允许子处理器5在事件驱动的基础上操作。

10. 发明公开

EP0561271A3 Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein 有权转让
标题翻译：数据线无干扰存储器块分割闪存和其中具有闪存的微型计算机
公开(公告)号：EP0561271A3
公开(公告)日：1995-07-26
申请号：EP93103907.7
申请日：1993-03-11
申请人： HITACHI, LTD. , HITACHI ULSI ENGINEERING CORPORATION
发明人： Matsubara, Kiyoshi, Arukasaru Musashino 210 , Yashiki, Naoki , Baba, Shiro , Ito, Takashi, Neokopo Kokubunji 211 , Mukai, Hirofumi , Sato, Masanao , Terasawa, Masaaki , Kuroda, Kenichi , Shiba, Kazuyoshi
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： H01L27/11526 , G06F9/445 , G06F15/7814 , G06F15/7821 , G11C7/1045 , G11C16/0416 , G11C16/102 , G11C16/105 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459 , H01L27/105 , H01L27/115 , H01L27/11531 , H01L27/11546 , Y02D10/43
摘要： An electrically rewritable flash memory device has a memory cell array including a plurality of memory cells (MC) arranged in rows and columns and is divided into a plurality of memory blocks (MB) having different memory capacities. Each memory block includes one or more rows of memory cells having their control gates connected to their associated word line conductors (WL) extending in a row direction. Sources of all of the memory cells in each memory are connected to one single common conductor (SL) associated therewith and extending in the row direction. Drains of memory cells are connected to respective data line conductors (DL) extending in a column direction. A common voltage control circuit (ERS) is provided for each of the memory blocks for applying a first potential (0V) to a common conductor for a memory block containing a memory cell selected with a selection voltage applied to its associated data line conductor for a writing operation and a second potential (Vddi--3.5V) higher than the first potential to a common conductor for a memory block containing a memory cell unselected with the selection voltage applied to its associated data line conductor and containing no selected memory cell for a writing operation. A microcomputer having a central processing unit (CPU) and the above-mentioned electrically rewritable flash memory (FMRY) formed in a single semiconductor chip (CHP) includes an input terminal (Pmode) for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of the central processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit (PRW) externally connectable to the microcomputer.
摘要翻译：电可重写闪存器件具有包括以行和列排列的多个存储器单元（MC）的存储器单元阵列，并且被划分为具有不同存储器容量的多个存储器块（MB）。每个存储器块包括一行或多行存储器单元，其存储器单元的控制栅极连接到沿行方向延伸的其相关字线导体（WL）。每个存储器中的所有存储器单元的源极连接到与其相关联并且在行方向上延伸的单个公共导体（SL）。存储单元的漏极连接到在列方向上延伸的各个数据线导体（DL）。为每个存储块提供公共电压控制电路（ERS），用于向存储块的公共导体施加第一电位（0V），该存储块包含通过施加到其关联的数据线导体的选择电压选择的存储单元，用于写入操作，并且将包含存储器单元的存储器块的公共导体的高于第一电位的第二电位（Vddi_3.5V）施加到存储器单元，所述存储器单元未被选择电压施加到其关联的数据线导体并且不包含用于写作操作。具有形成在单个半导体芯片（CHP）中的中央处理单元（CPU）和上述电可重写闪存（FMRY）的微型计算机包括用于接收操作模式信号的输入端子（Pmode），用于在在中央处理单元的控制下重写闪存的第一操作模式和在外部可连接到微型计算机的分离写入电路（PRW）的控制下重写闪存的第二操作模式。

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