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1. 发明公开

EP0561271A3 Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein 有权转让
标题翻译：数据线无干扰存储器块分割闪存和其中具有闪存的微型计算机
公开(公告)号：EP0561271A3
公开(公告)日：1995-07-26
申请号：EP93103907.7
申请日：1993-03-11
申请人： HITACHI, LTD. , HITACHI ULSI ENGINEERING CORPORATION
发明人： Matsubara, Kiyoshi, Arukasaru Musashino 210 , Yashiki, Naoki , Baba, Shiro , Ito, Takashi, Neokopo Kokubunji 211 , Mukai, Hirofumi , Sato, Masanao , Terasawa, Masaaki , Kuroda, Kenichi , Shiba, Kazuyoshi
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： H01L27/11526 , G06F9/445 , G06F15/7814 , G06F15/7821 , G11C7/1045 , G11C16/0416 , G11C16/102 , G11C16/105 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459 , H01L27/105 , H01L27/115 , H01L27/11531 , H01L27/11546 , Y02D10/43
摘要： An electrically rewritable flash memory device has a memory cell array including a plurality of memory cells (MC) arranged in rows and columns and is divided into a plurality of memory blocks (MB) having different memory capacities. Each memory block includes one or more rows of memory cells having their control gates connected to their associated word line conductors (WL) extending in a row direction. Sources of all of the memory cells in each memory are connected to one single common conductor (SL) associated therewith and extending in the row direction. Drains of memory cells are connected to respective data line conductors (DL) extending in a column direction. A common voltage control circuit (ERS) is provided for each of the memory blocks for applying a first potential (0V) to a common conductor for a memory block containing a memory cell selected with a selection voltage applied to its associated data line conductor for a writing operation and a second potential (Vddi--3.5V) higher than the first potential to a common conductor for a memory block containing a memory cell unselected with the selection voltage applied to its associated data line conductor and containing no selected memory cell for a writing operation. A microcomputer having a central processing unit (CPU) and the above-mentioned electrically rewritable flash memory (FMRY) formed in a single semiconductor chip (CHP) includes an input terminal (Pmode) for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of the central processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit (PRW) externally connectable to the microcomputer.
摘要翻译：电可重写闪存器件具有包括以行和列排列的多个存储器单元（MC）的存储器单元阵列，并且被划分为具有不同存储器容量的多个存储器块（MB）。每个存储器块包括一行或多行存储器单元，其存储器单元的控制栅极连接到沿行方向延伸的其相关字线导体（WL）。每个存储器中的所有存储器单元的源极连接到与其相关联并且在行方向上延伸的单个公共导体（SL）。存储单元的漏极连接到在列方向上延伸的各个数据线导体（DL）。为每个存储块提供公共电压控制电路（ERS），用于向存储块的公共导体施加第一电位（0V），该存储块包含通过施加到其关联的数据线导体的选择电压选择的存储单元，用于写入操作，并且将包含存储器单元的存储器块的公共导体的高于第一电位的第二电位（Vddi_3.5V）施加到存储器单元，所述存储器单元未被选择电压施加到其关联的数据线导体并且不包含用于写作操作。具有形成在单个半导体芯片（CHP）中的中央处理单元（CPU）和上述电可重写闪存（FMRY）的微型计算机包括用于接收操作模式信号的输入端子（Pmode），用于在在中央处理单元的控制下重写闪存的第一操作模式和在外部可连接到微型计算机的分离写入电路（PRW）的控制下重写闪存的第二操作模式。

2. 发明公开

EP0561271A2 Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein 有权转让
标题翻译： Datenleitungsstörungsfreier，在Speicherblöckegetterilter Flashspeicher und Mikrorechner mit Flashspeicher。
公开(公告)号：EP0561271A2
公开(公告)日：1993-09-22
申请号：EP93103907.7
申请日：1993-03-11
申请人： HITACHI, LTD. , HITACHI ULSI ENGINEERING CORPORATION
发明人： Matsubara, Kiyoshi, Arukasaru Musashino 210 , Yashiki, Naoki , Baba, Shiro , Ito, Takashi, Neokopo Kokubunji 211 , Mukai, Hirofumi , Sato, Masanao , Terasawa, Masaaki , Kuroda, Kenichi , Shiba, Kazuyoshi
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： H01L27/11526 , G06F9/445 , G06F15/7814 , G06F15/7821 , G11C7/1045 , G11C16/0416 , G11C16/102 , G11C16/105 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459 , H01L27/105 , H01L27/115 , H01L27/11531 , H01L27/11546 , Y02D10/43
摘要： An electrically rewritable flash memory device has a memory cell array including a plurality of memory cells (MC) arranged in rows and columns and is divided into a plurality of memory blocks (MB) having different memory capacities. Each memory block includes one or more rows of memory cells having their control gates connected to their associated word line conductors (WL) extending in a row direction. Sources of all of the memory cells in each memory are connected to one single common conductor (SL) associated therewith and extending in the row direction. Drains of memory cells are connected to respective data line conductors (DL) extending in a column direction. A common voltage control circuit (ERS) is provided for each of the memory blocks for applying a first potential (0V) to a common conductor for a memory block containing a memory cell selected with a selection voltage applied to its associated data line conductor for a writing operation and a second potential (Vddi--3.5V) higher than the first potential to a common conductor for a memory block containing a memory cell unselected with the selection voltage applied to its associated data line conductor and containing no selected memory cell for a writing operation. A microcomputer having a central processing unit (CPU) and the above-mentioned electrically rewritable flash memory (FMRY) formed in a single semiconductor chip (CHP) includes an input terminal (Pmode) for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of the central processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit (PRW) externally connectable to the microcomputer.
摘要翻译：电可重写闪速存储器件具有存储单元阵列，其包括以行和列排列的多个存储单元（MC），并被分成具有不同存储容量的多个存储块（MB）。每个存储器块包括一行或多行存储器单元，其存储单元的控制栅极连接到在行方向上延伸的相关联的字线导体（WL）。每个存储器中的所有存储单元的源连接到与其相关联并在行方向上延伸的单个公共导体（SL）。存储单元的漏极连接到沿列方向延伸的相应的数据线导体（DL）。为每个存储块提供公共电压控制电路（ERS），用于将第一电位（0V）施加到用于存储块的公共导体，该存储块包含用施加到其相关联的数据线导体的选择电压选择的存储单元，写入操作和高于第一电位的第二电位（Vddi-3.5V）到包含未施加到其相关联的数据线导体的选择电压的存储器单元的存储器块的公共导体的第二电位（Vddi-3.5V），并且不包含用于写作操作。具有中央处理单元（CPU）和形成在单个半导体芯片（CHP）中的上述电可重写闪存（FMRY）的微型计算机包括用于接收用于在微型计算机之间切换微型计算机的操作模式信号的输入端子（Pmode）在中央处理单元的控制下重写闪速存储器的第一操作模式和在外部可连接到微型计算机的单独写入电路（PRW）的控制下重写闪速存储器的第二操作模式。

3. 发明授权

EP0582991B1 Data processing apparatus having a flash memory built-in which is rewritable by use of external device 失效
标题翻译：结合使用外部快闪存储器结构的可再编程的数据处理设备
公开(公告)号：EP0582991B1
公开(公告)日：2002-11-06
申请号：EP93112755.9
申请日：1993-08-09
申请人： Hitachi, Ltd.
发明人： Matsubara, Kiyoshi , Sato, Masanao , Mukai, Hirofumi , Ishikawa, Eiichi
IPC分类号： G11C16/06
CPC分类号： G11C16/102 , G11C16/16

4. 发明授权

EP0902436B1 Microcomputer with flash memory programmable via external terminal 失效
标题翻译：微机与外部连接端子可编程闪存
公开(公告)号：EP0902436B1
公开(公告)日：2002-10-16
申请号：EP98118739.6
申请日：1993-03-11
申请人： Hitachi, Ltd. , HITACHI ULSI ENGINEERING CORP.
发明人： Matsubara, Kiyoshi , Yashiki, Naoki , Baba, Shiro , Ito, Takashi , Mukai, Hirofumi , Sato, Masanao , Terasawa, Masaaki , Kuroda, Kenichi , Shiba, Kazuyoshi
IPC分类号： G11C16/06 , G06F9/445
CPC分类号： H01L27/11526 , G06F9/445 , G06F15/7814 , G06F15/7821 , G11C7/1045 , G11C16/0416 , G11C16/102 , G11C16/105 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459 , H01L27/105 , H01L27/115 , H01L27/11531 , H01L27/11546 , Y02D10/43
摘要： A semiconductor integrated circuit device comprises a central processing unit (CPU), a first external terminal (EA0-EA16), and an electrically erasable and programmable nonvolatile flash memory (FMRY), wherein the semiconductor integrated circuit has a first operation mode in which the flash memory receives an address signal from the central processing unit executing a control program to erase and write data from and into the flash memory, and wherein the semiconductor integrated circuit has a second operation mode in which the flash memory receives an address signal on the external terminal to write data supplied from the outside of the semiconductor integrated circuit device into the flash memory.

5. 发明授权

EP1094470B1 Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein 失效
标题翻译：在快闪存储器和微处理器与快闪存储器共享存储器块中的数据线的无干扰
公开(公告)号：EP1094470B1
公开(公告)日：2003-08-13
申请号：EP00121759.5
申请日：1993-03-11
申请人： Hitachi, Ltd. , HITACHI ULSI ENGINEERING CORP.
发明人： Matsubara, Kiyoshi , Yashiki, Naoki , Baba, Shiro , Ito, Takashi , Mukai, Hirofumi , Sato, Masanao , Terasawa, Masaaki , Kuroda, Kenichi , Shiba, Kazuyoshi
IPC分类号： G11C16/06
CPC分类号： H01L27/11526 , G06F9/445 , G06F15/7814 , G06F15/7821 , G11C7/1045 , G11C16/0416 , G11C16/102 , G11C16/105 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459 , H01L27/105 , H01L27/115 , H01L27/11531 , H01L27/11546 , Y02D10/43
摘要： A semiconductor integrated circuit device comprises a central processing unit (CPU), a first external terminal (EA0-EA16), and an electrically erasable and programmable nonvolatile flash memory (FMRY), wherein the semiconductor integrated circuit has a first operation mode in which the flash memory receives an address signal from the central processing unit executing a control program to erase and write data from and into the flash memory, and wherein the semiconductor integrated circuit has a second operation mode in which the flash memory receives an address signal on the external terminal to write data supplied from the outside of the semiconductor integrated circuit device into the flash memory.

6. 发明授权

EP0561271B1 Microcomputer comprising a random access memory and a nonvolatile flash memory 有权转让
标题翻译：微机随机存取存储器和闪存
公开(公告)号：EP0561271B1
公开(公告)日：1999-07-07
申请号：EP93103907.7
申请日：1993-03-11
申请人： HITACHI, LTD. , Hitachi ULSI Systems Co.,Ltd.
发明人： Matsubara, Kiyoshi, Arukasaru Musashino 210 , Yashiki, Naoki , Baba, Shiro , Ito, Takashi, Neokopo Kokubunji 211 , Mukai, Hirofumi , Sato, Masanao , Terasawa, Masaaki , Kuroda, Kenichi , Shiba, Kazuyoshi
IPC分类号： G06F9/445 , G11C16/04 , G11C16/06
CPC分类号： H01L27/11526 , G06F9/445 , G06F15/7814 , G06F15/7821 , G11C7/1045 , G11C16/0416 , G11C16/102 , G11C16/105 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459 , H01L27/105 , H01L27/115 , H01L27/11531 , H01L27/11546 , Y02D10/43
摘要： A semiconductor integrated circuit device comprises a central processing unit (CPU), a first external terminal (EA0-EA16), and an electrically erasable and programmable nonvolatile flash memory (FMRY), wherein the semiconductor integrated circuit has a first operation mode in which the flash memory receives an address signal from the central processing unit executing a control program to erase and write data from and into the flash memory, and wherein the semiconductor integrated circuit has a second operation mode in which the flash memory receives an address signal on the external terminal to write data supplied from the outside of the semiconductor integrated circuit device into the flash memory.

7. 发明公开

EP0582991A3 Data processing apparatus having a flash memory built-in which is rewritable by use of external device 失效
标题翻译：具有通过使用外部设备可以获得闪存存储器的数据处理设备
公开(公告)号：EP0582991A3
公开(公告)日：1999-06-16
申请号：EP93112755.9
申请日：1993-08-09
申请人： HITACHI, LTD.
发明人： Matsubara, Kiyoshi , Sato, Masanao , Mukai, Hirofumi , Ishikawa, Eiichi
IPC分类号： G11C16/06
CPC分类号： G11C16/102 , G11C16/16
摘要： A data processing apparatus having a built-in flash memory and being capable of rewriting the built-in flash memory by use of versatilely used PROM writer has a CPU (10), an electrically rewritable nonvolatile flash memory both formed in a single semiconductor substrate (1), and is operable in a mode in which the built-in flash memory is rewritable in accordance with commands supplied from a PROM writer (30). The data processing apparatus has a command latch (21a, 21b, 21c) made externally writable when the above-mentioned operation mode is established, a command analyzer (22) and a sequence controller (23) for controlling a sequence of rewriting the flash memory in accordance with the analysis result. The command analyzer and sequence controller may be realized by the CPU.

8. 发明公开

EP0617377A2 Microcomputer with flash memory 失效
标题翻译： Mikrocomputer mit Flash-Speicher。
公开(公告)号：EP0617377A2
公开(公告)日：1994-09-28
申请号：EP94103180.9
申请日：1994-03-03
申请人： HITACHI, LTD.
发明人： Matsubara, Kiyoshi , Sato, Masanao , Ishikawa, Eiichi
IPC分类号： G06F15/78 , G11C16/06
CPC分类号： G11C29/52 , G06F15/7814 , G11C29/46
摘要： A one-chip type microcomputer or microprocessor includes a one-time programmable flash memory (FMRY) and a central processing unit (CPU) allowed to access the flash memory. The flash memory (FMRY) further includes a plurality of electrically erasable and programmable non-volatile memory elements arranged in a matrix pattern. The non-volatile memory element is made reprogrammable by erasure and writing only when a test mode (an operation mode exclusively utilizable by manufacturers of microcomputers) is designated by an external terminal (15). On the other hand, the flash memory is set one-time programmable by writing in a non-test mode (an op-eration mode inclusively utilizable by users of microcomputers) designated by the external terminal. The one-chip microcomputer or microprocessor is sealed in a plastic package with a pin-to-pin pitch of 0.5 mm or less.
摘要翻译：单片式微型计算机或微处理器包括允许访问闪存的一次性可编程闪存（FMRY）和中央处理单元（CPU）。闪速存储器（FMRY）还包括以矩阵模式布置的多个电可擦除和可编程的非易失性存储器元件。只有当外部终端（15）指定测试模式（由微型计算机的制造商专门使用的操作模式）时，通过擦除和写入使非易失性存储元件可重新编程。另一方面，通过由外部终端指定的非测试模式（由微型计算机可包含使用的操作模式）进行写入，将闪存设置为一次性可编程。单片微型计算机或微处理器以0.5mm或更小的针对针间距密封在塑料封装中。

9. 发明公开

EP0902436A3 Microcomputer with flash memory programmable via external terminal 失效
标题翻译： ääereäääher her her her her her her her her her her her her her
公开(公告)号：EP0902436A3
公开(公告)日：1999-05-19
申请号：EP98118739.6
申请日：1993-03-11
申请人： Hitachi, Ltd. , HITACHI ULSI ENGINEERING CORP.
发明人： Matsubara, Kiyoshi , Yashiki, Naoki , Baba, Shiro , Ito, Takashi , Mukai, Hirofumi , Sato, Masanao , Terasawa, Masaaki , Kuroda, Kenichi , Shiba, Kazuyoshi
IPC分类号： G11C16/06 , G06F9/445
CPC分类号： H01L27/11526 , G06F9/445 , G06F15/7814 , G06F15/7821 , G11C7/1045 , G11C16/0416 , G11C16/102 , G11C16/105 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459 , H01L27/105 , H01L27/115 , H01L27/11531 , H01L27/11546 , Y02D10/43
摘要： A semiconductor integrated circuit device comprises a central processing unit (CPU), a first external terminal (EA0-EA16), and an electrically erasable and programmable nonvolatile flash memory (FMRY), wherein the semiconductor integrated circuit has a first operation mode in which the flash memory receives an address signal from the central processing unit executing a control program to erase and write data from and into the flash memory, and wherein the semiconductor integrated circuit has a second operation mode in which the flash memory receives an address signal on the external terminal to write data supplied from the outside of the semiconductor integrated circuit device into the flash memory.
摘要翻译：半导体集成电路装置包括中央处理单元（CPU），第一外部端子（EA0-EA16）和电可擦除和可编程非易失性闪存（FMRY），其中半导体集成电路具有第一操作模式，闪速存储器从中央处理单元接收地址信号，执行控制程序以从闪存中擦除和写入数据，并且其中半导体集成电路具有第二操作模式，其中闪存接收外部的地址信号端子将从半导体集成电路器件的外部提供的数据写入闪速存储器。

10. 发明公开

EP0893799A3 Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein 失效
标题翻译：数据线无干扰存储器块分割闪存和其中具有闪存的微型计算机
公开(公告)号：EP0893799A3
公开(公告)日：1999-05-19
申请号：EP98118740.4
申请日：1993-03-11
申请人： Hitachi, Ltd. , HITACHI ULSI ENGINEERING CORP.
发明人： Matsubara, Kiyoshi , Yashiki, Naoki , Baba, Shiro , Ito, Takashi , Mukai, Hirofumi , Sato, Masanao , Terasawa, Masaaki , Kuroda, Kenichi , Shiba, Kazuyoshi
IPC分类号： G11C16/06
CPC分类号： H01L27/11526 , G06F9/445 , G06F15/7814 , G06F15/7821 , G11C7/1045 , G11C16/0416 , G11C16/102 , G11C16/105 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459 , H01L27/105 , H01L27/115 , H01L27/11531 , H01L27/11546 , Y02D10/43
摘要： A semiconductor integrated circuit device on a semiconductor chip comprises an address bus (ABUS), a data bus (DBUS, HDBUS, LDBUS), a central processing unit (CPU) being capable of processing data of a plurality of bits, and a flash memory (FMRY) having a plurality of memory cells (MC) arranged so as to be simultaneously erasable, said flash memory including a plurality of memory arrays (ARY0-ARY7) and being responsive to accessing from said central processing unit via said address bus and providing one data of a plurality of bits within a plurality of data stored therein to said central processing unit via said data bus in a manner in which each memory array outputs one bit (D0-C7) of said plurality of bits constituting said one data.
摘要翻译：半导体芯片上的半导体集成电路器件包括地址总线（ABUS），数据总线（DBUS，HDBUS，LDBUS），能够处理多位数据的中央处理单元（CPU），以及闪速存储器（FMRY）具有多个存储器单元（MC），所述存储器单元（MC）被布置为可同时擦除，所述闪存包括多个存储器阵列（ARY0-ARY7）并且响应于经由所述地址总线从所述中央处理单元进行访问并且提供通过所述数据总线以其中每个存储器阵列输出构成所述一个数据的所述多个比特中的一个比特（D0-C7）的方式将存储在其中的多个数据内的多个比特的一个数据传送到所述中央处理单元。

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