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1. 发明公开

EP0525375A2 Microcomputer and divider circuit 失效
标题翻译： Mikrocomputer和Teilerschaltung。
公开(公告)号：EP0525375A2
公开(公告)日：1993-02-03
申请号：EP92110517.7
申请日：1992-06-22
申请人： HITACHI, LTD. , HITACHI ULSI ENGINEERING CORPORATION , HITACHI MICROCOMPUTER SYSTEM LTD.
发明人： Kawasaki, Shumpei , Sakakibara, Eiji , Fukada, Kaoru , Yamazaki, Takanaga , Akao, Yasushi , Baba, Shiro , Kihara, Toshimasa , Kurakazu, Keiichi , Tsukamoto, Takashi , Masumura, Shigeki , Tawara, Yasuhiro , Kashiwagi, Yugo , Fujita, Shuya , Ishida, Katsuhiko , Sawa, Noriko , Asano, Yoichi , Chaki, Hideaki , Sugawara, Tadahiko , Kainaga, Masahiro , Noguchi, Kouki , Watabe, Mitsuru
IPC分类号： G06F9/38
CPC分类号： G06F7/535 , G06F9/30 , G06F9/3001 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/322 , G06F9/324 , G06F9/3557 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3867 , G06F2207/5352
摘要： RISC-type microprocessor has a fixed struction lenght of 2 n bits, whilst the data use size is 2 m bits,where m is greater than or equal to n.
摘要翻译： RISC型微处理器的固定结构长度为2 n位，数据使用大小为2 m，m大于或等于n。

2. 发明公开

EP0902361A2 Single-chip CPU and microcomputer 失效
标题翻译：单片机
公开(公告)号：EP0902361A2
公开(公告)日：1999-03-17
申请号：EP98120015.7
申请日：1992-06-22
申请人： Hitachi, Ltd. , HITACHI ULSI ENGINEERING CORPORATION , HITACHI MICROCOMPUTER SYSTEM LTD.
发明人： Kawasaki, Shumpei , Sakakibara, Eiji , Fukada, Kaoru , Yamazaki, Takanaga , Akao, Yasushi , Baba, Shiro , Kihara, Toshimasa , Kurakazu, Keiichi , Tsukamoto, Takashi , Masumura, Shigeki , Tawara, Yasuhiro , Kashiwagi, Yugo , Fujita, Shuya , Ishida, Katsuhiko , Sawa, Noriko , Asano, Yoichi , Chaki, Hideaki , Sugawara, Tadahiko , Kainaga, Masahiro , Noguchi, Kouki B-11, Hitachitennouueshataku , Watabe, Mitsuru
IPC分类号： G06F9/38 , G06F15/78
CPC分类号： G06F7/535 , G06F9/30 , G06F9/3001 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/322 , G06F9/324 , G06F9/3557 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3867 , G06F2207/5352
摘要： A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting an instruction format of a fixed length of 2 n bits which is smaller than the length of the maximum data word fed to instruction execution means. The control of the coded division is executed by noting the code bits.

3. 发明公开

EP0525375A3 Microcomputer and divider circuit 失效
标题翻译：微型计算机和分路器电路
公开(公告)号：EP0525375A3
公开(公告)日：1993-04-21
申请号：EP92110517.7
申请日：1992-06-22
申请人： HITACHI, LTD. , HITACHI ULSI ENGINEERING CORPORATION , HITACHI MICROCOMPUTER SYSTEM LTD.
发明人： Kawasaki, Shumpei , Sakakibara, Eiji , Fukada, Kaoru , Yamazaki, Takanaga , Akao, Yasushi , Baba, Shiro , Kihara, Toshimasa , Kurakazu, Keiichi , Tsukamoto, Takashi , Masumura, Shigeki , Tawara, Yasuhiro , Kashiwagi, Yugo , Fujita, Shuya , Ishida, Katsuhiko , Sawa, Noriko , Asano, Yoichi , Chaki, Hideaki , Sugawara, Tadahiko , Kainaga, Masahiro , Noguchi, Kouki , Watabe, Mitsuru
IPC分类号： G06F9/38
CPC分类号： G06F7/535 , G06F9/30 , G06F9/3001 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/322 , G06F9/324 , G06F9/3557 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3867 , G06F2207/5352
摘要： RISC-type microprocessor has a fixed struction lenght of 2 n bits, whilst the data use size is 2 m bits,where m is greater than or equal to n.

4. 发明公开

EP0902358A2 Division circuit and method 失效
标题翻译： Dividierschaltung und -verfahren
公开(公告)号：EP0902358A2
公开(公告)日：1999-03-17
申请号：EP98120014.0
申请日：1992-06-22
申请人： Hitachi, Ltd. , HITACHI ULSI ENGINEERING CORPORATION , HITACHI MICROCOMPUTER SYSTEM LTD.
发明人： Kawasaki, Shumpei , Sakakibara, Eiji , Fukada, Kaoru , Yamazaki, Takanaga , Akao, Yasushi , Baba, Shiro , Kihara, Toshimasa , Kurakazu, Keiichi , Tsukamoto, Takashi , Masumura, Shigeki , Tawara, Yasuhiro , Kashiwagi, Yugo , Fujita, Shuya , Ishida, Katsuhiko , Sawa, Noriko , Asano, Yoichi , Chaki, Hideaki , Sugawara, Tadahiko , Kainaga, Masahiro , Noguchi, Kouki B-11, Hitachitennouueshataku , Watabe, Mitsuru
IPC分类号： G06F7/52
CPC分类号： G06F7/535 , G06F9/30 , G06F9/3001 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/322 , G06F9/324 , G06F9/3557 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3867 , G06F2207/5352
摘要： A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting an instruction format of a fixed length of 2 n bits which is smaller than the length of the maximum data word fed to instruction execution means. The control of the coded division is executed by noting the code bits.
摘要翻译：采用通用寄存器方法的微型计算机MCU能够使用效率低的系统成本具有小的程序容量或高程序存储器，同时具有简化指令解码的优点，如具有固定长度指令格式的RISC机器通过采用小于馈送到指令执行装置的最大数据字的长度的2 个固定长度的指令格式。编码分割的控制是通过注意码位执行的。

5. 发明公开

EP0740254A3 Microprocessor and method for setting up its peripheral functions 失效
标题翻译：微处理器和设置其外设功能的方法
公开(公告)号：EP0740254A3
公开(公告)日：1996-11-20
申请号：EP96112686.9
申请日：1990-12-07
申请人： HITACHI, LTD. , HITACHI ULSI ENGINEERING CORPORATION
发明人： Akao, Yasushi , Baba, Shiro , Miwa, Yoshiyuki , Sawase, Terumi , Sato, Yuji , Masumura, Shigeki
IPC分类号： G06F13/12 , G06F9/38 , G06F15/78
CPC分类号： G06F13/124 , G06F15/7814
摘要： A single chip microprocessor 1 comprises a CPU 2 and a sub-processor 5 for implementing peripheral functions of the microprocessor 1 by software. The sub-processor 5 includes electrically writable internal storage devices called a microprogram memory unit 13 and a sequence control memory unit 62 for storing the software. Peripheral functions to be implemented by the sub-processor 5 can be defined or modified by writing software into the memory units 13 and 62. Accordingly, the time it takes to define or modify the peripheral functions is the same as the time it takes to program the memory units 13 and 62. The sub-processor 5 also includes an execution unit 16 for executing a plurality of tasks and an address control circuit 14 for providing addresses to the microprogram memory unit 13 in addition to the microprogram memory unit 13 for providing microinstructions to the execution unit 16. The sequence control memory unit 62 is part of the address control circuit 14 which also includes a plurality of address registers MAR0 to MAR11. The sequence control memory unit 62 is used for storing information on what order the multiple address registers MAR0 to MAR11 are to be selected in sequentially. One of the address registers MAR0 to MAR11 is selected at every read cycle performed on the sequence control memory unit 62. A microaddress stored in the selected one of the address registers MAR0 to MAR11 is then supplied to the microprogram memory unit 13. Task null information can also be stored in the sequence control memory unit 62. The selection of one of the address registers MAR0 to MAR11 at every read cycle allows the sub-processor 5 to operate on an event driven basis.
摘要翻译：单片微处理器1包括一个CPU2和一个用于通过软件实现微处理器1的外围功能的子处理器5。子处理器5包括称为微程序存储单元13的电可写内部存储设备和用于存储软件的顺序控制存储单元62。可以通过将软件写入存储器单元13和62来定义或修改要由子处理器5实现的外围功能。因此，定义或修改外围功能所花费的时间与编程所花费的时间相同存储器单元13和62.子处理器5还包括用于执行多个任务的执行单元16和用于向微程序存储单元13提供地址给微程序存储单元13以提供微指令的地址控制电路14 到执行单元16.序列控制存储器单元62是地址控制电路14的一部分，其也包括多个地址寄存器MAR0到MAR11。序列控制存储单元62用于存储多个地址寄存器MAR0至MAR11将按顺序选择的顺序的信息。在序列控制存储器单元62上执行的每个读取周期中选择地址寄存器MAR0至MAR11中的一个。然后，将存储在选择的地址寄存器MAR0至MAR11中的微型地址提供给微程序存储器单元13.任务空值信息也可以存储在序列控制存储单元62中。在每个读取周期中选择地址寄存器MAR0至MAR11中的一个允许子处理器5以事件驱动为基础进行操作。

6. 发明公开

EP0718779A1 Single-chip microcomputer 失效
标题翻译： Einchip-Mikrocomputer
公开(公告)号：EP0718779A1
公开(公告)日：1996-06-26
申请号：EP96102998.0
申请日：1994-08-10
申请人： HITACHI, LTD. , HITACHI MICROCOMPUTER SYSTEM LTD.
发明人： Kawasaki, Shumpei , Akao, Yasushi , Noguchi, Kouki , Hasegawa, Atsushi , Ohsuga, Hiroshi , Kurakazu, Keiichi , Matsubara, Kiyoshi , Hayakawa, Akio , Ito, Yoshitaka
IPC分类号： G06F13/42 , G06F13/40 , G06F15/78
CPC分类号： G06F9/3001 , G06F12/0893 , G06F13/36 , G06F13/405 , G06F15/7817 , H04W28/08 , H04W52/0216 , H04W88/02 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D70/142 , Y02D70/26
摘要： A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.
摘要翻译：一种单片微计算机，包括：具有中央处理单元和与其连接的高速缓冲存储器的第一总线; 具有动态存储器访问控制电路和与其连接的外部总线接口的第二总线; 用于选择性地连接第一总线和第二总线的断开控制器; 第三总线具有与其连接的外围模块，并且具有比第一和第二总线的总线周期更低的总线周期; 以及用于进行数据传送和第二总线与第三总线之间的同步的总线状态控制器。单片机具有三条分开的内部总线，以减少信号传输路径上的负载能力，从而可以高速实现信号传输。此外，隔离所需要的没有运行速度的外围模块，从而可以降低功耗。

7. 发明公开

EP0597307A1 Microcomputer and microcomputer system 失效
标题翻译： Mikrocomputer和Mikrocomputersystem。
公开(公告)号：EP0597307A1
公开(公告)日：1994-05-18
申请号：EP93117256.3
申请日：1993-10-25
申请人： HITACHI, LTD. , HITACHI MICROCOMPUTER SYSTEM LTD. , HITACHI VLSI ENGINEERING CORPORATION
发明人： Kawasaki, Shumpei , Fukada, Kaoru , Watabe, Mitsuru , Noguchi, Kouki , Matsubara, Kiyoshi , Mochizuki, Isamu , Suzukawa, Kazufumi , Masumura, Shigeki , Akao, Yasushi , Sakakibara, Eiji
IPC分类号： G06F13/42 , G06F15/78
CPC分类号： G06F15/7832 , G06F13/4239 , G06F15/786
摘要： A microcomputer that is easy to use and connected direct to such memories as dynamic and static RAM's and to other peripheral circuits. The microcomputer has strobe signal output terminals CASH * , CASL * and RAS * for direct connection to a dynamic RAM, and chip select signal output terminals CSO * through CS6 * for outputting a chip select signal in parallel with the output from the strobe signal output terminals. The microcomputer further includes address output terminals for outputting a non-multiplexed or multiplexed address signal as needed, and data I/O terminals for selectively outputting the address signal to comply with a multiple-bus interface scheme.
摘要翻译：一种易于使用和直接连接到诸如动态和静态RAM以及其他外围电路之类的存储器的微型计算机。微型计算机具有选通信号输出端子CASH *，CASL *和RAS *，用于直接连接到动态RAM，以及芯片选择信号输出端子CS0 *至CS6 *，用于与选通信号输出的输出并行输出芯片选择信号终端。微型计算机还包括用于根据需要输出未复用或复用的地址信号的地址输出端子和用于选择性地输出地址信号以符合多总线接口方案的数据I / O端子。

8. 发明授权

EP0431641B1 Microprocessor and method for setting up its peripheral functions 失效转让
标题翻译：微处理器和程序编制及其外设
公开(公告)号：EP0431641B1
公开(公告)日：1998-05-27
申请号：EP90123577.0
申请日：1990-12-07
申请人： HITACHI, LTD. , HITACHI ULSI ENGINEERING CORPORATION
发明人： Akao, Yasushi , Baba, Shiro , Miwa, Yoshiyuki , Sawase, Terumi , Sato, Yuji , Masumura, Shigeki
IPC分类号： G06F13/12 , G06F13/00 , G06F15/78
CPC分类号： G06F13/124 , G06F15/7814

9. 发明公开

EP0646873A2 Single-chip microcomputer 失效
标题翻译：单片机。
公开(公告)号：EP0646873A2
公开(公告)日：1995-04-05
申请号：EP94112520.5
申请日：1994-08-10
申请人： HITACHI, LTD. , HITACHI MICROCOMPUTER SYSTEM LTD.
发明人： Kawasaki, Shumpei , Akao, Yasushi , Noguchi, Kouki , Hasegawa, Atsushi , Ohsuga, Hiroshi , Kurakazu, Keiichi , Matsubara, Kiyoshi , Hayakawa, Akio , Ito, Yoshitaka
IPC分类号： G06F13/40 , G06F15/78 , G06F12/08 , G06F13/42
CPC分类号： G06F9/3001 , G06F12/0893 , G06F13/36 , G06F13/405 , G06F15/7817 , H04W28/08 , H04W52/0216 , H04W88/02 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D70/142 , Y02D70/26
摘要： A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

10. 发明公开

EP0740254A2 Microprocessor and method for setting up its peripheral functions 失效
标题翻译： Mikroprozessor und Verfahren zur Aufstellung seiner Peripheriefunktionen
公开(公告)号：EP0740254A2
公开(公告)日：1996-10-30
申请号：EP96112686.9
申请日：1990-12-07
申请人： HITACHI, LTD. , HITACHI ULSI ENGINEERING CORPORATION
发明人： Akao, Yasushi , Baba, Shiro , Miwa, Yoshiyuki , Sawase, Terumi , Sato, Yuji , Masumura, Shigeki
IPC分类号： G06F13/12 , G06F9/38 , G06F15/78
CPC分类号： G06F13/124 , G06F15/7814
摘要： A single chip microprocessor 1 comprises a CPU 2 and a sub-processor 5 for implementing peripheral functions of the microprocessor 1 by software. The sub-processor 5 includes electrically writable internal storage devices called a microprogram memory unit 13 and a sequence control memory unit 62 for storing the software. Peripheral functions to be implemented by the sub-processor 5 can be defined or modified by writing software into the memory units 13 and 62. Accordingly, the time it takes to define or modify the peripheral functions is the same as the time it takes to program the memory units 13 and 62.
The sub-processor 5 also includes an execution unit 16 for executing a plurality of tasks and an address control circuit 14 for providing addresses to the microprogram memory unit 13 in addition to the microprogram memory unit 13 for providing microinstructions to the execution unit 16. The sequence control memory unit 62 is part of the address control circuit 14 which also includes a plurality of address registers MAR0 to MAR11. The sequence control memory unit 62 is used for storing information on what order the multiple address registers MAR0 to MAR11 are to be selected in sequentially. One of the address registers MAR0 to MAR11 is selected at every read cycle performed on the sequence control memory unit 62. A microaddress stored in the selected one of the address registers MAR0 to MAR11 is then supplied to the microprogram memory unit 13. Task null information can also be stored in the sequence control memory unit 62. The selection of one of the address registers MAR0 to MAR11 at every read cycle allows the sub-processor 5 to operate on an event driven basis.
摘要翻译：单片微处理器1包括用于通过软件实现微处理器1的外围功能的CPU 2和子处理器5。子处理器5包括称为微程序存储单元13的电可写内部存储装置和用于存储软件的顺序控制存储单元62。可以通过将软件写入存储器单元13和62来定义或修改由子处理器5实现的外设功能。因此，定义或修改外设功能所花费的时间与编程所需的时间相同子处理器5还包括用于执行多个任务的执行单元16和用于向微程序存储单元13提供地址的地址控制电路14，除了用于提供微指令的微程序存储单元13 序列控制存储器单元62是还包括多个地址寄存器MAR0至MAR11的地址控制电路14的一部分。顺序控制存储器单元62用于存储关于要顺序地选择多地址寄存器MAR0至MAR11的顺序的信息。在顺序控制存储器单元62上执行的每个读取周期选择地址寄存器MAR0至MAR11中的一个。然后将存储在所选择的一个地址寄存器MAR0至MAR11中的微地址提供给微程序存储单元13.任务空信息也可以存储在顺序控制存储器单元62中。在每个读取周期选择地址寄存器MAR0至MAR11之一允许子处理器5在事件驱动的基础上操作。

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