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81. 发明公开

EP0895293A2 Semiconductor device comprising an aggregate of semiconductor micro-needles 失效
标题翻译：一种半导体装置，包括半导体材料的微针的集合体
公开(公告)号：EP0895293A2
公开(公告)日：1999-02-03
申请号：EP98119143.0
申请日：1994-11-02
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Eriguchi, Kofi , Kubota, Masafumi , Niwa, Masaaki , Nomura, Noboru
IPC分类号： H01L33/00 , H01L21/30 , H01L27/15
CPC分类号： H01L31/1804 , B82Y10/00 , G02B6/1245 , G02B2006/12102 , G02B2006/12173 , G02B2006/12176 , G11C23/00 , H01H1/0036 , H01L21/3086 , H01L31/0352 , H01L33/10 , H01L33/18 , Y02E10/547 , Y02P70/521 , Y10S438/947 , Y10S438/962 , Y10S438/964
摘要： On a silicon substrate is formed a silicon dioxide film and then hemispherical grains made of silicon, each having an extremely small diameter, are deposited thereon by LPCVD. After annealing the hemispherical grains, the silicon dioxide film is etched using the hemispherical grains as a first dotted mask, thereby forming a second dotted mask composed of the silicon dioxide film. The resulting second dotted mask is used to etch the silicon substrate to a specified depth from the surface thereof, thereby forming an aggregate of semiconductor micro-needles. Since the diameter of each of the semiconductor micro-needles is sufficiently small to cause the quantum size effects as well as has only small size variations, remarkable quantum size effects can be obtained. Therefore, it becomes possible to constitute a semiconductor apparatus with a high information-processing function by using the aggregate of semiconductor micro-needles (quantized region).

82. 发明公开

EP0892445A2 Semiconductor device comprising an aggregate of semiconductor micro-needles 失效
公开(公告)号：EP0892445A2
公开(公告)日：1999-01-20
申请号：EP98119144.8
申请日：1994-11-02
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Eriguchi, Kofi , Kubota, Masafumi , Niwa, Masaaki , Nomura, Noboru
IPC分类号： H01L33/00 , H01L21/30 , H01L27/15
CPC分类号： H01L31/1804 , B82Y10/00 , G02B6/1245 , G02B2006/12102 , G02B2006/12173 , G02B2006/12176 , G11C23/00 , H01H1/0036 , H01L21/3086 , H01L31/0352 , H01L33/10 , H01L33/18 , Y02E10/547 , Y02P70/521 , Y10S438/947 , Y10S438/962 , Y10S438/964
摘要： On a silicon substrate is formed a silicon dioxide film and then hemispherical grains made of silicon, each having an extremely small diameter, are deposited thereon by LPCVD. After annealing the hemispherical grains, the silicon dioxide film is etched using the hemispherical grains as a first dotted mask, thereby forming a second dotted mask composed of the silicon dioxide film. The resulting second dotted mask is used to etch the silicon substrate to a specified depth from the surface thereof, thereby forming an aggregate of semiconductor micro-needles. Since the diameter of each of the semiconductor micro-needles is sufficiently small to cause the quantum size effects as well as has only small size variations, remarkable quantum size effects can be obtained. Therefore, it becomes possible to constitute a semiconductor apparatus with a high information-processing function by using the aggregate of semiconductor micro-needles (quantized region).

83. 发明公开

EP0851464A1 Traitement anti-reflet de surfaces réflectives 失效
标题翻译：反驳者贝恩德伦von reflektierendenOberflächen
公开(公告)号：EP0851464A1
公开(公告)日：1998-07-01
申请号：EP97403107.2
申请日：1997-12-22
申请人： FRANCE TELECOM
发明人： Francou, Jean-Marc , Halimaoui, Aomar , Schiltz, André
IPC分类号： H01L21/027
CPC分类号： H01L21/0276 , Y10S430/151 , Y10S438/96 , Y10S438/964
摘要： La présente invention a trait à un procédé de photolithographie amélioré, particulièrement adapté aux techniques de lithographie optique à haute résolution utilisant les raies g, h et i du spectre du mercure et les UV à courte longueur d'onde, comprenant, préalablement au dépôt de la résine photosensible sur la couche de matériau à lithographier, la formation d'une couche poreuse anti-réflective au sein même de ladite couche à lithographier et à la surface de celle-ci.
摘要翻译：在IC制造中，感光性树脂层（5）的下面的层（3）的光刻工序涉及在层（3）的表面内部和表面形成具有相同材料并赋予厚度的多孔层（4），成为在沉积树脂之前是光刻结构的。优选地，待光刻结构的层（3）由导电或半导体材料，特别是可通过在含有硅氧烷型表面活性剂的浴中进行化学处理形成多孔硅的硅半导体材料构成。

84. 发明公开

EP0687008A3 Method and apparatus for improving interfacial adhesion between a polymer and a metal 失效
标题翻译：用于改善聚合物和金属之间的Grenzflächenadhesion方法和装置
公开(公告)号：EP0687008A3
公开(公告)日：1997-06-11
申请号：EP95108620.6
申请日：1995-06-06
申请人： MOTOROLA, INC.
发明人： Ganesan , Berg, Howard Martin
IPC分类号： H01L23/495 , H01L21/48
CPC分类号： H01L21/4821 , H01L23/49503 , H01L24/48 , H01L24/73 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/83385 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/12044 , H01L2924/15747 , H01L2924/181 , Y10S438/964 , Y10T29/49121 , Y10T29/49171 , H01L2924/00012 , H01L2924/00 , H01L2224/45099
摘要： A leadframe (11) and a method for improving adhesion of a polymer (17, 19) to the leadframe (11). The leadframe (11) has a flag (14) having a top surface (15) and a bottom surface (18), and leads (12). Microscopic locking features (31) are formed in the top surface (15) and the bottom surface (18) of flag (14) by bombarding the flag (14) with a grit material. Thus, the top and bottom surfaces (15, 18) are roughened. A semiconductor die (13) is attached to the flag (14) by a die attach material (17) and the flag (13), the semiconductor material (13), and portions of the leads (12) are encapsulated by a molding compound. The pits improve the adhesion of the die attach material (17) and the molding compound (19) to the leadframe (11).
摘要翻译：的引线框架（11）和用于改善聚合物（17,19）与引线框（11）的粘合性的方法。引线框架（11）包括具有顶表面（15）和底表面（18）和引线（12）的标志（14）。细微锁紧特征（31）在所述顶表面（15）和标志（14）的底表面（18）通过用砂砾材料轰击标志（14）形成。因此，顶面和底面（15，18）是粗糙的。引线的那个（13）由所述连接材料（17）和标志（13），半导体材料（13）附连到标志（14）一种半导体，和部分（12）由模制化合物包封，凹坑提高管芯附接材料（17）和所述模制化合物（19）与引线框（11）的粘合力。

85. 发明公开

EP0687008A2 Method and apparatus for improving interfacial adhesion between a polymer and a metal 失效
标题翻译：用于改善聚合物和金属之间的Grenzflächenadhesion方法和装置
公开(公告)号：EP0687008A2
公开(公告)日：1995-12-13
申请号：EP95108620.6
申请日：1995-06-06
申请人： MOTOROLA, INC.
发明人： Ganesan , Berg, Howard Martin
IPC分类号： H01L23/495 , H01L21/48
CPC分类号： H01L21/4821 , H01L23/49503 , H01L24/48 , H01L24/73 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/83385 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/12044 , H01L2924/15747 , H01L2924/181 , Y10S438/964 , Y10T29/49121 , Y10T29/49171 , H01L2924/00012 , H01L2924/00 , H01L2224/45099
摘要： A leadframe (11) and a method for improving adhesion of a polymer (17, 19) to the leadframe (11). The leadframe (11) has a flag (14) having a top surface (15) and a bottom surface (18), and leads (12). Microscopic locking features (31) are formed in the top surface (15) and the bottom surface (18) of flag (14) by bombarding the flag (14) with a grit material. Thus, the top and bottom surfaces (15, 18) are roughened. A semiconductor die (13) is attached to the flag (14) by a die attach material (17) and the flag (13), the semiconductor material (13), and portions of the leads (12) are encapsulated by a molding compound. The pits improve the adhesion of the die attach material (17) and the molding compound (19) to the leadframe (11).

86. 发明公开

EP0682360A2 Method of forming a capacitor from a polysilicon layer 失效
标题翻译： Verfahren zur Herstellung eines Kondensators aus einer Polysiliziumschicht。
公开(公告)号：EP0682360A2
公开(公告)日：1995-11-15
申请号：EP95302951.9
申请日：1995-05-01
申请人： ADVANCED MICRO DEVICES INC.
发明人： Anjum, Mohammed , Koop, Klaus H. , Kyaw, Haung H.
IPC分类号： H01L21/3205 , H01L21/329
CPC分类号： H01L27/10852 , H01L27/10808 , H01L28/82 , H01L28/84 , Y10S148/014 , Y10S438/964
摘要： An enhanced capacitor configuration is provided in which the conductive and insulative layers are formed by implantation rather than deposition. The conductive regions are implanted at dissimilar depths and the insulative region is implanted between the conductive regions to form the conductive plates and intermediate dielectric material. By implanting rather than depositing, the dielectric material remains free of pinholes and can be configured thinner than conventional dielectrics, with a higher dielectric constant (k) due to the absence of an oxide. Moreover, cross-diffusions which occur during the anneal step allow texturization of the dielectric/conductive juncture. Texturization corresponds to an increase in surface area of the capacitor and, similar to increase in dielectric constant and decrease in dielectric thickness, increases the capacitive value of the ensuing capacitor.
摘要翻译：方法包括：在上表面形貌上沉积多晶硅; 植入P离子使得聚异构化成第一深度; 将N离子注入到非晶化区域中较浅的峰深度; 将P离子注入到较浅的深度; 并退火以形成夹持氮化物电介质的注入P区的电容器。氮化物-P层界面由于扩散而被纹理化，但消除了穿过氮化物的导电路径。第一P植入物在40keV至峰浓度为1×10 15 / cm 2。深度520埃; N型植入物在2.5keV至峰浓度为5×10 15 / cm 2。深度为80埃; 并且第二P植入物在0.5keV至峰浓度为1×10 13 / cm 2。深度22埃。聚合物在600℃以上退火，得到的氮化物层的介电常数高于3.0。然后加入电容器金属化。

87. 发明公开

EP0630055A3 Method for fabricating polycrystalline silicon having micro roughness on the surface 失效
标题翻译：用于制造在表面上具有微粗糙度的多晶硅的方法
公开(公告)号：EP0630055A3
公开(公告)日：1995-01-04
申请号：EP94111698.0
申请日：1991-03-20
申请人： NEC CORPORATION
发明人： Watanabe, Hirohito , Tatsumi, Toru
IPC分类号： H01L29/94 , H01L29/04 , H01L21/20
CPC分类号： H01L27/10817 , H01L28/82 , H01L28/84 , H01L28/90 , Y10S438/964
摘要： A method for fabricating a polycrystalline silicon having a roughed surface, which is useful for a capacitor electrode is disclosed. The method is featured by depositing a polycrystalline silicon layer in such a manner that grains of silicon are caused at the surface of the polycrystalline silicon layer. The polycrystalline silicon layer thus obtained has a large effective surface area and is suitable for a capacitor electrode because of its increased effective surface area.
摘要翻译：公开了一种用于制造具有粗糙表面的多晶硅的方法，其可用于电容器电极。该方法的特征在于以在多晶硅层的表面处引起硅晶粒的方式沉积多晶硅层。由此获得的多晶硅层具有大的有效表面积，并且由于其有效表面积增大而适用于电容器电极。

88. 发明公开

EP0553791A1 Capacitor electrode for dram and process of fabrication thereof 失效
标题翻译： KondensatorelektrodefürDRAM und Verfahren zu ihrer Herstellung。
公开(公告)号：EP0553791A1
公开(公告)日：1993-08-04
申请号：EP93101212.4
申请日：1993-01-27
申请人： NEC CORPORATION
发明人： Hirota, Toshiyuki, c/o NEC Corporation , Honma, Ichirou, c/o NEC Corporation , Watanabe, Hirohito, c/o NEC Corporation , Zenke, Masanobu, c/o NEC Corporation
IPC分类号： H01L21/82 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10808 , Y10S148/138 , Y10S438/964
摘要： A capacitor incorporated in a semiconductor integrated circuit device is expected to have a large amount of capacitance without increase of the occupation area, and has a lower electrode (21a) increased in surface area by using a roughening technique selected from the group consisting of an anodizing technique, an anodic oxidation, a wet etching and a dry etching so that a surface of the lower electrode becomes porous (21b), thereby increasing the capacitance.
摘要翻译：期望在半导体集成电路器件中并入的电容器具有大量的电容而不增加占用面积，并且通过使用选自下列的粗糙化技术，具有增加表面积的下电极（21a）：阳极氧化技术，阳极氧化，湿蚀刻和干蚀刻，使得下电极的表面变得多孔（21b），从而增加电容。

89. 发明公开

EP0448374A1 Method for fabricating a semiconductor device having a capacitor with polycrystalline silicon having micro roughness on the surface 失效
标题翻译： Verfahren zum Herstellen von polykristallinen Silizium mit mikrorauherOberfläche。
公开(公告)号：EP0448374A1
公开(公告)日：1991-09-25
申请号：EP91302414.7
申请日：1991-03-20
申请人： NEC CORPORATION
发明人： Watanabe, Hirohito, c/o NEC Corporation , Tatsumi, Toru, c/o NEC Corporation
IPC分类号： H01L29/94 , H01L29/04 , H01L21/20
CPC分类号： H01L27/10817 , H01L28/82 , H01L28/84 , H01L28/90 , Y10S438/964
摘要： A method for fabricating a polycrystalline silicon having a roughed surface, which is useful for a capacitor electrode is disclosed. The method is featured by depositing a polycrystalline silicon layer in such a manner that grains of silicon are caused at the surface of the polycrystalline silicon layer. The polycrystalline silicon layer thus obtained has a large effective surface area and is suitable for a capacitor electrode because of its increased effective surface area.
摘要翻译：公开了一种制造具有粗糙表面的多晶硅的方法，其可用于电容器电极。该方法的特征在于以如下方式沉积多晶硅层，即在多晶硅层的表面引起硅晶粒。由此获得的多晶硅层具有大的有效表面积，由于其有效表面积增加，因此适用于电容器电极。

90. 发明公开

EP0334330A3 Opto-electric transducing element and method for producing the same 失效
标题翻译：光电转换元件及其制造方法
公开(公告)号：EP0334330A3
公开(公告)日：1990-09-26
申请号：EP89105160.9
申请日：1989-03-22
申请人： HITACHI, LTD.
发明人： Uematsu, Tsuyoshi , Saitoh, Tadashi
IPC分类号： H01L31/02 , H01L31/18 , H01L31/06
CPC分类号： H01L23/544 , H01L21/3083 , H01L31/02363 , H01L31/035281 , H01L31/0547 , H01L31/056 , H01L31/1804 , H01L2924/0002 , Y02E10/52 , Y02E10/547 , Y02P70/521 , Y10S438/964 , Y10S438/975 , H01L2924/00
摘要： Using a corrugated semiconductor substrate, the opto-electric transducing element is produced. The element has a reduced effective thickness and an improved opto-electric conversion efficiency, while maintaining the mechanical strength.

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