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1. 发明授权

EP0707345B1 Method for fabricating an integrated circuit 失效
标题翻译：一种用于制造集成电路装置的过程
公开(公告)号：EP0707345B1
公开(公告)日：2000-01-05
申请号：EP95307087.7
申请日：1995-10-06
申请人： ADVANCED MICRO DEVICES INC.
发明人： Anjum, Mohammed , Stuber, Alan, L. , Burki, Ibrahim, K.
IPC分类号： H01L29/08 , H01L21/8238
CPC分类号： H01L29/0847 , H01L21/823807
摘要： An MOS device is provided using indium as a threshold adjust implant in the channel regions of an NMOS device and/or in the conductive gate overlying the channel region in a PMOS device. Indium ions are relatively immobile and achieve location stability in the areas in which they are implanted. They do not readily segregate and diffuse in the lateral directions as well as in directions perpendicular to the silicon substrate. Placement immobility is necessary in order to minimize problems of threshold skew and gate oxide thickness enhancement. Additionally, it is believed that indium atoms within the channel region minimize hot carrier effects and the problems associated therewith.

2. 发明公开

EP0731494A2 Method for fabricating an integrated circuit using boron implant methodology 失效
标题翻译： Herstellungsverfahrenfürintegrierten Schaltkreis unter Benutzung von Bor-Implantat
公开(公告)号：EP0731494A2
公开(公告)日：1996-09-11
申请号：EP96301553.2
申请日：1996-03-06
申请人： ADVANCED MICRO DEVICES INC.
发明人： Anjum, Mohammed , Koop, Klaus H.
IPC分类号： H01L21/265
CPC分类号： H01L29/6659 , H01L21/26513 , H01L21/26586 , H01L29/42376 , H01L29/7833
摘要： A semiconductor structure with large tilt angle boron implant is provided for reducing threshold shifts or rolloff at the channel edges. By minimizing threshold shifts, short channel effects and subthreshold currents at or near the substrate surface are lessened. The semiconductor structure is prepared by implanting boron at a non-perpendicular angle into the juncture between the channel and the source/drain as well as the juncture between the field areas and the source/drain. Placement of boron into these critical regions replenishes segregating and redistributing threshold adjust implant species and channel stop implant species resulting from process temperature cycles. Using lighter boron ions allow for a lesser annealing temperature and thereby avoids the disadvantages of enhanced redistribution and diffusion caused by high temperature anneal.
摘要翻译：提供具有大倾角硼注入的半导体结构，用于减少通道边缘处的阈值偏移或滚降。通过最小化阈值偏移，减小衬底表面处或附近的短沟道效应和亚阈值电流。半导体结构是通过以非垂直角将硼注入到沟道和源极/漏极之间的接合部以及场区域和源极/漏极之间的接合处来制备的。将硼置入这些关键区域补充分离和重新分配阈值调整植入物种和通道停止植入物种，由过程温度循环产生。使用较轻的硼离子允许较小的退火温度，从而避免了由高温退火引起的增强的再分配和扩散的缺点。

3. 发明公开

EP0707345A1 Method for fabricating an integrated circuit 失效
标题翻译：一种用于制造集成电路装置的过程
公开(公告)号：EP0707345A1
公开(公告)日：1996-04-17
申请号：EP95307087.7
申请日：1995-10-06
申请人： ADVANCED MICRO DEVICES INC.
发明人： Anjum, Mohammed , Stuber, Alan, L. , Burki, Ibrahim, K.
IPC分类号： H01L29/08 , H01L21/8238
CPC分类号： H01L29/0847 , H01L21/823807
摘要： An MOS device is provided using indium as a threshold adjust implant in the channel regions of an NMOS device and/or in the conductive gate overlying the channel region in a PMOS device. Indium ions are relatively immobile and achieve location stability in the areas in which they are implanted. They do not readily segregate and diffuse in the lateral directions as well as in directions perpendicular to the silicon substrate. Placement immobility is necessary in order to minimize problems of threshold skew and gate oxide thickness enhancement. Additionally, it is believed that indium atoms within the channel region minimize hot carrier effects and the problems associated therewith.

4. 发明公开

EP0707346A1 Method for fabricating an integrated circuit 失效
标题翻译：制造集成电路的方法
公开(公告)号：EP0707346A1
公开(公告)日：1996-04-17
申请号：EP95307088.5
申请日：1995-10-06
申请人： ADVANCED MICRO DEVICES INC.
发明人： Anjum, Mohammed , Stuber, Alan L. , Burki, Ibrahim
IPC分类号： H01L29/10 , H01L21/8238
CPC分类号： H01L21/26513 , H01L21/823807 , H01L29/1045
摘要： An MOS device is provided using indium as a threshold adjust implant in the channel regions of an NMOS device and/or in the conductive gate overlying the channel region in a PMOS device. Indium ions are relatively immobile and achieve location stability in the areas in which they are implanted. They do not readily segregate and diffuse in the lateral directions as well as in directions perpendicular to the silicon substrate. Placement immobility is necessary in order to minimize problems of threshold skew and gate oxide thickness enhancement. Additionally, it is believed that indium atoms within the channel region minimize hot carrier effects and the problems associated therewith.
摘要翻译：提供使用铟作为NMOS器件的沟道区中的阈值调整注入和/或覆盖PMOS器件中的沟道区的导电栅极中的MOS器件。铟离子相对固定并且在其被植入的区域中实现位置稳定性。它们不容易在横向以及垂直于硅衬底的方向上分离和扩散。为了最小化阈值偏差和栅极氧化物厚度增强的问题，放置不动是必要的。另外，据信沟道区内的铟原子使热载流子效应和与之相关的问题最小化。

5. 发明公开

EP0682360A2 Method of forming a capacitor from a polysilicon layer 失效
标题翻译： Verfahren zur Herstellung eines Kondensators aus einer Polysiliziumschicht。
公开(公告)号：EP0682360A2
公开(公告)日：1995-11-15
申请号：EP95302951.9
申请日：1995-05-01
申请人： ADVANCED MICRO DEVICES INC.
发明人： Anjum, Mohammed , Koop, Klaus H. , Kyaw, Haung H.
IPC分类号： H01L21/3205 , H01L21/329
CPC分类号： H01L27/10852 , H01L27/10808 , H01L28/82 , H01L28/84 , Y10S148/014 , Y10S438/964
摘要： An enhanced capacitor configuration is provided in which the conductive and insulative layers are formed by implantation rather than deposition. The conductive regions are implanted at dissimilar depths and the insulative region is implanted between the conductive regions to form the conductive plates and intermediate dielectric material. By implanting rather than depositing, the dielectric material remains free of pinholes and can be configured thinner than conventional dielectrics, with a higher dielectric constant (k) due to the absence of an oxide. Moreover, cross-diffusions which occur during the anneal step allow texturization of the dielectric/conductive juncture. Texturization corresponds to an increase in surface area of the capacitor and, similar to increase in dielectric constant and decrease in dielectric thickness, increases the capacitive value of the ensuing capacitor.
摘要翻译：方法包括：在上表面形貌上沉积多晶硅; 植入P离子使得聚异构化成第一深度; 将N离子注入到非晶化区域中较浅的峰深度; 将P离子注入到较浅的深度; 并退火以形成夹持氮化物电介质的注入P区的电容器。氮化物-P层界面由于扩散而被纹理化，但消除了穿过氮化物的导电路径。第一P植入物在40keV至峰浓度为1×10 15 / cm 2。深度520埃; N型植入物在2.5keV至峰浓度为5×10 15 / cm 2。深度为80埃; 并且第二P植入物在0.5keV至峰浓度为1×10 13 / cm 2。深度22埃。聚合物在600℃以上退火，得到的氮化物层的介电常数高于3.0。然后加入电容器金属化。

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