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1. 发明公开

EP2230684A3 Integrierte Schaltungsanordnung mit niederohmigen Kontakten und Herstellungsverfahren 有权
标题翻译：与联系人和低制造方法集成电路装置
公开(公告)号：EP2230684A3
公开(公告)日：2011-08-24
申请号：EP10168883.6
申请日：2004-06-02
申请人： Infineon Technologies AG
发明人： Hofmann, Franz , Luyken, Richard Johannes , Rösner, Wolfgang , Specht, Michael
IPC分类号： H01L21/285 , H01L29/417
CPC分类号： H01L29/41783 , H01L21/28518 , H01L29/41725 , H01L29/665 , H01L29/78 , Y10S438/964
摘要： Erläutert wird unter anderem eine Schaltungsanordnung, die in einem Kontaktbereich eine Übergangsschicht (212) enthält, die von Teilen einer halbleitenden Materiallage (180) und von Teilen eines Anschlussbereiches (202) mehrfach durchdrungen wird. Durch diese Maßnahme verringert sich der Kontaktwiderstand erheblich.

2. 发明公开

EP1105880A4 METHOD AND APPARATUS FOR PROVIDING AN EMBEDDED FLASH-EEPROM TECHNOLOGY 有权
标题翻译：方法和设备嵌入式一体化FLAT STORE生产
公开(公告)号：EP1105880A4
公开(公告)日：2004-12-01
申请号：EP00930854
申请日：2000-05-24
申请人： KONINKL PHILIPS ELECTRONICS NV
发明人： CUNNINGHAM JAMES A , BLANCHARD RICHARD A
IPC分类号： H01L21/8247 , G11C16/04 , H01L21/28 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11519 , G11C16/0425 , H01L21/28273 , H01L27/115 , H01L29/42324 , Y10S438/964
摘要： Exemplary embodiments are directed to providing a flash EEPROM technology which is compatible with deep submicron dimensions, and which is suitable for straightforward integration with high performance logic technologies. Unlike known technologies, exemplary embodiments provide a reduced cell area size in a split gate cell structure. An exemplary process for implementing a flash EEPROM in accordance with the present invention involves growing a tunneling oxide (208) in a manner which reduces tunneling barrier height (202), and requires minimum perturbation to conventional high performance logic technologies, without compromising logic function performance.

3. 发明授权

EP0734060B1 Manufacture method of a DRAM capacitor storage electrode with textured surface 失效
标题翻译：具有结构化表面的DRAM电容器存储电极的制造过程的
公开(公告)号：EP0734060B1
公开(公告)日：2002-06-12
申请号：EP96302012.8
申请日：1996-03-22
申请人： Samsung Electronics Co., Ltd.
发明人： Kim, Kyung-hoon , Park, Young-wook , Yoo, Cha-young
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , Y10S438/964

4. 发明公开

EP1108267A1 CAPACITORS COMPRISING ROUGHENED PLATINUM LAYERS, METHODS OF FORMING ROUGHENED LAYERS OF PLATINUM AND METHODS OF FORMING CAPACITORS 有权
标题翻译：用于生产PLATINUM粗糙层，以及电容器的方法使这些粗糙的涂有铂层含
公开(公告)号：EP1108267A1
公开(公告)日：2001-06-20
申请号：EP99942541.6
申请日：1999-08-27
申请人： Micron Technology, Inc.
发明人： MARSH, Eugene, P.
IPC分类号： H01L21/285 , H01L29/92 , C23C16/18
CPC分类号： H01G4/005 , H01L23/53242 , H01L23/53247 , H01L23/53252 , H01L28/82 , H01L2924/0002 , Y10S438/964 , H01L2924/00
摘要： In one aspect, the invention includes a method of forming a roughened layer of platinum, comprising: a) providing a substrate within a reaction chamber; b) flowing an oxidizing gas into the reaction chamber; c) flowing a platinum precursor into the reaction chamber and depositing platinum from the platinum precursor over the substrate in the presence of the oxidizing gas; and d) maintaining a temperature within the reaction chamber at from about 0 °C to less than 300 °C during the depositing. In another aspect, the invention includes a platinum-containing material, comprising: a) a substrate; and b) a roughened platinum layer over the substrate, the roughened platinum layer having a continuous surface characterized by columnar pedestals having heights greater than or equal to about one-third of a total thickness of the platinum layer.

5. 发明授权

EP0642155B1 Method of manufacturing semiconductor capacitor electrode 失效
标题翻译：一种用于制造半导体电容器的电极的过程
公开(公告)号：EP0642155B1
公开(公告)日：2001-05-09
申请号：EP94113762.2
申请日：1994-09-02
申请人： NEC CORPORATION
发明人： Toshiyuki, Hirota, c/o NEC Corporation
IPC分类号： H01L21/3205 , H01L27/108
CPC分类号： H01L27/10844 , H01L21/32134 , H01L28/84 , Y10S438/964

6. 发明授权

EP0689252B1 Semiconductor device 失效
公开(公告)号：EP0689252B1
公开(公告)日：2000-08-02
申请号：EP95110516.2
申请日：1991-03-20
申请人： NEC CORPORATION
发明人： Watanabe, Hirohito , Tatsumi, Toru
IPC分类号： H01L29/92
CPC分类号： H01L27/10817 , H01L28/82 , H01L28/84 , H01L28/90 , Y10S438/964

7. 发明公开

EP0734060A1 DRAM capacitor storage electrode with textured surface 失效
标题翻译： DRAM-Kondensaotr-Speicherelektrode mit strukturierterOberfläche
公开(公告)号：EP0734060A1
公开(公告)日：1996-09-25
申请号：EP96302012.8
申请日：1996-03-22
申请人： Samsung Electronics Co., Ltd.
发明人： Kim, Kyung-hoon , Park, Young-wook , Yoo, Cha-young
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , Y10S438/964
摘要： A capacitor of a highly integrated semiconductor device and a manufacturing method therefor are provided. In the highly integrated semiconductor device, an HSG polysilicon layer pattern (46a) is formed having a multitude of hemispherical grains (50a) (HSG) on the top and side surfaces of the storage electrode.
Electrode separation is performed by selectively removing a silicide layer (52) that has been formed of a sacrificial metal layer (38) after the HSG step. The HSG polysilicon layer pattern does not have to be etched so that HSG polysilicon layer pattern (50a) on the top and side surfaces of conductive layer pattern (46a) remains intact.
摘要翻译：提供了一种高度集成的半导体器件的电容器及其制造方法。在高度集成的半导体器件中，在存储电极的顶表面和侧表面上形成有多个半球形晶粒（HSG）的HSG多晶硅层图案（46a）。通过选择性地去除在HSG步骤之后由牺牲金属层（38）形成的硅化物层（52）来进行电极分离。不需要蚀刻HSG多晶硅层图案，使得导电层图案（46a）的顶表面和侧表面上的HSG多晶硅层图案（50a）保持完整。

8. 发明授权

EP0420636B1 Method of controlling misfit dislocation 失效
标题翻译：一种用于失配位错的监视方法
公开(公告)号：EP0420636B1
公开(公告)日：1996-03-13
申请号：EP90310573.2
申请日：1990-09-27
申请人： SHIN-ETSU HANDOTAI COMPANY LIMITED
发明人： Miki, Katsuhiko , Naruke, Yukio
IPC分类号： H01L21/20 , H01L21/322
CPC分类号： H01L21/3221 , H01L21/02381 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L21/02658 , Y10S148/097 , Y10S148/127 , Y10S438/938 , Y10S438/964 , Y10S438/974

9. 发明公开

EP0642155A1 Method of manufacturing semiconductor capacitor electrode 失效
标题翻译： Verfahren zur Herstellung einer Halbleiter-Kondensator-Elektrode。
公开(公告)号：EP0642155A1
公开(公告)日：1995-03-08
申请号：EP94113762.2
申请日：1994-09-02
申请人： NEC CORPORATION
发明人： Toshiyuki, Hirota, c/o NEC Corporation
IPC分类号： H01L21/3205 , H01L27/108
CPC分类号： H01L27/10844 , H01L21/32134 , H01L28/84 , Y10S438/964
摘要： In a method of manufacturing a semiconductor device having a capacitor constituted by a lower electrode, an upper electrode, and a dielectric film arranged between the lower and upper electrodes, a polysilicon film containing a Group V element as an impurity is formed. The first etching step of forming an uneven portion on a surface of the polysilicon film is performed, it preferably etching the more highly doped crystal grain borders. The second etching step of forming an uneven portion on the surface of the polysilicon film is performed. The second etching step has an etch rate whose impurity concentration dependency is different from an impurity concentration dependency of an etch rate of the first etching step, preferably lower, and increases the width of recessed portions produced by the first etching step. It also removes porous silicon left by the first etching step.
摘要翻译：在制造具有由下电极，上电极和布置在下电极和上电极之间的电介质膜构成的电容器的半导体器件的制造方法中，形成含有作为杂质的V族元素的多晶硅膜。执行在多晶硅膜的表面上形成不均匀部分的第一蚀刻步骤，其优选地蚀刻更高掺杂的晶粒边界。执行在多晶硅膜的表面上形成不平坦部分的第二蚀刻步骤。第二蚀刻步骤具有其杂质浓度依赖性与第一蚀刻步骤的蚀刻速率的杂质浓度依赖性不同的蚀刻速率，优选较低，并且增加由第一蚀刻步骤产生的凹陷部分的宽度。它还去除了通过第一蚀刻步骤留下的多孔硅。

10. 发明授权

EP2230684B1 Herstellungsverfahren für integrierte Schaltungsanordnung mit niederohmigen Kontakten 有权
标题翻译：用于集成电路装置的制造过程中具有低电阻接触
公开(公告)号：EP2230684B1
公开(公告)日：2013-10-30
申请号：EP10168883.6
申请日：2004-06-02
申请人： Infineon Technologies AG
发明人： Hofmann, Franz , Luyken, Richard Johannes , Rösner, Wolfgang , Specht, Michael
IPC分类号： H01L21/285 , H01L29/417
CPC分类号： H01L29/41783 , H01L21/28518 , H01L29/41725 , H01L29/665 , H01L29/78 , Y10S438/964

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