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81. 发明公开

EP1891519A2 EFFICIENT SUBPROGRAM RETURN IN MICROPROCESSORS 有权
标题翻译：高效的子程序返回微处理器
公开(公告)号：EP1891519A2
公开(公告)日：2008-02-27
申请号：EP06771282.8
申请日：2006-05-25
申请人： Atmel Corporation
发明人： RENNO, Erik, K. , STROM, Oyvind , LUND, Morten, W.
IPC分类号： G06F9/44
CPC分类号： G06F9/30072 , G06F9/30054 , G06F9/30094 , G06F9/3806
摘要： A method and medium for performing subroutine return operations. Test operations (88, 90) are performed in parallel with other operations (92, 94) in a return operation (98) . These test operations (88, 90) and the return operations (96, 98) are performed in response to a single instruction (86) .

82. 发明公开

EP1880424A2 ULTRASCALABLE VERTICAL MOS TRANSISTOR WITH PLANAR CONTACTS 审中-公开
标题翻译：与PLANARKONTAKTEN ULTRA可扩展立式MOS晶体管
公开(公告)号：EP1880424A2
公开(公告)日：2008-01-23
申请号：EP06740920.1
申请日：2006-04-12
申请人： Atmel Corporation
发明人： LOJEK, Bohumil
IPC分类号： H01L29/94 , H01L21/8238
CPC分类号： H01L29/42332 , H01L21/823487 , H01L29/66666 , H01L29/7827 , H01L29/7881
摘要： A doped silicon block or island, formed above a drain electrode (17) in substrate (11) of a die or chip, has a height corresponding to the desired length of a channel (21, 23, 25). A source electrode (27) is formed above the silicon island and allows for contact (41) from above. Contact (43) from above may also be made with an L-shaped control gate (33, 35) and with the subsurface drain. A horizontal array of contacts for source, gate and drain is formed for the vertical transistor that is built. If nanocrystals (31) are incorporated into a layer (29) between the gate and the channel, a non-volatile floating gate transistor may be formed. Without the layer of nanocrystals, an MOS or CMOS transistor is formed.

83. 发明公开

EP1839314A2 SAMPLING AND LEVEL SHIFTING CIRCUIT 审中-公开
标题翻译：抽样和电平转换电路
公开(公告)号：EP1839314A2
公开(公告)日：2007-10-03
申请号：EP06718889.6
申请日：2006-01-18
申请人： ATMEL CORPORATION
发明人： RUNAR, Sorasen
IPC分类号： G11C27/02
CPC分类号： G11C27/026
摘要： A circuit (fig. 2) comprising a first switch (P1 and P2) for sampling a differential signal and a second switch (N1 and N2) for level shifting the sampled differential signal is disclosed. The first and second switches are cross-coupled to cancel a charge injected between the first and second switches and for linearizing the charge transfer; and a capacitor (124) coupled between the first and second switches. A circuit in accordance with the present invention adds an extra sampling switch (P3 and P4) to the sampling circuit and an extra charge transfer switch (N3 and N4) in the level shifting circuit. By cross coupling these extra switches, the result is a cancellation of the charge injection, and thus linearizing the charge transfer.

84. 发明授权

EP1086465B1 METHOD AND APPARATUS FOR A SERIAL ACCESS MEMORY 有权
标题翻译：操作和电路的串行存取存储器
公开(公告)号：EP1086465B1
公开(公告)日：2007-07-11
申请号：EP99916600.2
申请日：1999-04-09
申请人： ATMEL CORPORATION
发明人： NG, Philip, S. , SON, Jinshu , CHAN, Johnny
IPC分类号： G11C7/00 , G11C7/06 , G11C8/00
CPC分类号： G11C7/06 , G11C7/103 , G11C7/1039 , G11C7/1048 , G11C11/4096
摘要： A serial memory device (100) includes a Y decoder (108) and sensing circuitry (220-231; 720-723; 226-231; 820-827) which provide a predictive mode of operation, wherein data sensing of a target memory location begins before its address is fully known by sensing the data lines of a number of possible memory locations including the target location. The method and apparatus includes sensing first data bits of possible memory locations when some but not all of the address bits are clocked in. As additional address bits are clocked in, additional data bits are sensed. By the time the target address has been fully received, sensing of its first data bits will have completed so that serial outputting of the target memory can begin on the next clock. This sense-ahead feature permits an increase in the internal clock frequency without affecting external timing constraints imposed by the various serial memory device interfaces.

85. 发明授权

EP1423848B1 INDEPENDENT ASYNCHRONOUS BOOT BLOCK FOR SYNCHRONOUS NON-VOLATILE MEMORY DEVICES 有权
标题翻译：独立异步BOOT BLOCK同步不挥发存储器安排
公开(公告)号：EP1423848B1
公开(公告)日：2007-05-09
申请号：EP01991275.7
申请日：2001-12-19
申请人： ATMEL CORPORATION
发明人： FRANKLIN, Dirk, R. , HUI, Edward, S.
IPC分类号： G11B3/00
CPC分类号： G11C16/32 , G11C7/1072 , G11C7/20 , G11C16/08
摘要： A non-volatile memory device (20) having a main memory (23) that operates synchronously with the system clock and an asynchronous boot block (25). The boot block (25) can be activated to operate asynchronously upon initial power up or can be switched from synchronous to asynchronous mode upon receipt of a command signal by control logic circuitry within the device.

86. 发明公开

EP1779424A2 FABRICATION OF AN EEPROM CELL WITH EMITTER-POLYSILICON SOURCE/DRAIN REGIONS 审中-公开
标题翻译： MAKING WITH发射极多晶硅源/漏区甲EEPROM单元
公开(公告)号：EP1779424A2
公开(公告)日：2007-05-02
申请号：EP05762571.7
申请日：2005-06-20
申请人： ATMEL CORPORATION
发明人： CHAUDHRY, Muhammad, I.;
IPC分类号： H01L21/8238
CPC分类号： H01L21/8249 , H01L21/823425 , H01L27/0623 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11558
摘要： An EEPROM memory cell uses an emitter polysilicon film (701) for fabricating shallow source/drain regions to increase a breakdown voltage of the wells (105, 109, 111). The wells (105, 109, 111) are fabricated to be approximately 100 nm (0.1 micrometers (µm)) in depth with a breakdown voltage of approximately 14 volts or more. A typical breakdown voltage of a well in a bipolar process is approximately 10 volts. Due to the increased breakdown voltage achieved, EEPROM memory cells can be produced along with bipolar devices on a single integrated circuit chip and fabricated on a common semiconductor fabrication line.

87. 发明公开

EP1763713A2 METHOD AND SYSTEM FOR ENHANCED DIMMING RESOLUTION IN A LIGHT BALLAST THROUGH USE OF MULTIPLE CONTROL FREQUENCIES 有权
标题翻译：方法和系统用于改善DIMMLICHTVORSCHALTGERÄT分辨率使用多控制在不同频率
公开(公告)号：EP1763713A2
公开(公告)日：2007-03-21
申请号：EP05757493.1
申请日：2005-06-09
申请人： ATMEL CORPORATION
发明人： SAMUELSSON, Ulf, R.
IPC分类号： G05F1/00
CPC分类号： H05B41/3921 , H05B41/3925 , H05B41/3927 , Y10S315/04
摘要： A microcontroller or state machine controls a light ballast utilizing a timer structure. The microcontroller can program the timer structure to generate pulses where the 'average' frequency of a series of pulses can be varied with higher resolution than the frequency of a single pulse. This variation can occur without further microcontroller/state machine intervention. The pulses are used to control the on and/or off time of the light. The timer can be configured to modulate the outputs fast enough to ensure that the light does not appear to flicker to the human eye by limiting the number of pulses in a frame and by increasing the number of times the frequency shift occurs compared to the obvious implementation. The present invention relies on the fact that the human eye is not capable of detecting small frequency changes in high frequency signals and therefore uses pulses of two or more frequencies where the frequencies are close together. The average frequency can then be varied at much higher resolution than any single frequency.

88. 发明公开

EP1751664A1 BI-DIRECTIONAL SERIAL INTERFACE FOR COMMUNICATION CONTROL 审中-公开
标题翻译：双向串行通信控制器
公开(公告)号：EP1751664A1
公开(公告)日：2007-02-14
申请号：EP05725934.3
申请日：2005-03-18
申请人： ATMEL CORPORATION
发明人： DRESSEN, David, W. , GUEZ, Gregory S.
IPC分类号： G06F13/00
CPC分类号： G06F13/4291 , H04L5/14 , H04L25/45
摘要： A bi-directional serial interface (Fig. 3) for serial communication having a control line (48) to facilitate the transmission (46) of data to and from a microcontroller (44) and a serial interface module (42). The control line can be used by both the microcontroller and the serial interface module to send controlling signals (CTRL) such as start signals, receipt acknowledge signals, error signals, and stop signals. By having a dedicated control line that can be used by both the sending device and the receiving device, the present invention allows the initiation of a communication session by either the microcontroller or the serial interface.

89. 发明公开

EP1747592A1 NON-VOLATILE TRANSISTOR MEMORY ARRAY INCORPORATING READ-ONLY ELEMENTS WITH SINGLE MASK SET 审中-公开
标题翻译：只有READ不挥发晶体管存储矩阵使用单MASK KIT
公开(公告)号：EP1747592A1
公开(公告)日：2007-01-31
申请号：EP05724590.4
申请日：2005-03-03
申请人： ATMEL CORPORATION
发明人： WEINER, Albert, S.
IPC分类号： H01L31/119 , H01L31/108
CPC分类号： H01L27/112 , H01L27/0207 , H01L27/105 , H01L27/11286 , H01L27/115 , H01L27/11517 , H01L27/11526
摘要： A memory array has memory elements of identical topology or footprint arranged in rows and columns. Some of the memory elements are EEPROM cells (Figs. 1 and 2) and other memory elements are read only memory cells (Figs. 3-6) but all are made using a mask set having the same length and width dimensions. In the mask set for EEPROMs, a principal mask is used for formation of a depletion implant (23, 37). In the case of one type of read-only memory element (Figs. 3 and 4), this mask is mainly blocked, leading to formation of a transistor (51) with a non-conductive channel between source (25) and drain (55). In the case of another read only memory element (Figs. 5 and 6), the same mask is unblocked, leading to formation of a transistor (61) with a highly conductive or almost shorted channel (65) between source and drain. These two read only memory elements are designated as logic one and logic zero. By having rows of read-only memory elements with rows of EEPROMs on the same chip, a more versatile memory array chip may be built without sacrificing chip space.

90. 发明公开

EP1747559A2 METHOD AND APPARATUS FOR A DUAL POWER SUPPLY TO EMBEDDED NON-VOLATILE MEMORY 有权
标题翻译：用于向嵌入式非易失性存储器提供双电源的方法和设备
公开(公告)号：EP1747559A2
公开(公告)日：2007-01-31
申请号：EP05729910.9
申请日：2005-03-24
申请人： ATMEL CORPORATION
发明人： DAGA, Jean-Michel
IPC分类号： G11C16/08
CPC分类号： G11C16/12 , G11C5/145 , G11C5/147 , G11C8/08 , G11C16/30
摘要： A charge pump (407) is configured to receive the external voltage level (405) and generate a high voltage level (415), wherein the high voltage level is higher than the external voltage level. A memory control circuit (420) is configured to receive the external voltage level and the high voltage level, and to select one of the oltage levels. A memory array (430), with a word line and a bit line, is configured to receive the external and high voltage levels at the word line and the high voltage levels at the bit line. A word line driver (440) is configured to provide the external and high voltage levels to the word line. A bit line selector (455) is configured to select the bit line and receive the high, external, and regulated voltage levels. A bit line driver (450) is configured to provide the external voltage levels to the bit line selector (455).
摘要翻译：电荷泵（407）被配置为接收外部电压电平（405）并且生成高电压电平（415），其中高电压电平高于外部电压电平。存储器控制电路（420）被配置为接收外部电压电平和高电压电平，并且选择电压电平之一。具有字线和位线的存储器阵列（430）被配置为接收字线处的外部和高电压电平以及位线处的高电压电平。字线驱动器（440）被配置为向字线提供外部和高电压电平。位线选择器（455）被配置为选择位线并接收高，外部和调节的电压电平。位线驱动器（450）被配置为将外部电压电平提供给位线选择器（455）。

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