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1. 发明公开

EP1891516A2 SYSTEM AND METHOD FOR POWER SAVING IN PIPELINED MICROPROCESSORS 审中-公开
标题翻译：用于管道式微处理器中的节能的系统和方法
公开(公告)号：EP1891516A2
公开(公告)日：2008-02-27
申请号：EP06760325.8
申请日：2006-05-24
申请人： Atmel Corporation
发明人： RENNO, Erik, K. , STROM, Oyvind
IPC分类号： G06F9/30
CPC分类号： G06F1/3203 , G06F9/30141 , G06F9/3824 , G06F9/3826
摘要： A system and method for preserving power in a microprocessor pipeline (300). The system includes a register file read control unit (305), the read control unit (305) being configured to monitor one or more outputs from a control /decode unit (205) of the pipeline (300) and monitor write addresses from one or more other stages of the pipeline. The system also includes one or more read inhibit units (301, 303) each having an input, an output, and an enable terminal, the output of each of the one or more read inhibit units (301, 303) being coupled to a unique register port of a register file (109) within the pipeline (300). The input of each of the one or more read inhibit units (301, 303) being coupled to the control/decode unit (205), and the enable terminal of each of the one or more read inhibit units (301, 303) being coupled to a unique output of the read control unit (305).
摘要翻译：一种用于在微处理器管线（300）中保存功率的系统和方法。该系统包括寄存器文件读取控制单元（305），读取控制单元（305）被配置为监测来自流水线（300）的控制/解码单元（205）的一个或多个输出并且监视来自一个或多个管道的更多其他阶段。该系统还包括一个或多个读取禁止单元（301,303），每个读取禁止单元具有输入，输出和使能端子，一个或多个读取禁止单元（301,303）中的每一个的输出耦合到唯一的寄存器管道（300）内的寄存器文件（109）的端口。一个或多个读取禁止单元（301,303）中的每一个的输入端耦合到控制/解码单元（205），并且一个或多个读取禁止单元（301,303）中的每一个的使能端被耦合到读取控制单元（305）的唯一输出。

2. 发明公开

EP1987424A2 PACKED ADD-SUBTRACT OPERATION IN A MICRPROCESSOR 审中-公开
标题翻译：密封在微处理器加减操作
公开(公告)号：EP1987424A2
公开(公告)日：2008-11-05
申请号：EP07710165.7
申请日：2007-01-17
申请人： ATMEL CORPORATION
发明人： PEDERSEN, Ronny , RENNO, Erik, K. , STROM, Oyvind
IPC分类号： G06F9/44
CPC分类号： G06F7/505 , G06F7/49921 , G06F9/30014 , G06F9/30036 , G06F9/3885 , G06F17/142 , G06F2207/382
摘要： A packed half-word addition and subtraction operation is performed by a microprocessor in parallel upon half word operands obtained from designated top (_T) or bottom (_B) half-word locations of; designated source registers (REGA, REGB) of a register file (19) and the sum and difference results of such operation are packed into respective top and bottom half - word locations of a designated destination register (DST_REG). The microprocessor includes an arithmetic-logic unit (ALU 11) with adder circuitry that can be selectively split into separate half -word adders (13, 15) that are independently selectable (ADDSUB_CTL_T, ADDSUB_CTL_B) to perform -either an addition operation or subtraction operation upon the selected half-word operands (OP_B_T, OP_A_T, OP_B_B, OP_AB). The half word adders of the ALU access the operands from source registers via a set of multiplexers (21 - 26) that select among the top and bottom half-word locations. Operations with halving and saturation modifications to the sum and difference results may also be provided.

3. 发明授权

EP1891519B1 EFFICIENT SUBPROGRAM RETURN IN MICROPROCESSORS 有权
标题翻译：高效的子程序返回微处理器
公开(公告)号：EP1891519B1
公开(公告)日：2016-12-07
申请号：EP06771282.8
申请日：2006-05-25
申请人： Atmel Corporation
发明人： RENNO, Erik, K. , STROM, Oyvind , LUND, Morten, W.
IPC分类号： G06F9/38 , G06F9/44 , G06F9/30
CPC分类号： G06F9/30072 , G06F9/30054 , G06F9/30094 , G06F9/3806

4. 发明公开

EP1891519A2 EFFICIENT SUBPROGRAM RETURN IN MICROPROCESSORS 有权
标题翻译：高效的子程序返回微处理器
公开(公告)号：EP1891519A2
公开(公告)日：2008-02-27
申请号：EP06771282.8
申请日：2006-05-25
申请人： Atmel Corporation
发明人： RENNO, Erik, K. , STROM, Oyvind , LUND, Morten, W.
IPC分类号： G06F9/44
CPC分类号： G06F9/30072 , G06F9/30054 , G06F9/30094 , G06F9/3806
摘要： A method and medium for performing subroutine return operations. Test operations (88, 90) are performed in parallel with other operations (92, 94) in a return operation (98) . These test operations (88, 90) and the return operations (96, 98) are performed in response to a single instruction (86) .

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