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1. 发明公开

EP1634300A2 SIGNAL INTEGRITY CHECKING CIRCUIT 审中-公开
标题翻译：信号完整性检查电路
公开(公告)号：EP1634300A2
公开(公告)日：2006-03-15
申请号：EP04751942.6
申请日：2004-05-11
申请人： ATMEL CORPORATION
发明人： CHAN, Johnny , SON, Jinshu , YE, Ken, Kun , WONG, Tinwai
IPC分类号： G11C11/34
CPC分类号： G11C7/20 , G11C2029/0407
摘要： A signal integrity checking circuit (10) for an integrated circuit detects whether signal condition involving loading of data into storage elements is valid or improper and flags the result. The integrity circuit includes a plurality of adjacently positioned and substantially similar storage elements (13, 14), which are clocked by a common clock line (15) and loaded from a common data input line (16). A common reset line (R) may also be provided. The storage elements may be flip-flops, latches, RAM, etc. A logic gate (19), such as a NAND gate, receives the storage element outputs (Q) and flags (20) improper loading of data. Inverters (17, 18) on the input and output sides of one storage element force it to the opposite state from the other storage element. The signal integrity checking circuit is valuable for ensuring proper loading during power-on or start-up, and at other times when loading of data may occur.
摘要翻译：用于集成电路的信号完整性检查电路（10）检测涉及将数据加载到存储元件中的信号状态是否有效或不合适并标记结果。完整性电路包括由公共时钟线（15）计时并从公共数据输入线（16）加载的多个相邻定位且基本相似的存储元件（13,14）。公共复位线（R）也可以被提供。存储元件可以是触发器，锁存器，RAM等。诸如与非门的逻辑门（19）接收存储元件输出（Q）和标志（20）不正确的数据加载。一个存储元件的输入侧和输出侧上的逆变器（17,18）将其强制到与另一个存储元件相反的状态。信号完整性检查电路对于确保在加电或启动期间的正确加载以及在可能发生加载数据的其他时间是有价值的。

2. 发明公开

EP1652192A1 SHIFT REGISTER WITH REDUCED AREA AND POWER CONSUMPTION 审中-公开
标题翻译：具有降低的表面内容和消费移位寄存器
公开(公告)号：EP1652192A1
公开(公告)日：2006-05-03
申请号：EP04778856.7
申请日：2004-07-21
申请人： ATMEL CORPORATION
发明人： CHAN, Johnny , TSAI, Jeff, Ming-Hung , NG, Philip, S.
IPC分类号： G11C19/00
CPC分类号： G11C19/28
摘要： - A shift register device (30) includes transistor pass gates (36a-d) and latches (32a-d) connected in series and disposed along a data bit line (34), each latch connected to a corresponding transistor pass gate (36). Each transistor pass gate (36) is controlled by a separate control signal input line (C) that a provides a signal (S) to the transistor pass gate (36) connected to it. The signals (S1-S4) are provided in a staggered time pattern beginning with a latch (32d) disposed last in succession, shifting data from one position to the next succeeding position. Each latch (32) is capable of storing one bit of data. The shift register (30) utilizes less silicon space while reducing the amount of power consumed during operation.

3. 发明授权

EP2041751B1 METHOD AND APPARATUS TO PREVENT HIGH VOLTAGE SUPPLY DEGRADATION FOR HIGH-VOLTAGE LATCHES OF A NON-VOLATILE MEMORY 无效转让
标题翻译：用于防止高压电源恶化的高电压的方法和装置锁存器的非易失性存储器
公开(公告)号：EP2041751B1
公开(公告)日：2014-12-10
申请号：EP07784521.2
申请日：2007-06-22
申请人： Atmel Corporation
发明人： SON, Jinshu , CHAN, Johnny
IPC分类号： G11C16/10 , G11C7/10
CPC分类号： G11C7/1078 , G11C7/1087 , G11C16/10 , G11C2207/2227

4. 发明授权

EP1086465B1 METHOD AND APPARATUS FOR A SERIAL ACCESS MEMORY 有权
标题翻译：操作和电路的串行存取存储器
公开(公告)号：EP1086465B1
公开(公告)日：2007-07-11
申请号：EP99916600.2
申请日：1999-04-09
申请人： ATMEL CORPORATION
发明人： NG, Philip, S. , SON, Jinshu , CHAN, Johnny
IPC分类号： G11C7/00 , G11C7/06 , G11C8/00
CPC分类号： G11C7/06 , G11C7/103 , G11C7/1039 , G11C7/1048 , G11C11/4096
摘要： A serial memory device (100) includes a Y decoder (108) and sensing circuitry (220-231; 720-723; 226-231; 820-827) which provide a predictive mode of operation, wherein data sensing of a target memory location begins before its address is fully known by sensing the data lines of a number of possible memory locations including the target location. The method and apparatus includes sensing first data bits of possible memory locations when some but not all of the address bits are clocked in. As additional address bits are clocked in, additional data bits are sensed. By the time the target address has been fully received, sensing of its first data bits will have completed so that serial outputting of the target memory can begin on the next clock. This sense-ahead feature permits an increase in the internal clock frequency without affecting external timing constraints imposed by the various serial memory device interfaces.

5. 发明公开

EP1680744A2 METHOD AND SYSTEM FOR ENHANCING THE ENDURANCE OF MEMORY CELLS 审中-公开
标题翻译：方法和体系改善存储单元的强度
公开(公告)号：EP1680744A2
公开(公告)日：2006-07-19
申请号：EP04795162.9
申请日：2004-10-13
申请人： ATMEL CORPORATION
发明人： CHAN, Johnny , NG, Philip, S. , WONG, Tinwai
IPC分类号： G06F13/28
CPC分类号： G11C16/349
摘要： An integrated circuit device (10) includes a plurality of non-volatile memory cells (V1 and V2) associated with a plurality of flag cells (F1 and F2) storing managing data. The managing data of the flag cells (F1 and F2) forms a data set. The data set is utilized to determine to which memory cell of the plurality of memory cells (V1 and V2) to write new data and from which of the memory cells (V1 and V2) to read currently stored data. The data set is changed to a different data set whenever a new value is written to a designated memory cell to indicate an alternate memory cell to be written to next and an alternate memory cell to be read from next. The data set may be changed by alternately writing a new value to a different flag cell in each successive change of the data set.

6. 发明公开

EP1086465A1 METHOD AND APPARATUS FOR A SERIAL ACCESS MEMORY 有权
标题翻译：操作和电路的串行存取存储器
公开(公告)号：EP1086465A1
公开(公告)日：2001-03-28
申请号：EP99916600.2
申请日：1999-04-09
申请人： ATMEL CORPORATION
发明人： NG, Philip, S. , SON, Jinshu , CHAN, Johnny
IPC分类号： G11C7/00
CPC分类号： G11C7/06 , G11C7/103 , G11C7/1039 , G11C7/1048 , G11C11/4096
摘要： A serial memory device (100) includes a Y decoder (108) and sensing circuitry (220-231; 720-723; 226-231; 820-827) which provide a predictive mode of operation, wherein data sensing of a target memory location begins before its address is fully known by sensing the data lines of a number of possible memory locations including the target location. The method and apparatus includes sensing first data bits of possible memory locations when some but not all of the address bits are clocked in. As additional address bits are clocked in, additional data bits are sensed. By the time the target address has been fully received, sensing of its first data bits will have completed so that serial outputting of the target memory can begin on the next clock. This sense-ahead feature permits an increase in the internal clock frequency without affecting external timing constraints imposed by the various serial memory device interfaces.

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