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71. 发明公开

EP2006901A2 Procédé de fabrication d'une connexion électrique à base de nanotubes de carbone 审中-公开
标题翻译：一种用于碳纳米管的基础上产生电终端处理
公开(公告)号：EP2006901A2
公开(公告)日：2008-12-24
申请号：EP08354040.1
申请日：2008-06-17
申请人： Commissariat à l'Energie Atomique
发明人： Coiffic, Jean-Christophe
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L21/76879 , H01L21/76831 , H01L21/76844 , H01L23/53276 , H01L2221/1094 , H01L2924/0002 , H01L2924/00
摘要： Au moins un orifice, comportant un fond et des parois latérales est formé dans une couche (5) en matériau isolant séparant deux couches (4, 12) en matériau métallique. Une couche de catalyseur (9) est ensuite déposée. Puis une couche inhibitrice (11) est formée par dépôt directionnel sur les parois de l'orifice et sur la couche en matériau isolant (5), laissant libre uniquement ta partie de la couche de catalyseur (9) qui est disposée dans le fond de l'orifice. Des nanotubes sont ensuite formés dans ledit orifice et connectent électriquement les deux couches (4, 12) en matériau métallique,
摘要翻译：该方法包括经由包括底部形成并在绝缘材料，例如在侧壁氧化硅，层（5），并沉积催化剂层。上抑制层（11）被定向地沉积在通孔和绝缘材料层上的侧壁，并且该层是催化剂在通孔的底部布置。即纳米管碳纳米管，是生长在通过和金属材料的层（4）E. G. 铜，这些电极通过纳米管连接。阻挡层是催化剂（9）的沉积之前沉积。

72. 发明公开

EP1442153A4 GCIB PROCESSING TO IMPROVE INTERCONNECTION VIAS AND IMPROVED INTERCONNECTION VIA 审中-公开
标题翻译： GCIB处理用于连接接点和改进的接触的改进
公开(公告)号：EP1442153A4
公开(公告)日：2007-05-02
申请号：EP02778525
申请日：2002-10-11
申请人： EPION CORP
发明人： SKINNER WESLEY J , HAUTALA JOHN J
IPC分类号： H01L21/302 , C23C14/32 , H01J37/305 , H01L21/02 , H01L21/306 , H01L21/311 , H01L21/3213 , H01L21/322 , H01L21/461 , H01L21/768 , H01L23/48
CPC分类号： H01L21/02063 , H01J2237/0812 , H01J2237/31 , H01L21/02046 , H01L21/31116 , H01L21/32136 , H01L21/76814 , H01L21/76825 , H01L21/76831 , H01L21/76843 , H01L21/76844 , H01L21/76862 , H01L21/76865
摘要： Reactive gas cluster ion beam processing using gas cluster ions comprising a mixture of gases cleans and/or etches the bottoms of electrical interconnect vias and/or trenches in integrated circuits(900) to produce interconnect structures(902) with lower contact resistances and better reliability than was previously achieved with conventional processes. In one embodiment, an electrical interconnect via structure (902) uses a dielectric or high resistivity diffusion barrier material (702).

73. 发明授权

EP1183725B1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME 有权
标题翻译：半导体器件和方法及其
公开(公告)号：EP1183725B1
公开(公告)日：2007-01-24
申请号：EP01927704.5
申请日：2001-02-23
申请人： Koninklijke Philips Electronics N.V.
发明人： MEIJER, Petrus, M. , MUTSAERS, Cornelis, A., H., A.
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L21/76844 , H01L21/76807 , H01L21/76831 , H01L21/76843 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a semiconductor device comprising a substrate (1) comprising for instance silicon with thereon a layer (2, 4) comprising at least organic material which contains a passage (6, 8) to the substrate (1). The passage (6,8) has walls (7, 9) transverse to the layer (2, 4). A metal layer (11) is applied on the substrate (1) in at least that portion which adjoins the passage (8). The organic material forming the walls (7, 9) of the passage (6, 8) is covered with an oxide liner (12), and the passage (6, 8) is filled with a metal (14). According to the invention, a metal liner (13) comprising Ti or Ta is provided between the oxide liner (12) and the metal (14) filling the passage (6, 8). It is achieved by this that the device has a better barrier between the organic material (2, 4) and the interconnection metal (14) and that the organic material (2, 4) has a better protection during the various steps of the process.

74. 发明公开

EP1233449A3 A method of fabricating a semiconductor device 审中-公开
标题翻译：一种制造半导体器件的方法
公开(公告)号：EP1233449A3
公开(公告)日：2006-03-01
申请号：EP02447025.4
申请日：2002-02-15
申请人： Interuniversitair Micro-Elektronica Centrum
发明人： Vanhaelemeersch, Serge , Maex, Karen
IPC分类号： H01L21/768
CPC分类号： H01L21/76844 , H01L21/31138 , H01L21/76802 , H01L21/76831 , H01L21/76865 , H01L23/485 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The present invention is related to Integrated Circuit (IC) processing and fabrication. A device and a method are provided for etching an opening (4) in an insulating layer (3) while depositing a barrier layer (5) on the sidewalls of the opening without essentially depositing a barrier layer on the bottom of the opening.
摘要翻译：本发明涉及集成电路（IC）处理和制造。提供了一种用于在绝缘层（3）中蚀刻开口（4）的同时在开口的侧壁上沉积阻挡层（5）而基本不在开口的底部上沉积阻挡层的装置和方法。

75. 发明公开

EP1579497A2 METHOD FOR FORMING A SEMICONDUCTOR DEVICE AND STRUCTURE THEREOF 审中-公开
标题翻译：方法制造半导体器件及其结构
公开(公告)号：EP1579497A2
公开(公告)日：2005-09-28
申请号：EP03770538.1
申请日：2003-09-23
申请人： Freescale Semiconductor, Inc.
发明人： GOLDBERG, Cindy, K. , FILIPIAK, Stanley, M. , FLAKE, John, C. , LII, Yeong-Jyh, T. , SMITH, Bradley, P. , SOLOMENTSEV, Yuri, E. , SPARKS, Terry, G. , STROZEWSKI, Kirk, J. , YU, Kathleen, C.
IPC分类号： H01L21/768 , H01L21/288
CPC分类号： H01L21/76844 , H01L21/288 , H01L21/7682 , H01L21/76849 , H01L21/76874
摘要： Dummy features (64, 65, 48a, 48b) are formed within an interlevel dielectric layer (36). In one embodiment, a non-gap filling dielectric layer (72) is formed over the dummy features (64, 65, 48a, 48b) to form voids (74) between the dummy features (64, 65, 48a, 48b) or a dummy feature (48a) and a current carrying region (44). In one embodiment, passivation layers (32 and 54) are formed by electroless deposition to protect the underlying conductive regions (44, 48a, 48b and 30) from being penetrated from the air gaps (74). In addition, the passivation layers( 32 and 54) overhang the underlying conductive regions (44, 48a, 48b and 30), thereby defining dummy features (65a, 65b and 67) adjacent the conductive regions (48a, 44 and 48b). The passivation layers (32 and 54) can be formed without additional patterning steps and help minimize misaligned vias from puncturing air gaps.

76. 发明公开

EP1570518A2 A METHOD FOR DEPOSITING A METAL LAYER ON A SEMICONDUCTOR INTERCONNECT STRUCTURE 审中-公开
标题翻译：用于沉积金属层上半导体的方法INTERKONNEKTSTRUKTUR
公开(公告)号：EP1570518A2
公开(公告)日：2005-09-07
申请号：EP03799543.8
申请日：2003-12-08
申请人： International Business Machines Corporation
发明人： MALHOTRA, Sandra , SIMON, Andrew
IPC分类号： H01L21/768
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76865
摘要： Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor (14) is covered by a dielectric layer (18). The dielectric layer is patterned so as to expose the metal conductor. A liner layer (24) is then deposited into the pattern. The liner layer is then argon sputter etched to remove the liner layer and expose the metal conductor (14). In the process of argon sputter etching, the liner layer is redeposited onto the sidewall of the pattern. Lastly, an additional layer (26) is deposited into the pattern and covers the redeposited liner layer.

77. 发明公开

EP1459353A2 SELF-IONIZED AND INDUCTIVELY-COUPLED PLASMA FOR SPUTTERING AND RESPUTTERING 审中-公开
标题翻译： SELBSTIONISIERTES和电感耦合等离子体溅射和再溅射
公开(公告)号：EP1459353A2
公开(公告)日：2004-09-22
申请号：EP02784777.1
申请日：2002-12-10
申请人： Applied Materials, Inc.
发明人： DING, Peijun , XU, Zheng , MOSELY, Roderick, C. , RENGARAJAN, Suraj , MAITY, Nirmalya , CARL, Daniel, A. , CHIN, Barry , SMITH, Paul, F. , ANGELO, Darryl , TOLIA, Anish , FU, Jianming , CHEN, Fusen , GOPALRAJA, Praburam , TANG, Xianmin , FORSTER, John, C.
IPC分类号： H01J37/34 , H01J37/32
CPC分类号： H01L21/76844 , C23C14/046 , C23C14/345 , C23C14/3457 , C23C14/358 , H01J37/321 , H01J37/3408 , H01J2237/3327 , H01L21/2855 , H01L21/76805 , H01L21/76846 , H01L21/76862 , H01L21/76864 , H01L21/76865 , H01L21/76868 , H01L21/76873 , H01L21/76877 , H01L2221/1089
摘要： A magnetron sputter reactor for sputtering deposition materials such as tantalum, tantalum nitride and copper, for example, and its method of use, in which self-ionized plasma (SIP) sputtering and inductively coupled plasma (ICP) sputtering are promoted, either together or alternately, in the same chamber. Also, bottom coverage may be thinned or eliminated by ICP resputtering. SIP is promoted by a small magnetron having poles of unequal magnetic strength and a high power applied to the target during sputtering. ICP is provided by one or more RF coils which inductively couple RF energy into a plasma. The combined SIP-ICP layers can act as a liner or barrier or seed or nucleation layer for hole. In addition, an RF coil may be sputtered to provide protective material during ICP resputtering.

78. 发明公开

EP1439582A2 Image sensor device with copper interconnects and method for forming the same 有权转让
标题翻译： Herstellungsverfahrenfüreinen Bildsensor mit Kupfer-Leiterbahnen
公开(公告)号：EP1439582A2
公开(公告)日：2004-07-21
申请号：EP03018706.6
申请日：2003-08-25
申请人： Samsung Electronics Co., Ltd.
发明人： Lee, Soo-Guen , Park, Ki-Chul, 425-702 Kunyoung Apt. , Lee, Kyoung-Woo
IPC分类号： H01L27/146 , H01L31/0224 , H01L21/768 , H01L23/532
CPC分类号： H01L31/022408 , H01L21/76801 , H01L21/76805 , H01L21/76807 , H01L21/76843 , H01L21/76844 , H01L21/76865 , H01L23/53238 , H01L27/14623 , H01L27/14625 , H01L27/14627 , H01L27/14629 , H01L27/14632 , H01L27/14636 , H01L27/14685 , H01L2924/0002 , H01L2924/00
摘要： An image sensor device and method for forming the same include a photodiode formed in a substrate, at least one electrical interconnection line electrically associated with the photodiode, a light passageway having a light inlet, the light passageway being positioned in alignment with the photodiode, a color filter positioned over the light inlet of the light passageway and a lens positioned over the color filter in alignment with the light passageway wherein the at least one electrical interconnection line includes a copper interconnection formation having a plurality of interlayer dielectric layers in a stacked configuration with a diffusion barrier layer between adjacent interlayer dielectric layers, and a barrier metal layer between the copper interconnection formation and the plurality of interlayer dielectric layers and intervening diffusion barrier layers. An image sensor device may employ copper interconnections if a barrier metal layer is removed from above a photodiode.
摘要翻译：图像传感器装置及其形成方法包括形成在基板中的光电二极管，与光电二极管电连接的至少一个电互连线，具有光入口的光通道，光通路与光电二极管对准，位于光通道的光入口上方的滤色器和位于滤光器上的透镜，该透镜与光通路对准，其中至少一个电互连线包括具有堆叠构造的多个层间电介质层的铜互连结构，相邻层间电介质层之间的扩散阻挡层，以及铜互连结构与多个层间电介质层之间的阻挡金属层以及中间的扩散阻挡层。如果从光电二极管上方去除阻挡金属层，则图像传感器装置可以采用铜互连。

79. 发明公开

EP1246240A2 Method and apparatus for forming improved metal interconnects 审中-公开
标题翻译： Verfahren und Vorrichtung zur Herstellung verbesserter Metallleiterverbindungen
公开(公告)号：EP1246240A2
公开(公告)日：2002-10-02
申请号：EP02014021.6
申请日：1999-07-26
申请人： Applied Materials, Inc.
发明人： Hashim, Imran , Chiang, Tony , Chin, Barry
IPC分类号： H01L21/768 , H01L23/532 , H01L23/522
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76814 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76877 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming copper interconnects free from via-to-via leakage currents and having low resistances are disclosed. In a first aspect, a barrier layer is deposited on the first metal layer prior to copper oxide sputter-etching to prevent copper atoms from reaching the interlayer dielectric and forming via-to-via leakage current paths therein. In a second aspect, a capping dielectric barrier layer is deposited over the first metal layer prior to sputter-etching. During sputter-etching, the capping dielectric barrier layer redistributes on the sidewalls of the interlayer dielectric, preventing sputter-etched copper atoms from reaching the interlayer dielectric and forming via-to-via leakage paths therein. In a third aspect, both a capping dielectric barrier layer and a barrier layer are deposited over the first metal layer prior to sputter-etching to prevent copper atoms produced during sputter-etching.from reaching the interlayer dielectric and forming via-to-via leakage paths therein.
摘要翻译：公开了形成没有通孔到通孔泄漏电流并具有低电阻的铜互连的方法。在第一方面，在铜氧化物溅射蚀刻之前，在第一金属层上沉积阻挡层以防止铜原子到达层间电介质并且在其中形成通孔到通孔漏电流路径。在第二方面，在溅射蚀刻之前，在第一金属层上沉积封盖电介质阻挡层。在溅射蚀刻期间，封盖电介质阻挡层重新分布在层间电介质的侧壁上，防止溅射蚀刻的铜原子到达层间电介质并在其中形成通孔到通孔泄漏路径。在第三方面，在溅射蚀刻之前，在第一金属层上沉积封盖介电阻挡层和阻挡层，以防止在溅射蚀刻期间产生的铜原子，从而到达层间电介质并形成通孔到通孔泄漏路径。

80. 发明公开

EP1081754A3 Cleaning contact area with successive fluoride and hydrogen plasmas 审中-公开
标题翻译：接触表面的清洁通过连续氟化物和氢等离子体
公开(公告)号：EP1081754A3
公开(公告)日：2001-12-05
申请号：EP00307539.7
申请日：2000-09-01
申请人： Applied Materials, Inc.
发明人： Cohen, Barney M. , Su, Jingang , Ngan, Kenny King-Tai , Chen, Jr-Jyan
IPC分类号： H01L21/306 , H01L21/321 , H01L21/285
CPC分类号： H01L21/02063 , H01L21/76814 , H01L21/76843 , H01L21/76844 , Y10S438/906
摘要： A method of cleaning a contact area (17) of a semiconductor or metal region (12) on a substrate of an electronic device. First, the contact area is cleaned by exposing the substrate to a plasma that includes fluorine-containing species (102). Second, the substrate is exposed to a second atmosphere that scavenges fluorine (103) preferably formed by a plasma decomposition of a hydrogen-containing gas. The second atmosphere removes any fluorine residue remaining on the contact area and overcomes any need to include argon sputtering in the cleaning process. Another aspect of the invention is a method of depositing a refractory metal over a contact area of a semiconductor region on a substrate. The contact area is cleaned according to the two-step process. Then a refractory metal (52) is deposited over the contact area. The two-step cleaning process can reduce the electrical resistance between the refractory metal and the semiconductor region. Furthermore, if the substrate is annealed (104) to interdiffuse atoms of the semiconductor material and the refractory metal, the two-step cleaning process can reduce the anneal temperature required to achieve a desired low electrical resistance.

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