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41. 发明公开

EP0503904A2 Contact structure of an interconnection layer placed on a surface having steps and SRAM having a multilayer interconnection and manufacturing method thereof 失效
标题翻译：的接触结构安装在台阶表面和与多层互连和方法，用于其生产的SRAM电路层。
公开(公告)号：EP0503904A2
公开(公告)日：1992-09-16
申请号：EP92302045.7
申请日：1992-03-11
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Sakamoto, Osamu, c/o Mitsubishi Denki K.K.
IPC分类号： H01L27/11 , H01L23/522 , H01L21/82 , H01L21/90
CPC分类号： H01L27/1104 , H01L21/76877 , H01L23/53271 , H01L2924/0002 , Y10S257/903 , H01L2924/00
摘要： A silicon layer (1) in a lower layer and an interconnection layer (8a) arranged in an upper layer are electrically connected through an opening (16) for contact. A silicon plug layer (15) having the same conductivity type as that of the silicon layer is embedded in the opening. The silicon plug layer is embedded in the opening by an etch back method after deposited using a CVD method. The interconnection layer in the upper layer has conductivity type different from that of the silicon plug layer. A refractory metal silicide layer (11) is formed between the upper interconnection layer and the silicon plug layer.
The refractory metal silicide layer prevents pn junction from being formed between the upper interconnection layer and the silicon plug layer.
摘要翻译：在下层和在对上层布置互连层（8a）的甲硅层（1）被电通过为接触开口（16）相连接。具有相同的导电类型没有硅层的硅插塞层（15）被嵌入在开口中。该硅柱塞层嵌入在该开口通过使用CVD法沉积后，在回蚀刻方法。在上层中的布线层具有从硅酮不同确实插塞层的导电类型。难熔金属硅化物层（11）上互连层和硅插塞层之间形成。该难熔金属硅化物层与所述上互连层与该硅柱塞层之间形成防止pn结。

42. 发明公开

EP0499824A1 Stacked capacitor SRAM cell 失效
标题翻译： SRAM-Zelle mit geschichteterKapazität。
公开(公告)号：EP0499824A1
公开(公告)日：1992-08-26
申请号：EP92101131.8
申请日：1992-01-24
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Rodder, Mark S.
IPC分类号： G11C11/412
CPC分类号： H01L27/1104 , G11C11/4125
摘要： This is an SRAM cell and the cell can comprise: two NMOS drive transistors, two PMOS load transistors; first and second bottom capacitor plates 50,52 , with the first plate 50 being over a gate 34 of one of the drive transistors and the second plate 52 being over a gate 40 of another of the drive transistors; a layer of dielectric material 68 over the first and second bottom capacitor plates; and first and second top capacitor plates 20,26 over the dielectric layer, with the first top capacitor 20 plate forming a gate of one of the load transistors and with the second top capacitor plate 26 forming a gate of another of the load transistors, whereby the capacitor plates form two cross-coupled capacitors between the gates of the drive transistors and the stability of the cell is enhanced. This is also a method of forming an SRAM cell.
摘要翻译：这是一个SRAM单元，单元可以包括：两个NMOS驱动晶体管，两个PMOS负载晶体管; 第一和第二底部电容器板50,52，其中第一板50在驱动晶体管之一的栅极34之上，而第二板52位于另一个驱动晶体管的栅极40之上; 位于第一和第二底部电容器板上的电介质材料层68; 以及介电层上的第一和第二顶部电容器板20,26，其中第一顶部电容器20板形成负载晶体管之一的栅极，并且与第二顶部电容器板26形成另一个负载晶体管的栅极，由此电容器板在驱动晶体管的栅极之间形成两个交叉耦合的电容器，并且增强了电池的稳定性。这也是形成SRAM单元的方法。

43. 发明公开

EP0490877A3 Interconnection for an integrated circuit 失效
标题翻译：一体化电路互连
公开(公告)号：EP0490877A3
公开(公告)日：1992-08-26
申请号：EP92102717.3
申请日：1986-01-16
申请人： FAIRCHILD SEMICONDUCTOR CORPORATION
发明人： Vora, Madhukar , Burton, Greg , Kapoor, Ashok
IPC分类号： H01L21/90 , H01L21/285
CPC分类号： H01L21/8249 , H01L21/28518 , H01L21/76877 , H01L21/76885 , H01L21/76889 , H01L21/76895 , H01L23/485 , H01L23/528 , H01L23/53271 , H01L27/10805 , H01L27/1104 , H01L2924/0002 , H01L2924/00
摘要： An improved MOS transistor construction utilizes a polysilicon gate covered by silicide and silicide covered, self-aligned source and drain regions separated from the gate polysilicon by thin silicon dioxide spacers. No contact windows are formed within the perimeter of the isolation island. This allows for very small geometries. Electrical contact to the source and drain regions is provided by a conductive pattern formed in a layer of refractory metal which is in electrical contact with the source, drain and gate silicide and which extends over the field oxide to contact pad positions outside the isolation islands of the transistors. The contact pads located outside the isolation islands support post type vias or contact windows. The posts can be formed of different heights so that electrical contact by first and second metal layers to the source, gate and drain regions of the device can be made with the first and second metal layers separated by intermetal insulation. A process is disclosed for making high performance bipolar and high performance MOS devices on the same integrated circuit die which comprises forming isolation islands of epitaxial silicon surrounded by field oxide and forming MOS transistors having polysilicon gates in some islands and forming bipolar transistors having polysilicon emitters in other islands. Insulating spacers are then formed around the edges of the polysilicon electrodes by anisotropically etching a layer of insulation material. A layer of refractory metal is then deposited and heat treated at a temperature high enough to form silicide over the tops of the polysilicon electrodes and on top of the bases, sources and drains. Regions of this refractory metal are then masked off such that the electrical contact with the silicide is preserved and so that the refractory metal extends to a contact pad position external to the isolation island. Metal posts can be formed at the contact pad positions and a layer of planarized insulation material is formed so as to leave only the tops of the posts exposed. A layer of metal can then be deposited and etched to make electrical contact with tops of the posts. There is also disclosed a dynamic RAM cell using an MOS transistor and a CMOS static RAM cell comprising six MOS transistors having source, drain and gate electrodes which are smaller than the smallest contact window which can be made by the process which was used to make the transistor.

44. 发明公开

EP0478793A1 SUBSTRATE STRUCTURE OF A SEMICONDUCTOR DEVICE 失效
标题翻译： SUBSTRATSTRUKTUR FUR EINE HALBLEITERANORDNUNG。
公开(公告)号：EP0478793A1
公开(公告)日：1992-04-08
申请号：EP91906985.6
申请日：1991-04-12
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： FUJII, Syuso , SHIMIZU, Mitsuru , SAKURAI, Kiyofumi
IPC分类号： H01L27/04
CPC分类号： H01L27/1104 , H01L27/0248
摘要： A semiconductor memory device which is prevented from malfunction if a negative external potential (vin) is applied to an input circuit such as an address buffer circuit or a data-in buffer circuit during a function test. A p-well region (16) is formed in an n-type semiconductor substrate (11). A potential (V BB ) lower than the external input potential (Vin) is applied to the p-well region (16). There are formed a first n-type impurity diffused layer (12) to which the external input potential (Vin) is applied, and a second n-type impurity diffused layer (13) to which a reference potential (Vref) is applied. The potential (V BB ) applied to the well region is lower than Vin. Therefore, when Vin is negative, minority carriers generated do not migrate into the well region having a high energy potential and do not move into the second diffused layer. Therefore, Vref does not change and the device does not erroneously operate.
摘要翻译：一种半导体存储器件，在功能测试期间，如果在诸如地址缓冲电路或数据输入缓冲电路之类的输入电路上施加负的外部电位（vin），则防止其发生故障。 p型阱区（16）形成在n型半导体衬底（11）中。低于外部输入电位（Vin）的电位（VBB）被施加到p阱区域（16）。形成施加外部输入电位（Vin）的第一n型杂质扩散层（12）和施加基准电位（Vref）的第二n型杂质扩散层（13）。施加到阱区的电位（VBB）低于Vin。因此，当Vin为负时，产生的少数载流子不迁移到具有高能势的阱区，并且不移入第二扩散层。因此，Vref不变，器件不会错误地运行。

45. 发明授权

EP0222215B1 Polysilicon MOS transistor and method of manufacturing the same 失效
标题翻译：多晶硅MOS晶体管及其制造方法
公开(公告)号：EP0222215B1
公开(公告)日：1991-10-16
申请号：EP86114610.8
申请日：1986-10-22
申请人： HITACHI, LTD.
发明人： Saito, Ryuichi , Momma, Naohiro
IPC分类号： H01L29/78 , H01L21/31
CPC分类号： H01L29/66757 , H01L21/32155 , H01L27/0922 , H01L27/11 , H01L27/1104 , H01L27/1108 , H01L29/04 , H01L29/167 , H01L29/78618 , H01L29/78675 , H01L29/78684

46. 发明授权

EP0136106B1 Static random-access memory device 失效
标题翻译：静态随机存取设备
公开(公告)号：EP0136106B1
公开(公告)日：1990-10-17
申请号：EP84305917.1
申请日：1984-08-30
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kanazawa, Katsue , Toyoda, Nobuyuki , Hojo, Akimichi
IPC分类号： G11C11/40
CPC分类号： G11C11/418 , G11C11/412 , G11C11/419 , H01L27/11 , H01L27/1104

47. 发明公开

EP0359204A2 Semicondutor memory device capable of relieving defective bits 失效
标题翻译： Halbleiterspeicheranordnung，welche ein Herabsetzen der Anzahl mangelhafter Bits erlaubt。
公开(公告)号：EP0359204A2
公开(公告)日：1990-03-21
申请号：EP89116872.6
申请日：1989-09-12
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Segawa, Makoto c/o Intellectual Property Division
IPC分类号： G06F11/20 , G11C5/14 , G11C11/41 , G11C11/412 , H01L27/11
CPC分类号： G11C29/78 , G11C5/14 , G11C11/41 , G11C11/412 , G11C29/832 , H01L27/1104
摘要： A memory cell array includes static memory cells arranged in an array of n rows × m columns. Each of the memory cells includes MOS transistors formed in a semiconductor substrate (11) and in a corresponding one of well regions (12-1, 12-2, ---, 12-n) of the conductivity type opposite to that of the semiconductor substrate (11). The well regions (12-1, 12-2, ---, 12-n) are independently formed for each row or for every two or more rows of the memory cell array. The well regions (12-1, 12-2, ---, 12-n) are connected to the respective sources of MOS transistors formed in the well regions (12-1, 12-2, ---, 12-n). The source and back-gate of each of the MOS transistors formed in the well regions (12-1, 12-2, ---, 12-n) are connected to the common source wirings (14-1, 14-2, ---, 14-n) for each of the independently formed well regions (12-1, 12-2, ---, 12-n). Isolation circuits are respectively connected between the common source wirings (14-1, 14-2, ---, 14-n) for the respective well regions (12-1, 12-2, ---, 12-n) and the power source. A row of the memory cell array to which a defective memory cell is connected is isolated from the power source by means of the isolation circuits.
摘要翻译：存储单元阵列包括排列成n行×m列的阵列的静态存储单元。每个存储单元包括形成在半导体衬底（11）中的MOS晶体管，以及形成在导电类型相反的阱区（12-1,12-2，...，12-n）中的相应的一个阱区半导体衬底（11）。对于每行或每两行或多行存储单元阵列独立地形成阱区（12-1,12-2，...，12-n）。阱区域（12-1,12-2，...，12-n）连接到形成在阱区域（12-1,12-2，...，12-n）中的各个MOS晶体管源）。形成在阱区域（12-1,12-2，...，12-n）中的每个MOS晶体管的源极和背栅极连接到公共源极配线（14-1,14-2， ---，14-n），每个独立形成的阱区域（12-1,12-2，...，12-n）。隔离电路分别连接在各个阱区域（12-1,12-2，...，12-n）的公共源极配线（14-1,14-2，...，14-n）和电源。通过隔离电路将与缺陷存储单元连接的存储单元阵列的一行与电源隔离。

48. 发明公开

EP0334927A4 INTEGRATED CIRCUIT TRENCH CELL. 失效
标题翻译：与矿山综合电路单元。
公开(公告)号：EP0334927A4
公开(公告)日：1990-03-12
申请号：EP88908487
申请日：1988-08-12
申请人： MOTOROLA INC
发明人： TENG KER-WEN , WANG KARL L , NGUYEN BICH-YEN , WU WEI
IPC分类号： G11C11/412 , H01L21/8244 , H01L27/06 , H01L27/088 , H01L27/11 , H01L29/78
CPC分类号： H01L27/0629 , H01L27/088 , H01L27/1104 , H01L27/1112 , H01L29/7827 , Y10S257/903

49. 发明公开

EP0297350A3 Static ram cell with trench pull-down transistors and buried-layer ground plate 失效
标题翻译：静态RAM单元，带有TRENCH下拉晶体管和BALIED层接地板
公开(公告)号：EP0297350A3
公开(公告)日：1989-11-29
申请号：EP88109475.9
申请日：1988-06-14
申请人： INTEGRATED DEVICE TECHNOLOGY, INC.
发明人： Hsu, Fu-Chieh
IPC分类号： H01L27/11
CPC分类号： H01L27/11 , H01L21/74 , H01L23/53271 , H01L27/1104 , H01L27/1112 , H01L2924/0002 , Y10S257/903 , H01L2924/00
摘要： Disclosed is a (4T-2R) SRAM cell and method which achieves a much reduced cell area through the combined use of vertical trench pull-down n-channel transistors and a buried-layer ground plate. The reduced cell area allows the fabrication of a higher density SRAM for a given set of lithographic rules. The cell structure also allows the implementation of a (6T) SRAM cell with non-self-aligned poly-silicon p-channel pull-up transistors without appreciably enlarging the cell area.

50. 发明授权

EP0098111B1 Vertical IGFET device and method for fabricating same 失效
标题翻译：垂直IGFET装置及其制造方法
公开(公告)号：EP0098111B1
公开(公告)日：1989-08-09
申请号：EP83303637.9
申请日：1983-06-23
申请人： Harris Semiconductor Patents, Inc.
发明人： Jastrzebski, Lubomir Leon , Kokkas, Achilles George , Ipri, Alfred Charles
IPC分类号： H01L21/28 , H01L29/60 , H01L29/78
CPC分类号： H01L29/7827 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/28273 , H01L27/0688 , H01L27/1104 , H01L29/4236

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