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1. 发明公开

EP1308995A3 Semiconductor Device Having A Dielectric Layer With A Uniform Nitrogen Profile 审中-公开
标题翻译：一种半导体器件，包括具有均匀氮轮廓的介电层
公开(公告)号：EP1308995A3
公开(公告)日：2004-09-08
申请号：EP02102513.5
申请日：2002-10-31
申请人： Texas Instruments Incorporated
发明人： Hu, Jerry , Nicollian, Paul E. , Eason, Kwame N. , Khamankar, Rejesh , Rodder, Mark S. , Hattangady, Sunil
IPC分类号： H01L21/314
CPC分类号： H01L29/513 , H01L21/28202 , H01L21/3144 , H01L29/517 , H01L29/518
摘要： A method for manufacturing a semiconductor device includes forming a first layer (12) adjacent a semiconductor substrate (11). The first layer (12) may comprise oxygen. The first layer may be subjected to a material (14) comprising nitrogen to form a second layer. The second layer may be oxidized to form a dielectric layer which may have a relatively uniform nitrogen profile. Rapid thermal oxidation may be used to form the dielectric layer. The dielectric layer may have a physical thickness greater than a physical thickness of the second layer.

2. 发明公开

EP0899784A2 Semiconductor device and method of fabricating thereof 有权
标题翻译： Verfahren zur Herstellung einer Halbleiteranordnung
公开(公告)号：EP0899784A2
公开(公告)日：1999-03-03
申请号：EP98116186.2
申请日：1998-08-27
申请人： Texas Instruments Incorporated
发明人： Rodder, Mark S.
IPC分类号： H01L21/8238 , H01L29/423
CPC分类号： H01L29/0847 , H01L21/823842 , H01L29/42376 , H01L29/4933 , H01L29/495 , H01L29/66545 , Y10S438/902
摘要： Transistors may be fabricated by isolating a first region (16) of a semiconductor layer from a second region (18) of the semiconductor layer (12). A first disposable gate structure (26) of the first transistor may be formed over the first region (16) of the semiconductor layer (12). A second disposable gate structure (28) of the second, complementary transistor may be formed over the second region (18) of the semiconductor layer (12). A capping layer (60) may be formed over the first and second regions (16, 18) including the first and second disposable gate structures (26, 28). A portion (62, 64) of the first and second disposable gate structures (26, 28) may be exposed through the capping layer (60). A second disposable gate cap (66) may be formed over the exposed portion (64) of the second disposable gate structure (28) and at least part of the first disposable gate structure (26) removed. A first gate structure (70) of the first transistor may be formed in the place of removed part of the first disposable gate structure. In one embodiment, a second gate structure (80) of the second transistor may comprise the second disposable gate structure (28). In another embodiment, a first disposable gate cap (76) may be formed over the exposed portion (78) of the first gate structure and the second disposable gate cap (66) over the second disposable gate structure (28) may be removed. The second gate structure (80) of the second transistor may then be formed in the place of the removed second disposable gate structure (28).
摘要翻译：可以通过将半导体层的第一区域（16）与半导体层（12）的第二区域（18）隔离来制造晶体管。第一晶体管的第一一次性栅极结构（26）可以形成在半导体层（12）的第一区域（16）上。可以在半导体层（12）的第二区域（18）上形成第二互补晶体管的第二一次性栅极结构（28）。可以在包括第一和第二一次性栅极结构（26,28）的第一和第二区域（16,18）之上形成覆盖层（60）。第一和第二一次性栅极结构（26,28）的部分（62,64）可以通过覆盖层（60）暴露。可以在第二一次性栅极结构（28）的暴露部分（64）上形成第二一次性栅极盖（66），并且移除第一一次性栅极结构（26）的至少一部分。第一晶体管的第一栅极结构（70）可以形成在第一一次性栅极结构的去除部分的位置。在一个实施例中，第二晶体管的第二栅极结构（80）可以包括第二一次性栅极结构（28）。在另一个实施例中，可以在第一栅极结构的暴露部分（78）上形成第一一次性栅极盖（76），并且可以移除第二一次性栅极结构（28）上的第二一次性栅极盖（66）。然后可以形成第二晶体管的第二栅极结构（80）代替去除的第二一次性栅极结构（28）。

3. 发明公开

EP0899784A3 Semiconductor device and method of fabricating thereof 有权
标题翻译： Halbleiteranordnung und Verfahren zu deren Herstellung
公开(公告)号：EP0899784A3
公开(公告)日：1999-05-12
申请号：EP98116186.2
申请日：1998-08-27
申请人： Texas Instruments Incorporated
发明人： Rodder, Mark S.
IPC分类号： H01L21/8238 , H01L29/423
CPC分类号： H01L29/0847 , H01L21/823842 , H01L29/42376 , H01L29/4933 , H01L29/495 , H01L29/66545 , Y10S438/902
摘要： Transistors may be fabricated by isolating a first region (16) of a semiconductor layer from a second region (18) of the semiconductor layer (12). A first disposable gate structure (26) of the first transistor may be formed over the first region (16) of the semiconductor layer (12). A second disposable gate structure (28) of the second, complementary transistor may be formed over the second region (18) of the semiconductor layer (12). A capping layer (60) may be formed over the first and second regions (16, 18) including the first and second disposable gate structures (26, 28). A portion (62, 64) of the first and second disposable gate structures (26, 28) may be exposed through the capping layer (60). A second disposable gate cap (66) may be formed over the exposed portion (64) of the second disposable gate structure (28) and at least part of the first disposable gate structure (26) removed. A first gate structure (70) of the first transistor may be formed in the place of removed part of the first disposable gate structure. In one embodiment, a second gate structure (80) of the second transistor may comprise the second disposable gate structure (28). In another embodiment, a first disposable gate cap (76) may be formed over the exposed portion (78) of the first gate structure and the second disposable gate cap (66) over the second disposable gate structure (28) may be removed. The second gate structure (80) of the second transistor may then be formed in the place of the removed second disposable gate structure (28).
摘要翻译：可以通过将半导体层的第一区域（16）与半导体层（12）的第二区域（18）隔离来制造晶体管。第一晶体管的第一一次性栅极结构（26）可以形成在半导体层（12）的第一区域（16）上。可以在半导体层（12）的第二区域（18）上形成第二互补晶体管的第二一次性栅极结构（28）。可以在包括第一和第二一次性栅极结构（26,28）的第一和第二区域（16,18）之上形成覆盖层（60）。第一和第二一次性栅极结构（26,28）的部分（62,64）可以通过覆盖层（60）暴露。可以在第二一次性栅极结构（28）的暴露部分（64）上形成第二一次性栅极盖（66），并且移除第一一次性栅极结构（26）的至少一部分。第一晶体管的第一栅极结构（70）可以形成在第一一次性栅极结构的去除部分的位置。在一个实施例中，第二晶体管的第二栅极结构（80）可以包括第二一次性栅极结构（28）。在另一个实施例中，可以在第一栅极结构的暴露部分（78）上形成第一一次性栅极盖（76），并且可以移除第二一次性栅极结构（28）上的第二一次性栅极盖（66）。然后可以形成第二晶体管的第二栅极结构（80）代替去除的第二一次性栅极结构（28）。

4. 发明公开

EP0499855A2 Method and structure for microelectronic device incorporating low-resistivity straps between conductive regions 失效
标题翻译：一种用于在具有导电区域之间的低电阻桥微电子器件的方法和结构。
公开(公告)号：EP0499855A2
公开(公告)日：1992-08-26
申请号：EP92101538.4
申请日：1992-01-30
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Rodder, Mark S.
IPC分类号： H01L21/90 , H01L21/3205 , H01L21/285 , H01L23/485
CPC分类号： H01L21/76889
摘要： A microelectronic device (10) provides decreased contact and sheet resistivity for strap (24) and decreased contact resistivity with respect to gate (14) and/or moat (16). The inventive method allows strap (24) to overpass unrelated gate (20) if desired. In accordance with the invention, unrelated conductor (20) can be electrically isolated from overlying strap (24) by virtue of insulating (22). Further, strap (24) is formed to include titanium silicide layer (130) and noncrystalline silicon sublayer (132). Additionally, the strap formation process allows the patterning and removal of the silicide-forming metal, such as titanium, prior to the intended reaction of such metal with noncrystalline silicon to form a silicide, thereby avoiding the potential creation of undesired titanium oxide compounds which may generate undesirable shorting effects.
摘要翻译：的微电子器件（10）提供了用于减少带（24）和减少接触电阻率的接触和薄片电阻率相对于栅极（14）和/或壕沟（16）。本发明的方法允许带（24）立交桥无关栅极（20）如果需要清除。在符合本发明雅舞蹈的，无关的导体（20）可借助来自上覆带（24）电隔离的绝缘（22）。此外，条带（24）被形成为包括钛硅化物层（130）和非晶硅子层（132）。另外，所述带形成过程允许该图案化和除去硅化物形成金属的，颜色：诸如钛，之前寻求与非结晶硅金属，以形成硅化物，从而避免不希望的氧化钛化合物的潜在创建的预期反应可产生不希望的短路的效果。

5. 发明公开

EP0899793A2 Transistor having localized source and drain extensions and method 审中-公开
标题翻译：晶体管具有局部的源极和漏极扩展和方法
公开(公告)号：EP0899793A2
公开(公告)日：1999-03-03
申请号：EP98202868.0
申请日：1998-08-26
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Rodder, Mark S.
IPC分类号： H01L29/78 , H01L29/08 , H01L21/336
CPC分类号： H01L29/0847 , H01L21/26586 , H01L21/823418 , H01L27/0207 , H01L29/1083 , H01L29/66492 , H01L29/6659 , H01L29/7833 , H01L29/7836
摘要： A transistor comprising a gate electrode (22) insulated from a semiconductor layer (12). A channel region (94) may be defined in the semiconductor layer (12) inwardly of the gate electrode (22). A source region (92) may be formed in the semiconductor layer (12) between the channel region (94) and a first isolation member (16). The source region (92) may comprise a source main body (88) and a localized source extension (52). The localized source extension (52) may be spaced apart from the first isolation member (16) and extend from the source main body (88) to the channel region (94). A drain region (96) may be formed in a semiconductor layer (12) between the channel region (94) and a second isolation member (18). The drain region (96) may comprise a drain main body (90) and a localized drain extension (54). The localized drain extension (54) may be spaced apart from the second isolation member (18) and extend from the drain main body (90) to the channel region (94).
摘要翻译：一种晶体管，包括与半导体层（12）绝缘的栅电极（22）。沟道区域（94）可以在半导体层（12）中被限定在栅电极（22）的内部。源区（92）可以形成在沟道区（94）和第一隔离构件（16）之间的半导体层（12）中。源区（92）可以包括源主体（88）和局部源延伸（52）。局部源极延伸部（52）可以与第一隔离部件（16）间隔开并且从源主体（88）延伸到沟道区（94）。漏区（96）可以形成在沟道区（94）和第二隔离构件（18）之间的半导体层（12）中。漏极区（96）可以包括漏极主体（90）和局部漏极延伸部（54）。局部的漏极延伸部（54）可以与第二隔离构件（18）间隔开并且从漏极主体（90）延伸到沟道区域（94）。

6. 发明公开

EP0838849A2 A method of forming a mosfet 失效
标题翻译： Verfahren zur Herstellung采用了MOSFET
公开(公告)号：EP0838849A2
公开(公告)日：1998-04-29
申请号：EP97308619.2
申请日：1997-10-27
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Rodder, Mark S.
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/0847 , H01L29/41783 , H01L29/42376 , H01L29/66545 , H01L29/66606 , H01L29/66628 , Y10S438/926
摘要： A method for forming a MOSFET (200) using a disposable gate. A disposable gate (220) having at least two materials that may be etched selectively with respect to each other is formed on a substrate (202). A sidewall dielectric (215) is formed on the sidewalls of the disposable gate (220). The composition of the disposable gate materials (222, 223 and 224) and the sidewall dielectric (215) are chosen such that the disposable gate (220) may be removed selectively with respect to the sidewall dielectric (215). A dielectric layer (214) is then deposited over the structure and a portion of the dielectric layer (214) is removed to expose the disposable gate (220) (e.g. using CMP or an etch-back). The composition of the dielectric layer (214) is chosen such that (1) the dielectric layer (214) may be removed selectively with respect to the sidewall dielectric (215) and (2) a layer of the disposable gate (220) may be removed selectively with respect to the dielectric layer (214). The disposable gate (220) is then removed and the gate dielectric (210) and gate electrode (212) are formed.
摘要翻译：一种使用一次性栅极形成MOSFET（200）的方法。在衬底（202）上形成具有可相对于彼此选择性蚀刻的至少两种材料的一次性栅极（220）。侧壁电介质（215）形成在一次性门（220）的侧壁上。选择一次性栅极材料（222,223和224）和侧壁电介质（215）的组成，使得可以相对于侧壁电介质（215）选择性地移除一次性栅极（220）。然后将介电层（214）沉积在结构上，并且去除电介质层（214）的一部分以露出一次性栅极（220）（例如使用CMP或回蚀刻）。选择介电层（214）的组成，使得（1）可以相对于侧壁电介质（215）选择性地移除电介质层（214），和（2）一次性栅极（220）的层可以是相对于电介质层（214）有选择地移除。然后去除一次性栅极（220），并形成栅极电介质（210）和栅电极（212）。

7. 发明公开

EP1026738A3 Novel mixed voltage CMOS process for high reliability and high performance core and I/O transistors with reduced mask steps 有权
标题翻译：与用于生产具有高性能和高可靠性的-I / O晶体管混合电压CMOS晶体管的掩模的数量减少的过程
公开(公告)号：EP1026738A3
公开(公告)日：2004-06-23
申请号：EP00300969.3
申请日：2000-02-08
申请人： Texas Instruments Incorporated
发明人： Rodder, Mark S. , Nandakumar, Mahalingam , Mehrotra, Manoj
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814
摘要： A mixed voltage CMOS process for high reliability and high performance core transistors and input-output transistors with reduced mask steps. A gate stack (30) is formed over the silicon substrate (10). Ion implantation is performed of a first species and a second species to produce the doping profiles (70, 80, 90, 100) in the input-output transistors.

8. 发明公开

EP0926727A1 Process for manufacturing semiconductor device with migrated gate material 审中-公开
标题翻译： Herstellungsverfahrenfürein Halbleiterbauelement mit ausgetauschtem Gatematerial
公开(公告)号：EP0926727A1
公开(公告)日：1999-06-30
申请号：EP98204362.2
申请日：1998-12-22
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Rodder, Mark S.
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/28 , H01L21/336
CPC分类号： H01L29/66628 , H01L21/28079 , H01L21/82345 , H01L29/41783
摘要： Transistors may be fabricated by isolating a first region (16) of a semiconductor layer from a second region (18) of the semiconductor layer (12). A first disposable gate structure (26) of the first transistor may be formed over the first region (16) of the semiconductor layer (12). The first disposable gate structure (26) may comprise a replaceable material A second disposable gate structure (28) of the second complementary transistor may be formed over the second region (18) of the semiconductor layer (12). A replacement layer (70) may be formed over the first disposable gate structure (26). The replacement layer (70) may comprise a replacement material. At least a portion of the replaceable material of the first disposable gate structure (26) may be substitutionally replaced with the replacement material of the replacement layer (70) to form a first gate structure (80).
摘要翻译：可以通过将半导体层的第一区域（16）与半导体层（12）的第二区域（18）隔离来制造晶体管。第一晶体管的第一一次性栅极结构（26）可以形成在半导体层（12）的第一区域（16）上。第一一次性栅极结构（26）可以包括可替换材料。第二互补晶体管的第二一次性栅极结构（28）可以形成在半导体层（12）的第二区域（18）上。替换层（70）可以形成在第一一次性栅极结构（26）上。替换层（70）可以包括替换材料。第一一次性栅极结构（26）的可更换材料的至少一部分可替换地替换为置换层（70）的替换材料，以形成第一栅极结构（80）。

9. 发明授权

EP0499824B1 Stacked capacitor SRAM cell 失效
标题翻译： SRAM单元分层能力
公开(公告)号：EP0499824B1
公开(公告)日：1996-09-25
申请号：EP92101131.8
申请日：1992-01-24
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Rodder, Mark S.
IPC分类号： G11C11/412
CPC分类号： H01L27/1104 , G11C11/4125

10. 发明公开

EP0499855A3 Method and structure for microelectronic device incorporating low-resistivity straps between conductive regions 失效
标题翻译：在导电区域中并入低电阻条的微电子器件的方法和结构
公开(公告)号：EP0499855A3
公开(公告)日：1992-10-28
申请号：EP92101538.4
申请日：1992-01-30
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Rodder, Mark S.
IPC分类号： H01L21/90 , H01L21/3205 , H01L21/285 , H01L23/485
CPC分类号： H01L21/76889
摘要： A microelectronic device (10) provides decreased contact and sheet resistivity for strap (24) and decreased contact resistivity with respect to gate (14) and/or moat (16). The inventive method allows strap (24) to overpass unrelated gate (20) if desired. In accordance with the invention, unrelated conductor (20) can be electrically isolated from overlying strap (24) by virtue of insulating (22). Further, strap (24) is formed to include titanium silicide layer (130) and noncrystalline silicon sublayer (132). Additionally, the strap formation process allows the patterning and removal of the silicide-forming metal, such as titanium, prior to the intended reaction of such metal with noncrystalline silicon to form a silicide, thereby avoiding the potential creation of undesired titanium oxide compounds which may generate undesirable shorting effects.

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