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1. 发明授权

EP0093557B1 High-speed complementary semiconductor integrated circuit 失效
标题翻译：高速互补半导体集成电路
公开(公告)号：EP0093557B1
公开(公告)日：1989-07-12
申请号：EP83302315.3
申请日：1983-04-22
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Nii, Riro , Toyoda, Nobuyuki , Hojo, Akimichi , Yanai, Hisayoshi
IPC分类号： H01L27/08 , H01L27/12 , H01L29/24
CPC分类号： H01L27/12 , H01L29/245

2. 发明授权

EP0055140B1 Method of manufacturing a GaAs field effect transistor 失效
标题翻译：制造GAAS场效应晶体管的方法
公开(公告)号：EP0055140B1
公开(公告)日：1986-02-26
申请号：EP81306110.8
申请日：1981-12-23
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Toyoda, Nobuyuki , Hojo, Akimichi
IPC分类号： H01L21/28 , H01L21/64
CPC分类号： H01L29/66863 , H01L21/3245 , H01L29/80

3. 发明公开

EP0093557A3 High-speed complementary semiconductor integrated circuit 失效
标题翻译：高速互补半导体集成电路
公开(公告)号：EP0093557A3
公开(公告)日：1985-09-11
申请号：EP83302315
申请日：1983-04-22
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Nii, Riro , Toyoda, Nobuyuki , Hojo, Akimichi , Yanai, Hisayoshi
IPC分类号： H01L27/08 , H01L27/12 , H01L29/24
CPC分类号： H01L27/12 , H01L29/245
摘要： A complementary semiconductor integrated circuit device includes an electrical insulative substrate (10), a p-channel FET (Q 1 ) formed on the substrate (10) and consists of lead chalcogenide based semiconductive material, for example, PbTe, and an n-channel FET (0 2 ) consisting similarly of PbTe and to operates mutually and complementarily with the p-channel FET (Q 1 ). The PbTe constituting the FETs (Q,, Q 2 ) has electron and hole mobilities whose values are each greater by at least about one digit place than the value of a corresponding one of the electron and hole mobilities of silicon material. Accordingly, the device has an increased speed of operation.

4. 发明公开

EP0087251A3 Process for manufacturing a buried gate field effect transistor 失效
标题翻译：用于制造栅极场效应晶体管的方法
公开(公告)号：EP0087251A3
公开(公告)日：1986-04-16
申请号：EP83300709
申请日：1983-02-11
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Nii, Riro , Toyoda, Nobuyuki , Hojo, Akimichi
IPC分类号： H01L21/28 , H01L29/80
CPC分类号： H01L29/66462 , H01L21/28587 , H01L29/42316 , H01L29/7787 , H01L29/80
摘要： A process for manufacturing a buried gate field effect transistor having a small effective gate length, which process enables precise control of the threshold voltage. First, a compound semiconductor crystal (10) having a first impurity region (12) as a source region, a second impurity region (14) as a drain region and a channel layer (16) buried inside the compound semiconductor crystal (10) is prepared by a conventional process. A V-shaped groove is then formed with an etching solution having high selectivity toward the crystal face in the gate region of this compound semiconductor crystal. Onto the inner wall surface of the V-shaped groove, a metal (40) likely to form an alloy type of Schottky junction with the compound semiconductor is vapor-deposited. The resultant structure is heated, while measuring the threshold voltage, to form an alloy type of Schottky junction and for use of this junction as a gate electrode.

5. 发明公开

EP0093557A2 High-speed complementary semiconductor integrated circuit 失效
标题翻译： Schlele integriertekomplementäreHalbleiterschaltung。
公开(公告)号：EP0093557A2
公开(公告)日：1983-11-09
申请号：EP83302315.3
申请日：1983-04-22
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Nii, Riro , Toyoda, Nobuyuki , Hojo, Akimichi , Yanai, Hisayoshi
IPC分类号： H01L27/08 , H01L27/12 , H01L29/24
CPC分类号： H01L27/12 , H01L29/245
摘要： A complementary semiconductor integrated circuit device includes an electrical insulative substrate (10), a p-channel FET (Q 1 ) formed on the substrate (10) and consists of lead chalcogenide based semiconductive material, for example, PbTe, and an n-channel FET (0 2 ) consisting similarly of PbTe and to operates mutually and complementarily with the p-channel FET (Q 1 ). The PbTe constituting the FETs (Q,, Q 2 ) has electron and hole mobilities whose values are each greater by at least about one digit place than the value of a corresponding one of the electron and hole mobilities of silicon material. Accordingly, the device has an increased speed of operation.
摘要翻译：互补半导体集成电路器件包括电绝缘衬底（10），形成在衬底（10）上的p沟道FET（Q1），由基于硫族化物的半导体材料例如PbTe和n沟道FET （Q2），其类似地由PbTe组成并且与p沟道FET（Q1）相互和互补地操作。构成FET（Q1，Q2）的PbTe具有电子和空穴迁移率，其值比硅材料的电子和空穴迁移率的对应的一个值的值大至多一位数位置。因此，该装置具有增加的操作速度。

6. 发明授权

EP0087251B1 Process for manufacturing a buried gate field effect transistor 失效
标题翻译：用于制造BEDIED门式场效应晶体管的方法
公开(公告)号：EP0087251B1
公开(公告)日：1988-11-30
申请号：EP83300709.9
申请日：1983-02-11
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Nii, Riro , Toyoda, Nobuyuki , Hojo, Akimichi
IPC分类号： H01L21/28 , H01L29/80
CPC分类号： H01L29/66462 , H01L21/28587 , H01L29/42316 , H01L29/7787 , H01L29/80

7. 发明公开

EP0136106A3 Static random-access memory device 失效
标题翻译：静态随机存取设备
公开(公告)号：EP0136106A3
公开(公告)日：1986-02-19
申请号：EP84305917
申请日：1984-08-30
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kanazawa, Katsue , Toyoda, Nobuyuki , Hojo, Akimichi
IPC分类号： G11C11/40
CPC分类号： G11C11/418 , G11C11/412 , G11C11/419 , H01L27/11 , H01L27/1104
摘要： A static random-access memory device is disclosed which employs MESFETs formed on a gallium arsenide substrate. The memory device includes a plurality of memory cells C 11 -Cmn interconnected by word lines W 1 - W m and bit lines R 11 -Rn 1 , R 12 -Rn 2 . Each memory cell C 22 includes a flip-flop 14 and a pair of transfer gates connected between the flip-flop 14 and a pair of bit lines R 21 , R 22 . The transfer gates are formed by Schottky barrier gate field-effect transistors (MESFETs) 17, 18 having their gates connected to word line W 2 . Schottky barrier gate diodes D 1 , D 3 are connected in a forward bias direction between ground potential and the word lines W 2 to clamp the gate voltages to the MESFETs 17, 18 forming the transfer gates and to suppress current flow form the gates toward the sources or drains of the MESFETs 17, 18 to thereby prevent destruction of data stored in the memory cells and improve read-out reliability. Additional Schottky barrier gate diodes D 2 are connected in a forward bias direction between ground potential and drive line 6 2 for driving the gates of MESFETs 35, 36 forming switching circuit 3 for selecting the bit lines R 21 , R 22 connected to the transfer gates. These additional diodes D 2 serve the same purpose as the diodes D 1 , D 3 connected to the word lines W 2 .

8. 发明公开

EP0113161A2 Method of fabricating a schottky gate field effect transistor 失效
标题翻译：一种用于与肖特基栅极制造场效应晶体管过程。
公开(公告)号：EP0113161A2
公开(公告)日：1984-07-11
申请号：EP83304872.1
申请日：1983-08-23
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Toyoda, Nobuyuki , Terada, Toshiyuki , Mizoguchi, Takamaro , Hojo, Akimichi
IPC分类号： H01L21/28 , H01L29/80
CPC分类号： H01L29/66863 , H01L29/80 , H01L29/812
摘要： A Schottky gate FET is fabricated by forming on a semiconductor substrate (20) first and second stacks (26a, 26b) facing each other. Each stack (26a, 26b)-is constructed by an ohmic electrode (24a, 24b) and a spacer film (25a, 25b). On the substrate (20) having stacks (26a, 26b) formed thereon an insulation layer is formed and is anisotropically etched in the direction of its thickness until the planar surface portions are exposed. As a result, portions (27a, 27b) of the insulation layer remain on opposing side walls of the stacks (26a, 26b). After removing the spacer films (25a, 25b) to define stepped portions between each remaining portion (27a, 27b) and each electrode (24a, 24b), a layer of a metallic material capable of forming a Schottky barrier with the substrate (20) is formed. The remaining portions (27a, 27b) are removed to pattern the metallic material layer, thereby forming a Shottky gate electrode (28'c).

9. 发明公开

EP0083181A2 An integrated logic circuit 失效
标题翻译： Intergrated逻辑电路。
公开(公告)号：EP0083181A2
公开(公告)日：1983-07-06
申请号：EP82306768.1
申请日：1982-12-17
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Toyoda, Nobuyuki , Hojo, Akimichi
IPC分类号： H03K19/094
CPC分类号： H03K19/094 , H03K19/09407 , H03K19/0952
摘要： In an integrated logic circuit employing normally-off type FET's, it is difficult, but desirable to realize a NAND gate due to unwanted flow of the forward current to the next stage.
In accordance with the invention, a stable NAND gate operation can be realized by introducing a NOR gate (30) into all gate electrodes (IN1) of the inputs of the NAND gate, except one gate electrode (IN2) thereof of which source is grounded.

10. 发明授权

EP0136106B1 Static random-access memory device 失效
标题翻译：静态随机存取设备
公开(公告)号：EP0136106B1
公开(公告)日：1990-10-17
申请号：EP84305917.1
申请日：1984-08-30
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kanazawa, Katsue , Toyoda, Nobuyuki , Hojo, Akimichi
IPC分类号： G11C11/40
CPC分类号： G11C11/418 , G11C11/412 , G11C11/419 , H01L27/11 , H01L27/1104

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