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41. 发明公开

EP0292641A2 Output buffer of MOS semiconductor integrated circuit 失效
标题翻译： AusgangspufferfürMOS-integrierte Halbleiterschaltung。
公开(公告)号：EP0292641A2
公开(公告)日：1988-11-30
申请号：EP88101710.7
申请日：1988-02-05
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Kinugasa, Masanori c/o Patent Division , Shimazaki, Kenichiro , Tanaka, Fuminari c/o Patent Division
IPC分类号： H01L27/02 , H01L23/52 , H03K19/094
CPC分类号： H03K19/00361 , H01L23/528 , H01L27/11898 , H01L2924/0002 , H03K5/133 , H03K2005/00221 , H01L2924/00
摘要： An output buffer of a MOS semiconductor integrated circuit includes MOSFETs (Q11 to Q1n; Q21 to Q2n) constituting at least one of a driving and a load circuit, a resistive region (43; 44) connected to the gate electrodes (15-1 to 15-n; 20-1 to 20-n) of the MOSFETs (Q11 to Q1n; Q21 to Q2n), an insulation layer (10) formed on the gate wiring layers (15-1 to 15-n; 20-1 to 20-n) and the resistive regions (43; 44), and a metal wiring layer (23A) for signal input, formed on the insulation layer (10) and connected to the resistive regions (43; 44) via a contact hole (45; 46) formed in the insulation layer (10). The width of the contact hole (45; 46) is set so as to be less than the interval between any adjacent two of the gate wiring layers (15-1 to 15-n; 20-1 to 20-n). The metal wiring layer (23A) to which an input signal is supplied is connected to part of the resistive region (43; 44), so that the gate wiring lengths from the metal wiring layer (23A) to the gate electrodes of the MOSFETs (Q11 to Q1n; Q21 to Q2n) will be set to different values. Thus, an input signal is supplied to the MOSFETs (Q11 to Q1n; Q21 to Q2n) with different delay times to operate the MOSFETs (Q11 to Q1n; Q21 to Q2n) at different timings, causing the variation of an output signal to be gentle.
摘要翻译： MOS半导体集成电路的输出缓冲器包括构成驱动和负载电路中的至少一个的MOSFET（Q11至Q1n; Q21至Q2n），连接到栅电极的电阻区域（43,44） 15-n; 20-1至20-n）的MOSFET（Q11至Q1n; Q21至Q2n），形成在栅极布线层（15-1至15-n; 20-1至 20-n）和电阻区（43; 44）和用于信号输入的金属布线层（23A），形成在绝缘层（10）上，并经由接触孔（43; 44）连接到电阻区 45; 46）形成在所述绝缘层（10）中。接触孔（45; 46）的宽度被设定为小于任何相邻的两个栅极布线层（15-1至15-n; 20-1至20-n）之间的间隔。供给输入信号的金属布线层（23A）连接到电阻区域（43,44）的一部分，使得从金属布线层（23A）到MOSFET的栅电极 Q11至Q1n; Q21至Q2n）将被设置为不同的值。因此，以不同的延迟时间向MOSFET（Q11〜Q1n; Q21〜Q2n）供给输入信号，以在不同的定时对MOSFET（Q11〜Q1n; Q21〜Q2n）进行操作，使输出信号的变化为温和。

42. 发明公开

EP0286121A2 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：EP0286121A2
公开(公告)日：1988-10-12
申请号：EP88105638.6
申请日：1988-04-08
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Matsumoto, Osamu c/o Patent Division , Maruyama, Tadashi c/o Patent Division , Murata, Hiroyoshi c/o Patent Division , Abe, Isao , Shigematsu, Tomohisa c/o Patent Division , Shinada, Kazuyoshi c/o Patent Division , Suzuki, Yasoji c/o Patent Division , Kobayashi, Ichiro c/o Patent Division
IPC分类号： G11C16/04
CPC分类号： G11C16/0416 , G11C16/0425
摘要： A memory cell of a nonvolatile semiconductor memory device comprises a P conductive type semiconductor substrate (10), first and second diffusion layers of an N conductivity type, formed in the substrate, a channel region formed in the surface region of the substrate, and which is located between the first and second diffusion layers, a floating gate electrode (14) formed on the channel region, and a control gate electrode (15) formed on the floating gate electrode. The memory cell further includes a third diffusion layer of the N conductivity type, and formed between the first layer and the channel region, the third layer having an impurity concentration lower than that of the first layer.
摘要翻译：非易失性半导体存储器件的存储单元包括P导电类型的半导体衬底（10），形成在衬底中的N导电类型的第一和第二扩散层，形成在衬底的表面区域中的沟道区域，并且其位于第一扩散层和第二扩散层之间，形成在沟道区上的浮栅电极（14）和形成在浮栅电极上的控制栅电极（15）。存储单元还包括N导电类型的第三扩散层，并且形成在第一层和沟道区之间，第三层的杂质浓度低于第一层的杂质浓度。

43. 发明公开

EP0280883A2 Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：EP0280883A2
公开(公告)日：1988-09-07
申请号：EP88101335.3
申请日：1988-01-29
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Maruyama, Tadashi c/o Patent Division , Wada, Yukio c/o Patent Division , Suzuki, Yasoji c/o Patent Division , Shigematsu, Tomohisa c/o Patent Division , Yoshizawa, Makoto c/o Patent Division
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/26 , G11C16/0433 , G11C16/10
摘要： In a nonvolatile semiconductor memory according to the invention, a power source voltage of 5 V used in a ordinary read mode is applied to a read line (RL) in the data read mode without changing its value. If a write line (WL), a selection gate line (SG), a control gate line (CG), and a read line (RL) are respectively set at 0 V, 5 V, 0 V, and 5 V in the data read mode, the potential at an n-type diffusion layer (12) becomes 0 V. In this case, the potential at the control gate line (CG) is 0 V, and the potential at a floating gate electrode (16) becomes substantially 0 V. That is, an electric field is not applied to a thin insulating film (17) located between the floating gate electrode (16) and the n-type diffusion layer (12). As a result, electron injection and discharge due to the tunnel effect do not occur.
摘要翻译：在根据本发明的非易失性半导体存储器中，在数据读取模式中，在普通读取模式中使用的5V电源电压被施加到读取线（RL），而不改变其值。如果写入线（WL），选择栅极线（SG），控制栅极线（CG）和读取线（RL）分别设置为数据中的0V，5V，0V和5V 读取模式时，n型扩散层（12）处的电位变为0V。在这种情况下，控制栅极线（CG）处的电位为0V，并且浮置栅电极（16）处的电位变得基本上即，对位于浮置栅电极（16）和n型扩散层（12）之间的薄绝缘膜（17）不施加电场。结果，由隧道效应引起的电子注入和放电不会发生。

44. 发明公开

EP0122564A3 Read only memory 失效
标题翻译：只读存储器
公开(公告)号：EP0122564A3
公开(公告)日：1988-03-16
申请号：EP84103832
申请日：1984-04-06
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Iwahashi, Hiroshi , Asano, Masamichi 308 Denenchofu-Sky-Heights , Minagawa, Hidenobu
IPC分类号： G11C17/00
CPC分类号： G11C16/28
摘要： Data is read out from memory cells (M 11 - Mmn) in which "0" level and "1" level binary data have been stored, and a signal potential responsive to the readout data is compared with a comparison potential (VD) by a sense amplifier (SA), thereby sensing the data. In a comparison potential generator (20), the above comparison potential (VD) is set to have the intermediate potential between a potential (VBc) obtained by a dummy cell (Mc) in which the "1" level data has been stored, and a potential (VB d ) obtained by a dummy cell (M d ) in which the "0" level data has been stored.

45. 发明公开

EP0254139A2 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：EP0254139A2
公开(公告)日：1988-01-27
申请号：EP87109877.8
申请日：1987-07-08
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Nakai, Hiroto c/o Patent Division , Iwahashi, Hiroshi c/o Patent Division , Asano, Masamichi c/o Patent Division , Sato, Isao , Kumagai, Shigeru , Suzuki, Kazuto
IPC分类号： G11C16/00 , G11C17/00
CPC分类号： G11C16/32 , G11C16/30
摘要： A nonvolatile semiconductor memory device includes a pulse signal generator (ROS, IV6, IV7, BR) for applying a pulse signal to a capacitor (C), a first diode (T31) connected at an anode to the capacitor (C), a charging circuit (T29, T30, T33) for charging the capacitor (C) in a programming mode, a voltage limiter (T35, T36) for preventing a potential at the output node (SO) from increasing above a predetermined level, memory cells of nonvolatile MOS transistors (TM11 to TMMN), a load MOS transistor (T8) connected to a high-voltage. terminal (Vp), a row decoder (RDC, WSC) for selecting a set of memory cells arranged in one row, column gate MOS transistors (T91 to T9N) connected between respective sets of memory cells arranged in one column and the load MOS transistor (T8), a data generator (DG, DID) responsive .to the voltage at the output node (SO) to turn on or off the load MOS transistor (T8), and a column decoder (CSC, CDC) responsive to the voltage at the output node (SO) to selectively energize the column gate MOS transistors (T91 to T9N). It further comprises a second diode (T32) connected between the cathode of the first diode (T31) and the output node (SO), and a discharging circuit (T38, T39) for discharging the cathode of the first diode (T31) to a reference voltage level during a time other than a programming mode.
摘要翻译：一种非易失性半导体存储器件包括用于向电容器（C）施加脉冲信号的脉冲信号发生器（ROS，IV6，IV7，BR），在阳极与电容器（C）连接的第一二极管（T31）用于在编程模式下对电容器（C）充电的电路（T29，T30，T33），用于防止输出节点（SO）处的电势升高到预定电平以上的电压限制器（T35，T36），非易失性存储器单元 MOS晶体管（TM11至TMMN），连接至高电压的负载MOS晶体管（T8）。用于选择一行中排列的一组存储单元的行解码器（RDC，WSC），连接在排列成一列的各组存储单元之间的列选通MOS晶体管（T91至T9N），以及负载MOS晶体管（T8），响应于输出节点（SO）处的电压以导通或关断负载MOS晶体管（T8）的数据发生器（DG，DID）以及响应于该电压的列解码器（CSC，CDC）在输出节点（SO）选择性地激励列选通MOS晶体管（T91至T9N）。它还包括连接在第一二极管（T31）的阴极和输出节点（SO）之间的第二二极管（T32），以及用于将第一二极管（T31）的阴极放电到第一二极管参考电压电平在除了编程模式之外的时间期间。

46. 发明公开

EP0251275A2 Noise cancelling circuit 失效
标题翻译： Rauschunterdrückungsschaltung。
公开(公告)号：EP0251275A2
公开(公告)日：1988-01-07
申请号：EP87109329.0
申请日：1987-06-29
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Saito, Tomotaka c/o Patent Division , Ando, Kazumasa c/o Patent Division , Wada, Akira
IPC分类号： H03K5/01
CPC分类号： H03K5/1252
摘要： A noise cancelling circuit includes a delay circuit (19) for delaying an input signal which is supplied to an input terminal (18), and a signal processing circuit (Q1 to Q6, 23) responsive to the input signal and an output signal from the delay circuit (19), to generate an output signal corresponding to the input signal. The signal processing circuit has a first switching circuit, which includes first and second switching elements (Q1 and Q3) connected in series between a first power supply terminal (Vcc) and an output (20), and a second switching circuit, which includes third and fourth switching elements (Q2 and Q4) connected in series between a second power supply terminal and the output (20), wherein the first and third switching elements (Q1 and Q2) are responsive to the aforementioned input signal, by which they are set in mutually opposite conduction states, and the second and fourth switching elements (Q3 and Q4) are responsive to the output signal of the delay circuit (19), by which they too are set in mutually opposite conduction states.
摘要翻译：噪声消除电路包括用于延迟提供给输入端子（18）的输入信号的延迟电路（19）和响应于输入信号的信号处理电路（Q1至Q6,23）和来自延迟电路（19），以产生对应于输入信号的输出信号。信号处理电路具有第一开关电路，其包括串联连接在第一电源端子（Vcc）和输出端（20）之间的第一和第二开关元件（Q1和Q3），第二开关电路包括第三开关元件以及串联连接在第二电源端子和输出端（20）之间的第四开关元件（Q2和Q4），其中第一和第三开关元件（Q1和Q2）响应于上述输入信号而被设置在相互相反的导通状态下，第二和第四开关元件（Q3和Q4）响应于延迟电路（19）的输出信号，由此它们也被设置在相互相反的导通状态。

47. 发明公开

EP0244628A1 Sense amplifier for a semiconductor memory device 失效
标题翻译： Leseverstärkerfüreine Halbleiter-Speicheranordnung。
公开(公告)号：EP0244628A1
公开(公告)日：1987-11-11
申请号：EP87104661.1
申请日：1987-03-30
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Atsumi, Shigeru c/o Patent Division , Tanaka, Sumio c/o Patent Division , Otsuka, Nobuaki c/o Patent Division , Kamei, Takashi c/o Patent Division
IPC分类号： G11C7/06 , G11C11/34
CPC分类号： G11C16/3459 , G11C7/06 , G11C16/12 , G11C16/28 , G11C16/3454
摘要： In a sense amplifier, the first input terminal of the differential amplifier (26) is connected to a first MOS transistor (23) operating as a transfer gate, a first floating gate transistor (22) operating as a memory cell, and a first load (24). The gates of the first MOS transistor (23) and the first floating gate transistor (22) are respectively connected to the column-select line (BL) and the word line (WL). The second input terminal of the differential amplifier (26) is connected to a second load (28), a second MOS transistor (31) operating as a transfer gate, and a second floating gate transistor (32) operating as a dummy cell. The second load (28) has the same characteristics as the first load (24). The second load (28) is composed of first and second load elements (28A, 28B). The second floating gate transistor (32) is constantly supplied with power voltage. When a shift in the thre shold voltage of the first floating gate transistor (22) is monitored, the first load element (28A) of the second load (28) is disconnected from the input terminal of the differential amplifier (26), and only the second load element (28B) remains connected to the input terminal. The gate of the second MOS transistor (31) is supplied with the high potential. A gradually increasing potential is applied to the gates of the first MOS transistor (23) and the first floating gate transistor (22). The potential is detected when the data of the first floating gate transistor changes from "0" to "1".
摘要翻译：在读出放大器中，差分放大器（26）的第一输入端连接到作为传输门工作的第一MOS晶体管（23），作为存储单元工作的第一浮栅晶体管（22）和第一负载（24）。第一MOS晶体管（23）和第一浮栅晶体管（22）的栅极分别连接到列选择线（BL）和字线（WL）。差分放大器（26）的第二输入端连接到第二负载（28），作为传输栅极工作的第二MOS晶体管（31）和作为虚设单元工作的第二浮栅晶体管（32）。第二负载（28）具有与第一负载（24）相同的特性。第二负载（28）由第一和第二负载元件（28A，28B）组成。第二浮栅晶体管（32）经常被供给电源电压。当监视第一浮栅晶体管（22）的输出电压的偏移时，第二负载（28）的第一负载元件（28A）与差分放大器（26）的输入端断开，只有第二负载元件（28B）保持连接到输入端子。第二MOS晶体管（31）的栅极被提供高电位。对第一MOS晶体管（23）和第一浮栅晶体管（22）的栅极施加逐渐增加的电位。当第一浮栅晶体管的数据从“0”变为“1”时，检测电位。

48. 发明公开

EP0205104A3 Intermediate potential generation circuit 失效
标题翻译：中间电位发生电路
公开(公告)号：EP0205104A3
公开(公告)日：1987-09-23
申请号：EP86107643
申请日：1986-06-05
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Okada, Yoshio c/o Patent Division , Shimizu, Mitsuru
IPC分类号： H03H11/24 , G05F03/24
CPC分类号： G05F3/24 , H03H11/245
摘要： @ Two intermediate potentials (Vn1, Vn2) of small current driving capacity are generated using load elements (R3, R4) and MOStransistors (Q1, Q2), and are respectively supplied to the gates of two MOS transistors (Q3, Q4) which are series-connected between power sources (Vcc, Vss) and have large current driving capacity, thus obtaining an intermediate potential (VR) from a node (N3) between the MOS transistors (Q3, Q4). The MOS transistors (Q3, Q4) atthe output stage are complementarily operated so as not to be turned on at the same time.

49. 发明公开

EP0131930A3 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：EP0131930A3
公开(公告)日：1987-08-05
申请号：EP84108240
申请日：1984-07-13
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Isobe, Mitsuo c/o Patent Division , Sakurai, Takayasu c/o Patent Division , Sawada, Kazuhiro c/o Patent Division , Iizuka, Tetsuya c/o Patent Division , Ohtani, Takayuki c/o Patent Division , Aono, Akira
IPC分类号： G06F11/20
CPC分类号： G11C29/84 , G11C29/832
摘要： In the semiconductor memory device according to the present invention, when there is a defective portion in the memory cells (7-1 to 7-256), those memory cells are substituted by redundancy memory cells (17-1,17-2). When defective portions were discovered in the memory cells (7-1 to 7-256), the fuse elements (FS-1 to FS-256) corresponding to the memory cells (7-1 to 7-256) having the defective portions are cut off. Voltages of the select lines (5-1 to 5-256) connected to the memory cells having the defective portions are held at L level by the resistors (R-1 to R-256). Due to this, the memory cells (7-1 to 7-256) having the defective portions are not selected.
摘要翻译：在根据本发明的半导体存储器件中，当存储器单元（7-1至7-256）中存在缺陷部分时，那些存储器单元被冗余存储器单元（17-1,17-2）替代。当在存储单元（7-1至7-256）中发现缺陷部分时，与具有缺陷部分的存储单元（7-1至7-256）相对应的熔丝元件（FS-1至FS-256）隔断。连接到具有缺陷部分的存储器单元的选择线（5-1到5-256）的电压由电阻器（R-1到R-256）保持在L电平。由此，具有缺陷部分的存储器单元（7-1至7-256）未被选择。

50. 发明公开

EP0212589A2 Synchronous binary counter 失效
标题翻译： SynchronerBinärzähler。
公开(公告)号：EP0212589A2
公开(公告)日：1987-03-04
申请号：EP86111290.2
申请日：1986-08-14
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Iida, Tetsuya c/o Patent Division , Ikarashi, Takayoshi
IPC分类号： H03K23/50
CPC分类号： H03K23/50
摘要： synchronous binary circuit comprising a counter including J-K flip-flops (FF1 to FF8) constituting lower ! bit stages and higher m bit stages, first logic means (1, 2;13 to 16) for feeding, to J and K input terminals of each of flip-flops among the lower I bit stage flip-flops higher than the second bit stage, and AND of noninverted outputs of all the lower stage flip-flops than the pertinent stage, second logic means (3; 20) for feeding, to the J and K input terminals of the first stage flip-flops among the higher m bit stage flip-flops, a first logical product of the non-inverted output of a one bit lower stage flip-flop and non-inverted outputs of the first to (/-1 -th bit stage flip-flops among the lower bit stage flip-flops, and third logic means (4 1 , 4 2 , 5 1 , 5 2 , 6 1 , 6 2 , 26 to 28) for feeding, to the J and K input terminals of flip-flops among the higher m bit stage flip-flops higher than the second stage, a second logical product of non-inverted outputs of the lower first to (1-1) -th bit stage flip-flops and a third logical product, the third logical product being a logical product of an non-inverted output of a flip-flop lower by one bit than each of the flip-flops lower than the second stage and a fourth logical product, and the fourth logical product being a logical product of non-inverted outputs of flip-flops lower by more than two bit stages in the higher bit stage flip-flops.

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