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1. 发明公开

EP0254139A2 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：EP0254139A2
公开(公告)日：1988-01-27
申请号：EP87109877.8
申请日：1987-07-08
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Nakai, Hiroto c/o Patent Division , Iwahashi, Hiroshi c/o Patent Division , Asano, Masamichi c/o Patent Division , Sato, Isao , Kumagai, Shigeru , Suzuki, Kazuto
IPC分类号： G11C16/00 , G11C17/00
CPC分类号： G11C16/32 , G11C16/30
摘要： A nonvolatile semiconductor memory device includes a pulse signal generator (ROS, IV6, IV7, BR) for applying a pulse signal to a capacitor (C), a first diode (T31) connected at an anode to the capacitor (C), a charging circuit (T29, T30, T33) for charging the capacitor (C) in a programming mode, a voltage limiter (T35, T36) for preventing a potential at the output node (SO) from increasing above a predetermined level, memory cells of nonvolatile MOS transistors (TM11 to TMMN), a load MOS transistor (T8) connected to a high-voltage. terminal (Vp), a row decoder (RDC, WSC) for selecting a set of memory cells arranged in one row, column gate MOS transistors (T91 to T9N) connected between respective sets of memory cells arranged in one column and the load MOS transistor (T8), a data generator (DG, DID) responsive .to the voltage at the output node (SO) to turn on or off the load MOS transistor (T8), and a column decoder (CSC, CDC) responsive to the voltage at the output node (SO) to selectively energize the column gate MOS transistors (T91 to T9N). It further comprises a second diode (T32) connected between the cathode of the first diode (T31) and the output node (SO), and a discharging circuit (T38, T39) for discharging the cathode of the first diode (T31) to a reference voltage level during a time other than a programming mode.
摘要翻译：一种非易失性半导体存储器件包括用于向电容器（C）施加脉冲信号的脉冲信号发生器（ROS，IV6，IV7，BR），在阳极与电容器（C）连接的第一二极管（T31）用于在编程模式下对电容器（C）充电的电路（T29，T30，T33），用于防止输出节点（SO）处的电势升高到预定电平以上的电压限制器（T35，T36），非易失性存储器单元 MOS晶体管（TM11至TMMN），连接至高电压的负载MOS晶体管（T8）。用于选择一行中排列的一组存储单元的行解码器（RDC，WSC），连接在排列成一列的各组存储单元之间的列选通MOS晶体管（T91至T9N），以及负载MOS晶体管（T8），响应于输出节点（SO）处的电压以导通或关断负载MOS晶体管（T8）的数据发生器（DG，DID）以及响应于该电压的列解码器（CSC，CDC）在输出节点（SO）选择性地激励列选通MOS晶体管（T91至T9N）。它还包括连接在第一二极管（T31）的阴极和输出节点（SO）之间的第二二极管（T32），以及用于将第一二极管（T31）的阴极放电到第一二极管参考电压电平在除了编程模式之外的时间期间。

2. 发明授权

EP0254139B1 Nonvolatile semiconductor memory device 失效
公开(公告)号：EP0254139B1
公开(公告)日：1992-04-29
申请号：EP87109877.8
申请日：1987-07-08
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Nakai, Hiroto c/o Patent Division , Iwahashi, Hiroshi c/o Patent Division , Asano, Masamichi c/o Patent Division , Sato, Isao , Kumagai, Shigeru , Suzuki, Kazuto
IPC分类号： G11C16/00 , G11C17/00
CPC分类号： G11C16/32 , G11C16/30

3. 发明公开

EP0254139A3 Nonvolatile semiconductor memory device 失效
公开(公告)号：EP0254139A3
公开(公告)日：1991-01-09
申请号：EP87109877.8
申请日：1987-07-08
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Nakai, Hiroto c/o Patent Division , Iwahashi, Hiroshi c/o Patent Division , Asano, Masamichi c/o Patent Division , Sato, Isao , Kumagai, Shigeru , Suzuki, Kazuto
IPC分类号： G11C16/00 , G11C17/00
CPC分类号： G11C16/32 , G11C16/30
摘要： A nonvolatile semiconductor memory device includes a pulse signal generator (ROS, IV6, IV7, BR) for applying a pulse signal to a capacitor (C), a first diode (T31) connected at an anode to the capacitor (C), a charging circuit (T29, T30, T33) for charging the capacitor (C) in a programming mode, a voltage limiter (T35, T36) for preventing a potential at the output node (SO) from increasing above a predetermined level, memory cells of nonvolatile MOS transistors (TM11 to TMMN), a load MOS transistor (T8) connected to a high-voltage. terminal (Vp), a row decoder (RDC, WSC) for selecting a set of memory cells arranged in one row, column gate MOS transistors (T91 to T9N) connected between respective sets of memory cells arranged in one column and the load MOS transistor (T8), a data generator (DG, DID) responsive .to the voltage at the output node (SO) to turn on or off the load MOS transistor (T8), and a column decoder (CSC, CDC) responsive to the voltage at the output node (SO) to selectively energize the column gate MOS transistors (T91 to T9N). It further comprises a second diode (T32) connected between the cathode of the first diode (T31) and the output node (SO), and a discharging circuit (T38, T39) for discharging the cathode of the first diode (T31) to a reference voltage level during a time other than a programming mode.

4. 发明授权

EP0347935B1 Semiconductor memory device 失效
公开(公告)号：EP0347935B1
公开(公告)日：1995-07-26
申请号：EP89111475.3
申请日：1989-06-23
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Nakai, Hiroto , Iwahashi, Hiroshi , Kanazawa, Kazuhiha , Kumagai, Shigeru , Sato, Isao
IPC分类号： G11C16/06 , G11C7/06
CPC分类号： G11C7/12 , G11C7/062 , G11C7/14 , G11C16/28

5. 发明公开

EP0347935A2 Semiconductor memory device 失效
标题翻译： Halbleiterspeicheranordnung。
公开(公告)号：EP0347935A2
公开(公告)日：1989-12-27
申请号：EP89111475.3
申请日：1989-06-23
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Nakai, Hiroto , Iwahashi, Hiroshi , Kanazawa, Kazuhiha , Kumagai, Shigeru , Sato, Isao
IPC分类号： G11C16/06 , G11C7/06
CPC分类号： G11C7/12 , G11C7/062 , G11C7/14 , G11C16/28
摘要： In a semiconductor memory device, a first load circuit (14A) is coupled with the column lines (BL1,..., BLn). first dummy cells (DC1,..., DCm) are connected to a dummy column line (DBL), a second load circuit (14B) is connected to the dummy column line, a second dummy cell (DCm+1) is connected to the dummy column line, and a sense amplifier (15) senses the data stored in the memory cell in accordance with a potential difference between the column line and the dummy column line. In semiconductor memory devices thus arranged, the second dummy cell is set in an on state normally. The connection of the second dummy cell with the dummy line changes a current flowing to the dummy line at the time of row line switching, thereby to hold back a rise of the reference potential at the time of the row line switching.
摘要翻译：在半导体存储器件中，第一负载电路（14A）与列线（BL1，...，BLn）耦合。第一虚拟单元（DC1，...，DCm）连接到虚拟列线（DBL），第二负载电路（14B）连接到虚拟列线，第二虚设单元（DCm + 1）虚拟列线和读出放大器（15）根据列线和虚拟列线之间的电位差来感测存储在存储单元中的数据。在这样布置的半导体存储器件中，第二虚设单元被正常地设置为导通状态。第二虚拟单元与虚拟线的连接在行线切换时改变流向虚拟线的电流，从而在行线切换时保持基准电位的上升。

6. 发明公开

EP0347935A3 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：EP0347935A3
公开(公告)日：1991-05-29
申请号：EP89111475.3
申请日：1989-06-23
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Nakai, Hiroto , Iwahashi, Hiroshi , Kanazawa, Kazuhiha , Kumagai, Shigeru , Sato, Isao
IPC分类号： G11C16/06 , G11C7/06
CPC分类号： G11C7/12 , G11C7/062 , G11C7/14 , G11C16/28
摘要： In a semiconductor memory device, a first load circuit (14A) is coupled with the column lines (BL1,..., BLn). first dummy cells (DC1,..., DCm) are connected to a dummy column line (DBL), a second load circuit (14B) is connected to the dummy column line, a second dummy cell (DCm+1) is connected to the dummy column line, and a sense amplifier (15) senses the data stored in the memory cell in accordance with a potential difference between the column line and the dummy column line. In semiconductor memory devices thus arranged, the second dummy cell is set in an on state normally. The connection of the second dummy cell with the dummy line changes a current flowing to the dummy line at the time of row line switching, thereby to hold back a rise of the reference potential at the time of the row line switching.
摘要翻译：在半导体存储器件中，第一负载电路（14A）与列线（BL1，...，BLn）耦合。第一虚拟单元（DC1，...，DCm）连接到虚拟列线（DBL），第二负载电路（14B）连接到虚拟列线，第二虚拟单元（DCm + 1）连接到虚拟列线虚拟列线和读出放大器（15）根据列线和虚拟列线之间的电位差来读出存储在存储单元中的数据。在这样配置的半导体存储器件中，第二虚设单元通常处于导通状态。第二虚拟单元与虚拟线的连接在行线切换时改变流向虚拟线的电流，从而抑制行线切换时的参考电位的上升。

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