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1. 发明公开

EP0122564A3 Read only memory 失效
标题翻译：只读存储器
公开(公告)号：EP0122564A3
公开(公告)日：1988-03-16
申请号：EP84103832
申请日：1984-04-06
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Iwahashi, Hiroshi , Asano, Masamichi 308 Denenchofu-Sky-Heights , Minagawa, Hidenobu
IPC分类号： G11C17/00
CPC分类号： G11C16/28
摘要： Data is read out from memory cells (M 11 - Mmn) in which "0" level and "1" level binary data have been stored, and a signal potential responsive to the readout data is compared with a comparison potential (VD) by a sense amplifier (SA), thereby sensing the data. In a comparison potential generator (20), the above comparison potential (VD) is set to have the intermediate potential between a potential (VBc) obtained by a dummy cell (Mc) in which the "1" level data has been stored, and a potential (VB d ) obtained by a dummy cell (M d ) in which the "0" level data has been stored.

2. 发明公开

EP0137245A3 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：EP0137245A3
公开(公告)日：1987-01-07
申请号：EP84109957
申请日：1984-08-21
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation , Tosbac Computer System Co., Ltd.
发明人： Iwahashi, Hiroshi c/o Patent Division , Asano, Masamichi c/o Patent Division , Momodomi, Masaki c/o Patent Division , Minagawa, Hidenobu , Suzuki, Kazuto , Narita, Akira
IPC分类号： G11C17/00
CPC分类号： G11C16/12 , G11C16/30
摘要： A semiconductor integrated circuit which has a CMOS inverter formed of p- and n- channel MOSFETs (OP10 and QN10), and a D-type n-channel MOSFET (QN13) couped at the gate to the output terminal of the CMOS inverter, at one end of the current path to a high voltage terminal (VH) applied with a high voltage and at the other end to the current path of the p-channel MOSFET (OP10) is provided.

3. 发明授权

EP0301588B1 Semiconductor memory device 失效
公开(公告)号：EP0301588B1
公开(公告)日：1994-01-19
申请号：EP88112373.1
申请日：1988-07-29
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Tatsumi, Yuuichi , Minagawa, Hidenobu , Iwahashi, Hiroshi c/o Patent Division , Asano, Masamichi c/o Patent Division , Imai, Mizuho
IPC分类号： G11C16/06
CPC分类号： G11C16/28

4. 发明公开

EP0301588A3 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：EP0301588A3
公开(公告)日：1991-01-23
申请号：EP88112373.1
申请日：1988-07-29
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Tatsumi, Yuuichi , Minagawa, Hidenobu , Iwahashi, Hiroshi c/o Patent Division , Asano, Masamichi c/o Patent Division , Imai, Mizuho
IPC分类号： G11C16/06
CPC分类号： G11C16/28
摘要： A semiconductor memory device includes word lines (WL1-Wln) selectively driven by a signal from a row decoder (RD), memory cells (MC11-MCn) connected to word liens (WL1-WLn), first and second data liens (DL1, DL2) , a bit line (BL1) connected to receive data from the memory cell (MC11-MCn1) and to supply received data to the first data liens (DL1), dummy cells (DMC1-DMCn) connected to word lies (WL1-WLn), first and second dummy data liens (DDL1, DDL2), a dummy bit liens (DBL) connected to receive data from the dummy memory cell (DMC1-DMCn) and to supply received data to the first dummy data line (DDL1), a data sensing circuit (2) for generating an output signal corresponding to a potential difference between the second data line (DL2) and second dummy data line (DDL2), a first MOS transistor (T8) connected between the first and second data lines (DL1, DL2), a first load circuit (12) for charging the second data line (DL2), a second MOS transistor (T10) connected between the first and second dummy data liens (DDL1, DDL2), and a second load circuit (11) for charging the second dummy data liens (DDL2). The memory device further includes a first equalizer circuit (21) connected between the second data line (LD2) and dummy data line (DDL2) and equalizing potentials at both ends during a predetermined period of time after the semiconductor memory device is set in the active mode, and a second equalizer circuit (22) connected between the data line (DL1) and dummy data line (DDL1) and equalizing potential as at both ends during a predetermined period of time after the memory device is set in the active mode.
摘要翻译：半导体存储器件包括由来自行解码器（RD）的信号有选择地驱动的字线（WL1-Wln），连接到字符余量（WL1-WLn）的存储单元（MC11-MCn），第一和第二数据帧（DL1，（WL1-DL2），被连接以从存储单元（MC11-MCn1）接收数据并将接收的数据提供给第一数据寄存器（DL1）的位线（BL1），连接到字的谎言单元（DMC1- WLn），第一和第二伪数据寄存器（DDL1，DDL2），被连接以从伪存储单元（DMC1-DMCn）接收数据并将接收到的数据提供给第一伪数据线（DDL1）的伪位（DBL），用于产生对应于第二数据线（DL2）和第二虚拟数据线（DDL2）之间的电位差的输出信号的数据读出电路（2），连接在第一和第二数据线（DDL2）之间的第一MOS晶体管（T8）（DL1，DL2），用于对第二数据线（DL2）充电的第一负载电路（12），第二MOS晶体管（T10），连接在第二数据线第一和第二虚拟数据寄存器（DDL1，DDL2）以及用于给第二虚拟数据寄存器（DDL2）充电的第二负载电路（11）。存储器件还包括连接在第二数据线（LD2）和伪数据线（DDL2）之间的第一均衡器电路（21），并且在半导体存储器件被设置为有效状态之后的预定时间段内在两端均衡电位以及连接在数据线（DL1）和虚拟数据线（DDL1）之间的第二均衡器电路（22），以及在存储器件被设置为活动模式之后的预定时间段期间两端处的均衡电势。

5. 发明授权

EP0301603B1 Output circuit of semiconductor integrated circuit device 失效
标题翻译：一种半导体集成电路的输出电路。
公开(公告)号：EP0301603B1
公开(公告)日：1993-12-01
申请号：EP88112482.0
申请日：1988-08-01
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Tatsumi, Yuuichi , Minagawa, Hidenobu , Iwahashi, Hiroshi , Asano, Masamichi , Imai, Mizuho
IPC分类号： G11C7/00 , H03K19/00
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/22 , H03K19/00361

6. 发明公开

EP0306990A3 Semiconductor memory device with dummy cell array 失效
标题翻译：具有DUMMY CELL ARRAY的半导体存储器件
公开(公告)号：EP0306990A3
公开(公告)日：1991-07-10
申请号：EP88114825.8
申请日：1988-09-09
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Minagawa, Hidenobu , Tatsumi, Yuuichi , Iwahashi, Hiroshi , Asano, Masamichi , Imai, Mizuho
IPC分类号： G11C17/00 , G11C29/00
CPC分类号： G11C29/50012 , G11C16/04 , G11C16/08 , G11C16/28 , G11C16/32 , G11C16/34 , G11C29/24 , G11C29/50 , G11C29/52
摘要： A semiconductor memory device in which data can be read out in response to an address signal comprises power source lines, a plurality of row (WL1 - WLmn) and column conductive lines (COL1 - COLn), a memory cell array (10) including nonvolatile memory cells (M11 - Mmn) arranged in a matrix form of rows and columns and respectively connected to the plurality of row and column lines (COL1 - COLn, WL1 - WLn) and the power source lines, a first selector circuit (5) for generating a signal for selecting the row conductive lines in response to an address signal, a dummy row line (DWL), and dummy memory cells (DM1 - DMn) each having a source, a drain and a control gate connected to the dummy row line (DWL). In the semiconductor memory device, one of paths between the source and the power source line and between the drain and the corresponding row line is closed and the other path is opened, and it further includes a second selector circuit (11) for selectively generating a line selection signal for selecting one of the row conductive lines in response to an address signal and a dummy selection signal for selecting the dummy row line (DWL) in response to the same address signal.

7. 发明公开

EP0301603A3 Output circuit of semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的输出电路
公开(公告)号：EP0301603A3
公开(公告)日：1991-04-03
申请号：EP88112482.0
申请日：1988-08-01
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Tatsumi, Yuuichi , Minagawa, Hidenobu , Iwahashi, Hiroshi , Asano, Masamichi , Imai, Mizuho
IPC分类号： G11C7/00 , H03K19/00
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/22 , H03K19/00361
摘要： A semiconductor integrated circuit includes an output circuit (22) and a control circuit (23) for controlling the output circuit (22). The control circuit (23) controls the output circuit (22) so as to charge or discharge a preset node in the output circuit (22) at a rate different from an ordinary charging or discharging rate for a preset period of time after a control signal (OE* and OE* ) has been changed in level.

8. 发明授权

EP0137245B1 Semiconductor integrated circuit 失效
公开(公告)号：EP0137245B1
公开(公告)日：1990-03-14
申请号：EP84109957.5
申请日：1984-08-21
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation , Tosbac Computer System Co., Ltd.
发明人： Iwahashi, Hiroshi c/o Patent Division , Asano, Masamichi c/o Patent Division , Momodomi, Masaki c/o Patent Division , Minagawa, Hidenobu , Suzuki, Kazuto , Narita, Akira
IPC分类号： G11C17/00
CPC分类号： G11C16/12 , G11C16/30

9. 发明公开

EP0306990A2 Semiconductor memory device with dummy cell array 失效
标题翻译： Halbleiterspeicheranordnung mit einem Blindzellenfeld。
公开(公告)号：EP0306990A2
公开(公告)日：1989-03-15
申请号：EP88114825.8
申请日：1988-09-09
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Minagawa, Hidenobu , Tatsumi, Yuuichi , Iwahashi, Hiroshi , Asano, Masamichi , Imai, Mizuho
IPC分类号： G11C17/00 , G11C29/00
CPC分类号： G11C29/50012 , G11C16/04 , G11C16/08 , G11C16/28 , G11C16/32 , G11C16/34 , G11C29/24 , G11C29/50 , G11C29/52
摘要： A semiconductor memory device in which data can be read out in response to an address signal comprises power source lines, a plurality of row (WL1 - WLmn) and column conductive lines (COL1 - COLn), a memory cell array (10) including nonvolatile memory cells (M11 - Mmn) arranged in a matrix form of rows and columns and respectively connected to the plurality of row and column lines (COL1 - COLn, WL1 - WLn) and the power source lines, a first selector circuit (5) for generating a signal for selecting the row conductive lines in response to an address signal, a dummy row line (DWL), and dummy memory cells (DM1 - DMn) each having a source, a drain and a control gate connected to the dummy row line (DWL). In the semiconductor memory device, one of paths between the source and the power source line and between the drain and the corresponding row line is closed and the other path is opened, and it further includes a second selector circuit (11) for selectively generating a line selection signal for selecting one of the row conductive lines in response to an address signal and a dummy selection signal for selecting the dummy row line (DWL) in response to the same address signal.
摘要翻译：可以响应于地址信号读出数据的半导体存储器件包括电源线，多个行（WL1-WLmn）和列导线（COL1-COLn），包括非易失性存储单元阵列（10）的存储单元阵列存储单元（M11-Mmn），以行和列的矩阵形式排列并且分别连接到多个行和列线（COL1-COLn，WL1-WLn）和电源线;第一选择器电路（5），用于响应于地址信号，虚拟行线（DWL）和虚拟存储单元（DM1-DMn）产生用于选择行导线的信号，每个具有与虚拟行线连接的源极，漏极和控制栅极（DWL）。在半导体存储器件中，源极与电源线之间以及漏极与对应的行线之间的路径中的一个被封闭，另一个路径被打开，并且还包括第二选择器电路（11），用于选择性地产生行选择信号，用于响应于地址信号选择行导线之一，以及用于响应于相同地址信号选择虚拟行线（DWL）的虚拟选择信号。

10. 发明公开

EP0301588A2 Semiconductor memory device 失效
标题翻译： Halbleiterspeicheranordnung。
公开(公告)号：EP0301588A2
公开(公告)日：1989-02-01
申请号：EP88112373.1
申请日：1988-07-29
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Tatsumi, Yuuichi , Minagawa, Hidenobu , Iwahashi, Hiroshi c/o Patent Division , Asano, Masamichi c/o Patent Division , Imai, Mizuho
IPC分类号： G11C16/06
CPC分类号： G11C16/28
摘要： A semiconductor memory device includes word lines (WL1-Wln) selectively driven by a signal from a row decoder (RD), memory cells (MC11-MCn) connected to word liens (WL1-WLn), first and second data liens (DL1, DL2) , a bit line (BL1) connected to receive data from the memory cell (MC11-MCn1) and to supply received data to the first data liens (DL1), dummy cells (DMC1-DMCn) connected to word lies (WL1-WLn), first and second dummy data liens (DDL1, DDL2), a dummy bit liens (DBL) connected to receive data from the dummy memory cell (DMC1-DMCn) and to supply received data to the first dummy data line (DDL1), a data sensing circuit (2) for generating an output signal corresponding to a potential difference between the second data line (DL2) and second dummy data line (DDL2), a first MOS transistor (T8) connected between the first and second data lines (DL1, DL2), a first load circuit (12) for charging the second data line (DL2), a second MOS transistor (T10) connected between the first and second dummy data liens (DDL1, DDL2), and a second load circuit (11) for charging the second dummy data liens (DDL2). The memory device further includes a first equalizer circuit (21) connected between the second data line (LD2) and dummy data line (DDL2) and equalizing potentials at both ends during a predetermined period of time after the semiconductor memory device is set in the active mode, and a second equalizer circuit (22) connected between the data line (DL1) and dummy data line (DDL1) and equalizing potential as at both ends during a predetermined period of time after the memory device is set in the active mode.
摘要翻译：半导体存储器件包括由来自行解码器（RD）的信号选择性地驱动的字线（WL1-Wln），与字留有意（WL1-WLn）连接的存储单元（MC11-MCn），第一和第二数据留置（DL1， DL2），连接到从存储单元（MC11-MCn1）接收数据并将接收到的数据提供给第一数据留置（DL1）的位线（BL1），连接到单词的虚拟单元（DMC1-DMCn）（WL1- WLN），第一和第二虚拟数据留置（DDL1，DDL2），连接到从虚拟存储单元（DMC1-DMCn）接收数据的虚拟位元数据（DBL），并将接收数据提供给第一虚拟数据线（DDL1），用于产生对应于第二数据线（DL2）和第二虚拟数据线（DDL2）之间的电位差的输出信号的数据感测电路（2），连接在第一和第二数据线之间的第一MOS晶体管（T8）（DL1，DL2），用于对第二数据线（DL2）充电的第一负载电路（12），连接在第一和第二数据线之间的第二MOS晶体管（T10）（DDL1，DDL2）和用于对第二虚拟数据留置（DDL2）充电的第二负载电路（11）。存储装置还包括连接在第二数据线（LD2）和虚拟数据线（DDL2）之间的第一均衡器电路（21），并且在半导体存储器件被设置为激活状态之后的预定时间段期间使两端的电位相等模式，以及连接在数据线（DL1）和虚拟数据线（DDL1）之间的第二均衡器电路（22），并且在存储器件被设置为活动模式之后的预定时间段期间使两端的电位相等。

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