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31. 发明授权

EP1940028B1 Asynchronous interconnection system for 3D inter-chip communication 有权转让
标题翻译：用于3D芯片间通信的异步连接系统
公开(公告)号：EP1940028B1
公开(公告)日：2012-02-29
申请号：EP06027047.7
申请日：2006-12-29
申请人： STMicroelectronics S.r.l.
发明人： Fazzi, Alberto , Guerrieri, Roberto , Magagni, Luca , Ciccarelli, Luca , Canegallo, Roberto
IPC分类号： H03K19/0185 , H03K19/00
CPC分类号： H03K19/018521 , H03K3/356165

32. 发明授权

EP1868292B1 P-domino register with accelerated non-charge path 有权
标题翻译：快速P-多米诺寄存器电路
公开(公告)号：EP1868292B1
公开(公告)日：2008-09-24
申请号：EP06253824.4
申请日：2006-07-20
申请人： VIA Technologies, Inc.
发明人： Qureshi, Imran , Bertram, Raymond A.
IPC分类号： H03K19/096
CPC分类号： H03K19/0963 , H03K3/356165

33. 发明公开

EP1901430A2 High speed level shifter 有权
标题翻译：高速电平转换器
公开(公告)号：EP1901430A2
公开(公告)日：2008-03-19
申请号：EP07114839.9
申请日：2007-08-23
申请人： STMicroelectronics Pvt. Ltd.
发明人： Srivastava, Ankit , Jandial, Sourav
IPC分类号： H03K19/0185
CPC分类号： H03K19/018528 , H03K3/012 , H03K3/356165 , H03K3/356182
摘要： The present invention provides a level shifter circuit capable of high frequency operations. The level shifter circuit utilizes a dynamic charge injection device, which diminishes a capacitive coupling effect between a gate and a drain of input NMOS devices, when the input signal switches from a high logic level to a low logic level. The dynamic charge injection device is incorporated at output nodes to provide initial thrust to the level shifter circuit, which triggers a positive regenerative feedback of cross-coupled pull up PMOS devices enabling a rapid transition and hence the high frequency operations.
摘要翻译：本发明提供了一种能够进行高频操作的电平移位器电路。当输入信号从高逻辑电平切换到低逻辑电平时，电平移位器电路利用动态电荷注入器件，其减小输入NMOS器件的栅极和漏极之间的电容耦合效应。动态电荷注入器件集成在输出节点上，为电平转换器电路提供初始推力，触发交叉耦合上拉PMOS器件的正向再生反馈，从而实现快速转换，从而实现高频操作。

34. 发明公开

EP1868292A1 P-domino register with accelerated non-charge path 有权
标题翻译： Schnelle P-Domino-Registerschaltung
公开(公告)号：EP1868292A1
公开(公告)日：2007-12-19
申请号：EP06253824.4
申请日：2006-07-20
申请人： VIA Technologies, Inc.
发明人： Qureshi, Imran , Bertram, Raymond A.
IPC分类号： H03K19/096
CPC分类号： H03K19/0963 , H03K3/356165
摘要： A P-domino register has a domino stage, a write stage, an inverter, a high keeper path, a low keeper path, and an output stage. The domino stage evaluates a logic function based on at least one input data signal and a pulsed clock signal. The pulsed clock signal lags a symmetric clock signal. The domino stage pre-discharges a pre-discharged node low when the symmetric clock signal is high and opens an evaluation window when the pulsed clock signal goes low, and pulls the pre-discharged node high if it evaluates, and keeps the pre-discharged node low if it fails to evaluate. The output stage provides an output signal based on states of the pre-discharged node and a second preliminary output node.
摘要翻译：多米诺骨牌登记册具有多米诺骨牌阶段，写阶段，逆变器，高守护者路径，低守护者路径和输出阶段。多米诺骨牌阶段基于至少一个输入数据信号和脉冲时钟信号来评估逻辑功能。脉冲时钟信号滞后于对称时钟信号。当对称时钟信号为高电平时，多米诺舞台预放电节点为低电平，当脉冲时钟信号变低时打开评估窗口，如果评估则将预放电节点拉高，并保持预放电节点如果不能评估，则为低。输出级基于预放电节点和第二初步输出节点的状态提供输出信号。

35. 发明授权

EP1184983B1 Interface latch for data level transfer 有权
标题翻译：用于数据传输的接口电平锁定
公开(公告)号：EP1184983B1
公开(公告)日：2007-12-12
申请号：EP00830595.5
申请日：2000-08-31
申请人： STMicroelectronics S.r.l.
发明人： Adduci, Francesco , Bona, Claudio , Fassina, Andrea
IPC分类号： H03K3/356 , H03K17/10 , H03K19/003 , H03K19/007
CPC分类号： H03K3/356113 , H03K3/356165 , H03K17/102 , H03K19/003 , H03K19/007

36. 发明公开

EP0905892A3 RS-Flip-Flop mit Enable-Eingängen 失效
标题翻译： RS触发器与使能输入
公开(公告)号：EP0905892A3
公开(公告)日：2000-12-20
申请号：EP98114223.5
申请日：1998-07-29
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Johnson, Bret , Schneider, Ralf
IPC分类号： H03K3/037
CPC分类号： H03K3/356113 , H03K3/037 , H03K3/356165
摘要： Die Erfindung betrifft ein RS-Flip-Flop mit einem mit einem Eingangsanschluß (IN) verbundenen Inverter (14), einem einen Enable-Set-Anschluß (ENS) aufweisenden NOR-Gatter (15) und einem einen Enable-Reset-Anschluß (ENR) aufweisenden NAND-Gatter (17) und jeweils einem mit dem Inverter (14) verbundenen ersten und zweiten Transistor (12 bzw. 13). Der Ausgang des NOR- bzw. NAND-Gatters (15 bzw. 17) ist über die Gate-Strecke des ersten bzw. zweiten Transistors (12 bzw. 11) an die Gateelektrode von jeweils einem von zwei in Reihe liegenden und ein Halteglied bildenden dritten und vierten Transistoren (16, 18) angeschlossen, deren gemeinsamer Verbindungspunkt mit dem Ausgang des Inverters (14) und dem Ausgangsanschluß (Q) des Flip-Flops zusammengeschaltet ist.

37. 发明公开

EP0961290A3 Flash memory with improved erasability and its circuitry 失效
标题翻译：具有改进的可擦除性和电路的闪存
公开(公告)号：EP0961290A3
公开(公告)日：2000-02-02
申请号：EP99115180.4
申请日：1992-12-09
申请人： FUJITSU LIMITED
发明人： Akaogi, Takao , Kawashima, Hiromi , Takeguchi, Tetsuji , Hagiwara, Ryoji , Kasa, Yasushi , Itano, Kiyoshi , Kawamura, Shouichi , Ogawa, Yasushige
IPC分类号： G11C16/06 , H03K19/21 , G11C5/14
CPC分类号： G11C29/82 , G05F3/205 , G11C5/145 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , H03K3/356147 , H03K3/356165 , H03K19/018521 , H03K19/215
摘要： A substrate voltage control circuit comprises: a negative a negative-voltage source (860) for outputting negative voltage to a power line (V BS ) connected to a component whose voltage is controlled; a first n-channel transistor (867) whose substrate or well and source are connected to the power line (V BS ) and whose drain is connected to a ground power supply Vss; a second n-channel transistor (865) whose substrate or well and source are connected to the power line (V BS ) and whose drain is connected to the gate of the first n-channel transistor (867); a first switch (863) placed between the gate of the first n-channel transistor (867) and a positive power supply (Vcc); a second switch (864) for use in selecting whether the gate of the second n-channel transistor (865) is connected to the positive power supply (Vcc) or ground power supply (Vss), or opened; and a capacitative element (868) connected between the gate and source of the second n-channel transistor (865). When negative voltage is not to be applied, the negative-voltage source (860) is put into a non-output state, the first switch (863) is made, and the second switch (864) is connected to the ground power supply (Vss). When negative voltage is to be applied, the first switch (863) is opened, the second switch (864) is connected to the positive power supply (Vcc), and then the second switch (864) is opened, and the negative-voltage source (V BB ) is put into an output state.
摘要翻译：一种衬底电压控制电路，包括：用于将负电压输出到连接到其电压被控制的部件的电源线（VBS）的负负电压源（860）其衬底或阱和源极连接到电源线（VBS）并且其漏极连接到接地电源Vss的第一n沟道晶体管（867）其衬底或阱和源极连接到电源线（VBS）并且其漏极连接到第一n沟道晶体管（867）的栅极的第二n沟道晶体管（865）; 置于第一n沟道晶体管（867）的栅极和正电源（Vcc）之间的第一开关（863）; 用于选择第二n沟道晶体管（865）的栅极是连接到正电源（Vcc）还是接地电源（Vss）或打开的第二开关（864）; 以及连接在第二n沟道晶体管（865）的栅极和源极之间的电容性元件（868）。当不施加负电压时，使负电压源（860）处于非输出状态，形成第一开关（863），并且将第二开关（864）连接到接地电源（860） VSS）。当施加负电压时，第一开关（863）断开，第二开关（864）连接到正电源（Vcc），然后第二开关（864）断开，并且负电压源（VBB）被置于输出状态。

38. 发明公开

EP0961289A3 Flash memory with improved erasability and its circuitry 失效
标题翻译：闪存具有更好的可擦及其电路
公开(公告)号：EP0961289A3
公开(公告)日：2000-02-02
申请号：EP99115179.6
申请日：1992-12-09
申请人： FUJITSU LIMITED
发明人： Akaogi, Takao , Kawashima, Hiromi , Takeguchi, Tetsuji , Hagiwara, Ryoji , Kasa, Yasushi , Itano, Kiyoshi , Kawamura, Shouichi , Ogawa, Yasushige
IPC分类号： G11C16/06 , H03K19/21 , G11C5/14
CPC分类号： G11C29/82 , G05F3/205 , G11C5/145 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , H03K3/356147 , H03K3/356165 , H03K19/018521 , H03K19/215
摘要： A flash memory which includes a memory cell array (271) in which a plurality of nonvolatile memory cells that can be erased electrically are set in array and decoding units (273) that decode a plurality of signals and access said memory cell array (271), further comprises: drive units (274) each of which includes a first power terminal (275) and a second power terminal (276), inputs the output of the decoding unit (273), and selectively outputs a voltage applied to the first power terminal (275) or a voltage approximate to that voltage, and a voltage applied to the second power terminal or a voltage approximate to that voltage; the drive unit (274) assuming a first operation mode, in which a first voltage is applied to the first power terminal (275) and a second voltage that is lower than the first voltage is applied to the second power terminal (276), and a second operation mode, in which a third voltage is applied to the first power terminal (275) and a fourth voltage that is higher than the third voltage is applied to the second power terminal (276); and selecting an output voltage depending on whether the first or second operation mode is specified.

39. 发明公开

EP0954102A1 Exclusive or/nor circuits 失效
标题翻译： Exklusiv-NOR-Gatter
公开(公告)号：EP0954102A1
公开(公告)日：1999-11-03
申请号：EP99114223.3
申请日：1992-12-09
申请人： FUJITSU LIMITED
发明人： Akaogi, Takao , Kawashima, Hiromi , Takeguchi, Tetsuji , Hagiwara, Ryoji , Kasa, Yasushi , Itano, Kiyoshi , Kawamura, Shouichi , Ogawa, Yasushige
IPC分类号： H03K19/21
CPC分类号： G11C29/82 , G05F3/205 , G11C5/145 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , H03K3/356147 , H03K3/356165 , H03K19/018521 , H03K19/215
摘要： An exclusive OR circuit, for possible use in a flash memory, comprises: a first CMIS inverter (925) in which the source of a first pMIS transistor (921) is connected to a positive-voltage power supply line, the source of a first nMIS transistor (922) is connected to a low-voltage power supply line, the gates of said first pMIS transistor and first nMIS transistor are connected to each other to serve as an input terminal, and the drains of said first pMIS transistor and first nMIS transistor are connected to each other to serve as an output terminal; a second pMIS transistor (924) whose source is connected to said input terminal of said first CMIS inverter and provided with a first input (R); and a second nMIS transistor (923) whose drain is connected to said output terminal of said first CMIS inverter, and whose source is connected to the drain of said second pMIS transistor, and whose gate is connected to the gate of said second pMIS transistor and provided with a second input (S); the exclusive OR (X) of said first and second inputs being output from a contact point between the drain of said second pMIS transistor and the source of said second nMIS transistor.
Such an exclusive OR circuit has fewer circuit elements than previously-proposed circuits and consequently enables the integration of a semiconductor integrated circuit to be improved.
摘要翻译：提供负电压偏置电路，其包括：具有第一和第二端子（550B，550A）的电容器（550）; 第一p沟道MIS场效应晶体管（551），其漏极连接到负电压输出端子（554），其栅极和源极连接到电容器（550）的第一端子（550B）; 和第二p沟道MIS场效应晶体管（552），其漏极连接到栅极连接到负电压输出端子（554）的第一p沟道MIS场效应晶体管（551）的源极，并且其源极具有负电压（VBB）。第一p沟道MIS场效应晶体管（551）是耗尽型p沟道MIS场效应晶体管。在电路的工作中，对一系列时钟脉冲（CLK）的第二端子（550A）的应用导致负电压输出端子（554）的电位趋于负电压（VBB）。

40. 发明公开

EP0570597A4 FLASH MEMORY IMPROVED IN ERASING CHARACTERISTIC, AND CIRCUIT THEREFOR 失效
标题翻译：闪存存储器在擦除特性及其电路中得到改进
公开(公告)号：EP0570597A4
公开(公告)日：1998-11-11
申请号：EP92924898
申请日：1992-12-09
申请人： FUJITSU LTD
发明人： AKAOGI TAKAO , KAWASHIMA HIROMI , TAKEGUCHI TETSUJI , HAGIWARA RYOJI , KASA YASUSHI , ITANO KIYOSHI , OGAWA YASUSHIGE , KAWAMURA SHOUICHI
IPC分类号： G05F3/20 , G11C5/14 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/16 , G11C16/30 , G11C29/00 , H03K3/356 , H03K19/0185 , H03K19/21
CPC分类号： G11C29/82 , G05F3/205 , G11C5/145 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , H03K3/356147 , H03K3/356165 , H03K19/018521 , H03K19/215
摘要： A negative-voltage bias circuit is provided which comprises: a capacitor (550) having first and second terminals (550B, 550A) ; a first p-channel MIS field-effect transistor (551) whose drain is connected to a negative-voltage output terminal (554) and whose gate and source are connected to the first terminal (550B) of the capacitor (550); and a second p-channel MIS field-effect transistor (552) whose drain is connected to the source of the first p-channel MIS field effect transistor (551), whose gate is connected to the negative-voltage output terminal (554), and whose source is provided with a negative voltage (VBB). The first p-channel MIS field-effect transistor (551) is a depletion-type p-channel MIS field-effect transistor. In operation of the circuit, application to the second terminal (550A) of a series of clock pulses (CLK) causes a potential of the negative-voltage output terminal (554) to tend towards the negative voltage (VBB).
摘要翻译：提供负电压偏置电路，其包括：具有第一和第二端子（550B，550A）的电容器（550）; 第一p沟道MIS场效应晶体管（551），其漏极连接到负电压输出端子（554），其栅极和源极连接到电容器（550）的第一端子（550B）; 和第二p沟道MIS场效应晶体管（552），其漏极连接到栅极连接到负电压输出端子（554）的第一p沟道MIS场效应晶体管（551）的源极，并且其源极具有负电压（VBB）。第一p沟道MIS场效应晶体管（551）是耗尽型p沟道MIS场效应晶体管。在电路的工作中，对一系列时钟脉冲（CLK）的第二端子（550A）的应用导致负电压输出端子（554）的电位趋于负电压（VBB）。

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