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1. 发明公开

EP4402801A1 CIRCUIT AND METHOD FOR ADAPTIVELY ELIMINATING RINGING IN SIGNALS DRIVING CAPACITIVE LOADS 审中-实审
公开(公告)号：EP4402801A1
公开(公告)日：2024-07-24
申请号：EP22870541.4
申请日：2022-09-09
申请人： Analog Power Conversion LLC , Kyosan Electric Manufacturing Co., Ltd.
发明人： OCHI, Sam Seiichiro , TAKATA, Tetsuya , YUZURIHARA, Itsuo , YONEYAMA, Tomohiro , HOSOYAMADA, Yu
IPC分类号： H03K5/1252 , H03K3/037 , H03K19/21 , H03K5/00
CPC分类号： H03K19/21 , H03K2005/0001920130101 , H03K5/1252

2. 发明公开

EP4364293A1 ISOLATED GATE DRIVER 审中-实审
公开(公告)号：EP4364293A1
公开(公告)日：2024-05-08
申请号：EP22735582.3
申请日：2022-06-29
申请人： Quantum Power Transformation Limited
发明人： GWYNNE, Robert William
IPC分类号： H03K17/691 , H02M1/08 , H02M1/38 , H03K3/012 , H03K3/037 , H03K5/135
CPC分类号： H03K17/691 , H03K2217/008120130101 , H02M1/08 , Y02B70/10

3. 发明公开

EP4350993A1 COMPARATOR CIRCUIT AND DRIVE CIRCUIT 审中-实审
公开(公告)号：EP4350993A1
公开(公告)日：2024-04-10
申请号：EP22773373.0
申请日：2022-02-16
申请人： JVCKENWOOD Corporation
发明人： ANWAR, Marta Dinata
IPC分类号： H03K3/037 , G09G3/20 , G09G3/36 , H03K5/19
摘要： An object of the present embodiment is to provide a comparator circuit and a driver with a low power consumption.
A comparator circuit according to the present embodiment: including a comparator element configured to output a matching signal indicating whether or not a value of a first input signal matches a value of a second input signal; a flip-flop circuit including a data input terminal to which a constant potential is supplied and a clock input terminal and configured to hold a value of the data input terminal based on a self-clock signal input to the clock input terminal; and a clock generation circuit configured to generate the self-clock signal based on the matching signal.

4. 发明授权

EP3667911B1 SYNCHRONIZER WITH CONTROLLED METASTABILITY CHARACTERISTICS 有权
公开(公告)号：EP3667911B1
公开(公告)日：2023-10-18
申请号：EP19213113.4
申请日：2019-12-03
发明人： SEMENOV, Mikhail Yurievich , MIKHAILOV, Victor Mikhailovich , SOMOV, Sergei Victorovich , MALASHEVICH, Denis Borisovich , KALASHNIKOV, Viacheslav Sergeyevich
IPC分类号： H03K3/037 , H03K3/3562

5. 发明公开

EP4246762A1 MELT BONDING PROTECTION MODULE AND BATTERY SYSTEM COMPRISING SAME 审中-实审
公开(公告)号：EP4246762A1
公开(公告)日：2023-09-20
申请号：EP22867669.8
申请日：2022-09-06
申请人： LG Energy Solution, Ltd.
发明人： KIM, Kihoon , SONG, Changyong
IPC分类号： H02J7/00 , H02H7/18 , H03K3/037 , G01R19/10 , G01R19/00 , G01R19/165
摘要： A fusion bonding protecting module for controlling a negative electrode contactor connected between a negative electrode of a battery pack and a second output end according to fusion and bonding of a positive electrode contactor connected between a positive electrode of the battery pack and a first output end, including: an SR latch including a set terminal for receiving a fusion bonding sensing signal according to whether the positive electrode contactor is fused and bonded and a reset terminal for receiving a comparison signal according to a voltage difference between a first end and a second end of the positive contactor; and an AND gate for generating a compensation control signal by ANDing a logic control signal that is an inverted output of the SR latch and a control signal for controlling the negative electrode contactor.

6. 发明公开

EP4106171A1 MODE DETECTOR FOR DC-DC CONVERTERS 有权
公开(公告)号：EP4106171A1
公开(公告)日：2022-12-21
申请号：EP22178404.4
申请日：2022-06-10
申请人： NXP B.V.
发明人： Büthker, Henricus Cornelis Johannes , Harshey, Jitendra Prabhakar
IPC分类号： H02M3/158 , H02M1/42 , G06F1/26 , G06K19/07 , H03K3/037
摘要： Various embodiments relate to a mode detector configured to determine a mode of a circuit based upon an attached power source, including: a first latch configured to hold an first input value and output the first held value and an inverse of the first held value; a second latch configured to hold a second input value and output the second held value and an inverse of the second held value; a first output switch connected between a first power source line and a power source output of the mode detector, wherein the first output switch is configured to be controlled by the output of the first latch; a second output switch connected between a second power source line and the power source output of the mode detector, wherein the second output switch is configured to be controlled by the output of the second latch; a first AND gate with a first input and a second input connected to the inverse output of the second latch, wherein the first input is configured to receive a first power on reset signal based upon the first power source line; and a second AND gate with a first input and a second input connected to the inverse output of the first latch, wherein the first input is configured to receive a second power on reset signal based upon the second power source line, wherein the mode of the circuit is indicated by the outputs of the first latch and the second latch.

7. 发明授权

EP3001562B1 Fault resistant flip-flop 有权
公开(公告)号：EP3001562B1
公开(公告)日：2021-09-01
申请号：EP14185964.5
申请日：2014-09-23
发明人： Sharma, Vibhu , Malzahn, Ralf
IPC分类号： H03K3/037 , H03K3/3562

8. 发明公开

EP3848934A1 REGISTRE À TRIPLICATION COMPORTANT UN DISPOSITIF DE SÉCURISATION 审中-实审
公开(公告)号：EP3848934A1
公开(公告)日：2021-07-14
申请号：EP20214015.8
申请日：2020-12-15
申请人： THALES
发明人： DERVIN, Patrick , CAUDOUX, Frédéric , MURZEAU, Jean
IPC分类号： G11C29/34 , G11C5/00 , G11C29/00 , G11C29/12 , G11C29/16 , G11C29/24 , G11C29/46 , G11C29/52 , H03K19/23 , G11C29/04 , G11C29/20 , H03K3/037
摘要： L'invention concerne un dispositif à registres dit à triplication comportant un premier registre (REG.1), un second registre (REG.2) et un troisième registre (REG. 3), les trois registres étant identiques et comportant la même information en utilisation courante, un dispositif de vote majoritaire et un dispositif d'autocorrection (BAC), la correction étant fonction du résultat du dispositif de vote majoritaire, chaque registre étant commandé par la sortie d'un multiplexeur (mux) à deux entrées, la première entrée correspondant à une écriture fonctionnelle, la seconde entrée correspondant au résultat du vote majoritaire, caractérisé en ce que le dispositif à triplication comporte un dispositif de test dont la fonction est d'inhiber sur commande et de façon indépendante soit l'écriture fonctionnelle dans le premier registre, soit l'écriture fonctionnelle dans le second registre, soit l'écriture fonctionnelle dans le troisième registre, soit l'autocorrection. Le dispositif de test peut comporter un registre de commande qui peut également être sécurisé par triplication.

9. 发明公开

EP3736981A2 CURRENT-CONTROLLED OSCILLATOR 有权
公开(公告)号：EP3736981A2
公开(公告)日：2020-11-11
申请号：EP20173294.8
申请日：2020-05-06
申请人： NXP USA, Inc.
发明人： Vilas Boas, Andre Luis , Clayton, Felipe Ricardo
IPC分类号： H03K3/037 , H03K3/012 , H03K4/50
摘要： A current-controlled oscillator receives an input current. Ramp voltage generating circuitry generates first and second ramp voltages in response to the input current. Selecting circuitry selects one of the first and second ramp voltages depending on their relative values. Switching circuitry receives a selected ramp voltage, generates a signal based on the selected ramp voltage relative to a reference voltage, and outputs a clock signal. In one embodiment, a comparator receives the reference voltage, one of the first and second ramp voltages, and outputs a comparison signal. Logic circuitry controls the ramp voltage generating circuitry to output one of the ramp voltages during one half of a clock cycle and to output the other ramp voltage during another half cycle of the clock signal based on the comparison signal and logic states of the logic circuitry.

10. 发明公开

EP3729283A1 METHOD OF ACTIVATING A FEATURE OF A CHIP 有权转让
公开(公告)号：EP3729283A1
公开(公告)日：2020-10-28
申请号：EP18811040.7
申请日：2018-12-04
申请人： THALES DIS FRANCE SA
发明人： BERZATI, Alexandre , BONIZEC, Loïc , DOU NASSRE, Alaa
IPC分类号： G06F13/42 , G11C7/00 , H03K3/037 , H03K5/19

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