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    • 22. 发明公开
    • Radio frequency circuit with impedance matching
    • Funkfrequenzschaltung mit Impedanzanpassung
    • EP2461479A1
    • 2012-06-06
    • EP10290632.8
    • 2010-12-01
    • NXP B.V.
    • Andrei, Christian
    • H03F1/56H03F1/26H03F3/195
    • H03F1/565H03F1/26H03F3/195Y10T29/49155
    • A radio frequency (RF) circuit (e.g., 100, 200) is configured for impedance matching, such as for mitigating noise. In connection with an example embodiment, an RF circuit (e.g., 100) includes a transceiver (e.g., 200) in a substrate, and a conductive ring-type of material ( e.g ., 242, 244) in the substrate and around at least a portion of the transceiver circuit. An upper conductive ring material (e.g., 160, 260, 262) is over the substrate and separated from the conductive ring-type material by an insulating layer. The upper conductive ring material is configured to generate an inductance that matches input impedance characteristics of the transceiver circuit. In some implementations, the upper conductive ring material connects a gate input pin (e.g., 605) of the circuit with the gate ( e.g ., 630) of an input transistor of an amplifier in the transceiver, and exhibits an impedance that matches the impedance of the input transistor.
    • 射频(RF)电路(例如,100,200)被配置用于阻抗匹配,例如用于减轻噪声。 结合示例性实施例,RF电路(例如,100)在衬底中包括收发器(例如,200)以及衬底中的导电环型材料(例如,242,244),并且至少围绕 收发电路的一部分。 上导电环材料(例如,160,260,262)在衬底之上并且通过绝缘层与导电环型材料分离。 上导电环材料被配置为产生匹配收发器电路的输入阻抗特性的电感。 在一些实现中,上导电环材料将电路的栅极输入引脚(例如,605)与收发器中的放大器的输入晶体管的栅极(例如,630)连接,并且具有与阻抗匹配的阻抗 的输入晶体管。
    • 25. 发明公开
    • Low-noise high efficiency bias generation circuits and method
    • 低噪声高效率偏置发生电路和方法
    • EP2346169A2
    • 2011-07-20
    • EP11154275.9
    • 2009-07-17
    • PEREGRINE SEMICONDUCTOR CORPORATION
    • Kim, Tae YounEnglekirk, Robert MarkKelly, Dylan J.
    • H03K17/00
    • H03F1/26H02M3/07H03F3/45183H03F3/45237H03F3/45475H03F3/45659H03F2200/453H03F2200/456H03F2200/474H03F2203/45138H03F2203/45188H03F2203/45366H03F2203/45418H03F2203/45424H03F2203/45471H03F2203/45642H03H11/245H03K17/145
    • A bias generation method or apparatus defined by any one or any practical combination of numerous features that contribute to low noise and/or high efficiency biasing, including: having a charge pump control clock output with a waveform having limited harmonic content or distortion compared to a sine wave; having a ring oscillator to generating a charge pump clock that includes inverters current limited by cascode devices and achieves substantially rail-to-rail output amplitude; having a differential ring oscillator with optional startup and/or phase locking features to produce two phase outputs suitably matched and in adequate phase opposition; having a ring oscillator of less than five stages generating a charge pump clock; capacitively coupling the clock output(s) to some or all of the charge transfer capacitor switches; biasing an FET, which is capacitively coupled to a drive signal, to a bias voltage via an "active bias resistor" circuit that conducts between output terminals only during portions of a waveform appearing between the terminals, and/or wherein the bias voltage is generated by switching a small capacitance at cycles of said waveform. A threshold voltage bias voltage generation circuit may A charge pump for the bias generation may include a regulating feedback loop including an OTA that is also suitable for other uses, the OTA having a ratio-control input that controls a current mirror ratio in a differential amplifier over a continuous range, and optionally has differential outputs including an inverting output produced by a second differential amplifier that optionally includes a variable ratio current mirror controlled by the same ratio-control input. The ratio-control input may therefore control a common mode voltage of the differential outputs of the OTA. A control loop around the OTA may be configured to control the ratio of one or more variable ratio current mirrors, which may particularly control the output common mode voltage, and may control it such that the inverting output level tracks the non-inverting output level to cause the amplifier to function as a high-gain integrator.
    • 由有助于低噪声和/或高效率偏置的众多特征中的任何一个或任何实际组合定义的偏置生成方法或装置包括:具有电荷泵控制时钟输出,其具有与具有有限谐波含量或失真的波形相比 正弦波; 具有用于产生电荷泵时钟的环形振荡器,所述电荷泵时钟包括由共源共栅器件限制的电流的逆变器并且实质上实现轨到轨输出幅度; 具有差分环形振荡器,其具有可选的启动和/或锁相特征以产生适当匹配且处于适当反相的两相输出; 具有产生电荷泵时钟的小于五级的环形振荡器; 将时钟输出电容耦合到一些或全部电荷转移电容器开关; 和/或其中产生偏置电压的偏置电压经由仅在出现在端子之间的波形的部分期间在输出端子之间导通的“有源偏置电阻器”电路来偏置与驱动信号电容耦合的FET到偏置电压 通过在所述波形的周期切换小电容。 阈值电压偏置电压产生电路可以用于偏置产生的电荷泵可以包括调节反馈环路,该调节反馈环路包括也适用于其他用途的OTA,该OTA具有比率控制输入,该比例控制输入控制差分放大器中的电流镜像比 并且可选地具有包括由第二差分放大器产生的反相输出的差分输出,所述第二差分放大器可选地包括由相同比率控制输入控制的可变比率电流镜。 比率控制输入因此可以控制OTA的差分输出的共模电压。 围绕OTA的控制回路可以被配置为控制一个或多个可变比率电流镜的比率,其可以特别地控制输出共模电压,并且可以控制它以使得反相输出电平跟踪非反相输出电平到 使放大器起到高增益积分器的作用。
    • 26. 发明授权
    • POWER AMPLIFIER
    • 功率放大器
    • EP1447908B1
    • 2011-03-16
    • EP02775506.5
    • 2002-11-07
    • Sony Corporation
    • MASUDA, Toshihiko c/o SONY CORPORATIONOHKURI, Kazunobu c/o SONY CORPORATION
    • H03F3/217
    • H03F1/26H03F3/217H03F3/2173H03F3/3027H03F2200/331
    • A power amplifier for reducing radiation arising from the edge of an output voltage. The amplifier is provided with a pair of PWM modulation circuits (11, 12) to be supplied with an input signal, a pair of push-pull circuits (15, 16),and drive circuits (13, 14) which supply the output of the PWM modulation circuits (11, 12) as a drive signal to the push-pull circuits (15, 16). A loudspeaker (19) is connected between the output end of the push-pull circuit (15) and the output end of the push-pull circuit (16). The drive circuits (13, 14) are switched every cycle of a pulse modulation signal so that the drive signal to be supplied to the push-pull circuits (15, 16) may not change to a break point of every cycle of the pulse modulation signal.
    • 一种功率放大器,用于减少由输出电压边缘引起的辐射。 该放大器具备供给输入信号的一对PWM调制电路(11,12),一对推挽电路(15,16)和驱动电路(13,14),该一对推挽电路 PWM调制电路(11,12)作为推挽电路(15,16)的驱动信号。 扬声器(19)连接在推挽电路(15)的输出端和推挽电路(16)的输出端之间。 驱动电路(13,14)在脉冲调制信号的每个周期被切换,使得要提供给推挽电路(15,16)的驱动信号可以不改变为脉冲调制的每个周期的中断点 信号。