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    • 8. 发明公开
    • SRPP circuit having wide frequency range
    • 绅士绅士
    • EP0963038A3
    • 2000-05-17
    • EP99304108.6
    • 1999-05-26
    • SONY CORPORATION
    • Okanobu, Taiwa
    • H03F3/26H02M3/337G05F1/59G05F3/22H02M3/158
    • H03F3/3084H03F3/50
    • In an SRPP circuit, a transistor Q11 has a collector connected to a power supply terminal T13 through a resistor R11 and an emitter connected to the collector of a transistor Q12 having the same polarity as that of the transistor Q11. The emitter of the transistor Q12 is connected to the ground. The collector of the transistor Q11 is connected to the emitter of a transistor Q13 having the polarity opposite to that of the transistor Q11, and the collector of the transistor Q13 is connected to the base of the transistor Q12. A bias voltage V13 is applied to the base of the transistor Q13. An input signal Vin is supplied to the base of the transistor Q11 to extract an output signal from a node between the emitter of the transistor Q11 and the collector of the transistor Q12.
    • 在SRPP电路中,晶体管Q11具有通过电阻R11连接到电源端子T13的集电极和与晶体管Q12的集电极连接的发射极,其具有与晶体管Q11的极性相同的极性。 晶体管Q12的发射极连接到地。 晶体管Q11的集电极连接到具有与晶体管Q11的极性相反极性的晶体管Q13的发射极,并且晶体管Q13的集电极连接到晶体管Q12的基极。 偏置电压V13施加到晶体管Q13的基极。 输入信号Vin被提供给晶体管Q11的基极,以从晶体管Q11的发射极和晶体管Q12的集电极之间的节点提取输出信号。
    • 9. 发明公开
    • Fast buffer
    • 快速缓冲区
    • EP0841746A3
    • 1998-05-20
    • EP98102648.7
    • 1992-06-11
    • SGS-THOMSON MICROELECTRONICS, INC.
    • Bien, David Edward
    • H03F3/50H03F3/30
    • H03F3/505H03F3/3076H03F3/50
    • There is disclosed a buffer circuit, comprising an FET input amplifier connected to receive an input signal and to produce an output signal representing said input signal, an output amplifier, comprising an FET and a bipolar transistor, connected to receive said output signal from said input amplifier and to develop a circuit output signal, a differential amplifier comprising FET transistors connected to produce an output related to the difference between the input and output signals, and to apply the difference to the base of said bipolar transistor.
    • 公开了一种缓冲器电路,包括被连接以接收输入信号并产生表示所述输入信号的输出信号的FET输入放大器,包括FET和双极晶体管的输出放大器,被连接以从所述输入端接收所述输出信号 放大器并且产生电路输出信号;包括FET晶体管的差分放大器,被连接以产生与输入和输出信号之间的差有关的输出,并且将该差施加到所述双极晶体管的基极。
    • 10. 发明公开
    • Analog to digital converter
    • 模数转换器
    • EP0795963A3
    • 1997-10-22
    • EP97109122.8
    • 1994-06-09
    • SONY CORPORATION
    • Gendai, Yuji
    • H03M1/36
    • H03K19/0016H03F3/50H03F3/72H03M1/365
    • The present invention relates to an analog to digital converter, comprising: a reference voltage generation circuit (143) for generating a plurality of reference voltages having different voltage values, and a plurality of comparators (COP1d - COP255d) each including a first emitter follower stage (131) to which an analog input signal is supplied, a second emitter follower stage (132) to which one of the plurality of reference voltages is supplied, and a differential amplifier (133) for amplifying a difference between outputs of said first and second emitter follower stages (131; 132). Output terminals of the first emitter follower stages (131) are connected common between said plurality of comparators (133), and output terminals of the second emitter follower stages (132) are connected common between each adjacent ones of said plurality of comparators by way of a resistor (R152).
    • 本发明涉及一种模数转换器,包括:用于产生具有不同电压值的多个参考电压的参考电压产生电路(143),以及多个比较器(COP1d-COP255d),每个比较器包括第一射极跟随器级 (131),提供有模拟输入信号;第二射极跟随器级(132),所述多个参考电压中的一个被提供到所述第二射极跟随器级(132);以及差分放大器(133),用于放大所述第一和第二 射极跟随器级(131; 132)。 第一射极跟随器级(131)的输出端共同连接在所述多个比较器(133)之间,并且第二射极跟随器级(132)的输出端在所述多个比较器的每一个相邻的比较器之间通过公共连接 一个电阻(R152)。