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21. 发明公开

EP0540578A1 COMPACT SRAM CELL LAYOUT 失效
标题翻译： SRAM单元布局紧凑。
公开(公告)号：EP0540578A1
公开(公告)日：1993-05-12
申请号：EP91913226.0
申请日：1991-07-12
申请人： PARADIGM TECHNOLOGY, INC.
发明人： GODINHO, Norman , LEE, Frank, Tsu-Wei , CHEN, Hsiang-Wen , MOTTA, Richard, F. , TSANG, Juine-Kai , TZOU, Joseph , BAIK, Jai-Man , YEN, Ting-Pwu
IPC分类号： H01L21 , H01L23 , H01L27
CPC分类号： H01L27/11 , H01L21/768 , H01L21/76895 , H01L21/76897 , H01L21/823864 , H01L21/823871 , H01L23/53257 , H01L23/53271 , H01L27/1104 , H01L27/1112 , H01L2924/0002 , Y10S257/904 , H01L2924/00
摘要： On a élaboré une structure de cellule mémoire compacte pour cellule mémoire à accès sélectif statique. La cellule possède deux transistors ayant des portes (30a, 30b) qui sont pratiquement parallèles l'une par rapport à l'autre. Une première interconnexion (45) connecte la porte (30b) d'un premier transistor à une électrode (35a) du second transistor. Une seconde interconnexion (46) connecte la porte (30a) du second transistor à une électrode (35b) du premier transistor. Les deux portes et les deux interconnexions forment pratiquement un rectangle. Une ligne (47) de circuit d'alimentation en courant est placée à l'extérieur du rectangle. Cette ligne et les deux interconnexions sont formées à partir d'une couche conductrice. En outre, dans un réseau de cellules mémoires, certaines lignes (37) de circuit sont formées dans le substrat, et d'autres lignes (47) de circuit sont formées directement au-dessus desdites lignes (37) formées dans le substrat. Les lignes (37) formées dans le substrat sont pourvues de prolongements (42a, 42b) qui permettant le contact desdites lignes (37) sans qu'il y ait contact avec les autres lignes (47) situées au-dessus.

22. 发明公开

EP0471310A1 MOS-type semiconductor integrated circuit device 失效
标题翻译： Integriertes Halbleiter-Schaltkreisbauelement vom MOS-Typ。
公开(公告)号：EP0471310A1
公开(公告)日：1992-02-19
申请号：EP91113424.5
申请日：1991-08-09
申请人： NEC CORPORATION
发明人： Ooka, Hideyuki, c/o NEC Corporation
IPC分类号： H01L27/088 , H01L27/02 , H01L21/90
CPC分类号： H01L27/0266 , H01L23/53257 , H01L27/088 , H01L29/41725 , H01L29/456 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： In the semiconductor integrated circuit device of the present invention which uses MOSFETs as its components, the gate electrode of the MOSFET is constructed by using a silicide gate, a polycide gate or a metal gate. The source-drain region of the MOSFET for the internal circuit which does not require connection to an external circuit has the salicide structure, and the source-drain region of the MOSFET for the buffet circuit which requires a direct connection to an external device has a region which is not of salicide structure at least in a portion adjacent to the gate electrode. The gate electrode and the source-drain region of the internal circuit become to have low resistances so that it is possible to realize an increase in the operating speed by using them as a part of the wirings. Further, in the source-drain region of the buffer circuit there is provided a region of high resistance in the vicinity of the gate electrode so that it is possible to enhance the ESD resistance.
摘要翻译：在使用MOSFET作为其元件的本发明的半导体集成电路器件中，MOSFET的栅极通过使用硅化物栅，多晶硅栅极或金属栅极构成。用于不需要连接到外部电路的用于内部电路的MOSFET的源极 - 漏极区域具有自对准结构，并且需要直接连接到外部器件的用于自助电路的MOSFET的源极 - 漏极区域具有至少在与栅电极相邻的部分中不具有自对准硅结构的区域。内部电路的栅电极和源极 - 漏极区域变得具有低电阻，从而可以通过使用它们作为布线的一部分来实现操作速度的增加。此外，在缓冲电路的源极 - 漏极区域中，在栅电极附近提供高电阻的区域，从而可以提高ESD电阻。

23. 发明公开

EP0343667A3 Contact structure for connecting electrode to a semiconductor device and a method of forming the same 失效
标题翻译：用于将电极连接到半导体器件的接触结构及其形成方法
公开(公告)号：EP0343667A3
公开(公告)日：1991-04-17
申请号：EP89109461.7
申请日：1989-05-26
申请人： FUJITSU LIMITED
发明人： Nishida, Kenji , Sato, Noriaki
IPC分类号： H01L23/48 , H01L21/60 , H01L21/283
CPC分类号： H01L21/76897 , H01L21/28518 , H01L23/485 , H01L23/53257 , H01L29/665 , H01L2924/0002 , Y10S148/019 , H01L2924/00
摘要： A contact structure for connecting a semiconductor device to a wiring electrode comprises a semiconductor layer (11) forming a part of the semiconductor device, a first contact layer (17a) of reduced resistivity for covering a surface of the semiconductor layer, an insulating structure (18, 19) provided on the first contact layer so as to bury the first contact layer underneath, a penetrating hole (20) opened through the insulating structure so as to expose a part of the first contact layer, a second contact layer (17b) of reduced resistivity provided on the part of the first contact layer exposed by the penetrating hole, in which the second contact layer extends from a bottom of the penetrating hole along its side wall, and a conductor layer (22) forming the wiring electrode provided on the second contact layer.
摘要翻译：用于将半导体器件连接到布线电极的接触结构包括形成半导体器件的一部分的半导体层（11），用于覆盖半导体层的表面的电阻率降低的第一接触层（17a），绝缘结构 18，19）设置在第一接触层上，以便在其下方埋设第一接触层，穿过绝缘结构开放的穿透孔（20）以露出第一接触层的一部分，第二接触层（17b）所述第一接触层暴露在所述第一接触层的部分上的所述第一接触层的第二接触层沿着其侧壁从所述穿透孔的底部延伸，并且形成所述布线电极的导体层，第二接触层。

24. 发明公开

EP0347792A3 Multi-layer wirings on a semiconductor device and fabrication method 失效
标题翻译：半导体器件和制造方法上的多层布线
公开(公告)号：EP0347792A3
公开(公告)日：1990-12-05
申请号：EP89111073.6
申请日：1989-06-19
申请人： FUJITSU LIMITED
发明人： Takagi, Hideo , Suzuki, Noriyuki
IPC分类号： H01L21/90 , H01L23/52
CPC分类号： H01L21/32134 , H01L21/31111 , H01L21/76802 , H01L21/76838 , H01L23/5226 , H01L23/53257 , H01L23/53271 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , Y10T428/24917 , H01L2924/00
摘要： A first layer-wiring (6) formed of a material soluble in a solution containing hydrofluoric acid (HF) is protected in an insulating layer. A second layer-wiring (7) insulatingly overlying the first layer is connected with the first layer-wiring via a third layer-wiring (13) which is resistant to a solution containing HF. When contact holes (8-12) are opened through the insulating layer so as to lead out the first layer-wiring (6) and/or a part of the semiconductor substrate, the first layer-wiring (6) is not exposed to HF containing solution for cleaning the exposed materials in the opened holes. Accordingly, a material having small electrical conductivity but soluble by the HF can be employed for the layer-wiring allowing a high density integration as well good electrical contact with the Si substrate and with other multi-layer wirings.

25. 发明授权

EP0100454B1 Semiconductor device having a conductive layer consisting of a high-melting point metal silicide and a method for manufacturing such a semiconductor device 失效
标题翻译：具有高熔点金属硅化物的导电层的半导体器件和用于制造这种半导体器件的方法
公开(公告)号：EP0100454B1
公开(公告)日：1987-09-30
申请号：EP83106554.5
申请日：1983-07-05
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Okumura, Katsuya , Kawaguchi, Tatsuzo
IPC分类号： H01L23/52 , H01L29/40
CPC分类号： H01L29/4975 , H01L23/53257 , H01L29/78 , H01L2924/0002 , H01L2924/00

26. 发明公开

EP0077813A1 LOW RESISTIVITY COMPOSITE METALLIZATION FOR SEMICONDUCTOR DEVICES AND METHOD THEREFOR 无效
标题翻译： MEHRSCHICHTENMETALLISIERUNG低比电阻适用于半导体布置和方法。
公开(公告)号：EP0077813A1
公开(公告)日：1983-05-04
申请号：EP82901672.0
申请日：1982-04-15
申请人： MOTOROLA, INC.
发明人： ASPIN, Carlton H. , LO, Wei Jen
IPC分类号： H01L21 , H01L23 , H01L29
CPC分类号： H01L29/66575 , H01L21/0272 , H01L23/485 , H01L23/53257 , H01L29/4933 , H01L2924/0002 , H01L2924/00
摘要： Une resistance en serie de faible contact et a metallisation d'interconnexion sur des dispositifs semiconducteurs est obtenue tout en eliminant les problemes d'incompatibilite de materiaux et de procedes de l'art anterieur en utilisant une structure de metallisation composite (42, 44, 49) ayant deux couches intermetalliques superposees (44, 49) ayant des proprietes differentes. La premiere couche intermetallique (44) est choisie pour sa haute conductivite et sa compatibilite avec les interfaces des dispositifs. La seconde intermetallique (49) joue le role 'de chapeau' protecteur conducteur et est choisie pour sa conductivite et sa compatibilite avec les etapes ulterieures du procede. Les deux couches intermetalliques (44, 49) doivent egalement etre compatibles. Pour des dispositifs au silicium, la premiere et la seconde couches intermetalliques preferentielles sont, respectivement, du siliciure de titane riche en silicium et du nitrure de titane, mais d'autres materiaux peuvent egalement etre utilises. Du silicium polycristallin (42) est souhaitable pour une couche de base sous la premiere couche intermetallique (44) dans certaines structures de dispositifs telles que des portes MOS. La metallisation composite est preparee par une technique de decollage.

27. 发明公开

EP3361503A1 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：EP3361503A1
公开(公告)日：2018-08-15
申请号：EP17206886.8
申请日：2017-12-13
申请人： Renesas Electronics Corporation
发明人： Toshifumi, SUGANAGA
IPC分类号： H01L23/522
CPC分类号： H01L21/76804 , H01L21/76816 , H01L21/76829 , H01L21/76877 , H01L23/5226 , H01L23/5283 , H01L23/53228 , H01L23/53257 , H01L23/535 , H01L2224/05
摘要： An object of the present invention is to improve the operating characteristics of a semiconductor device.
A semiconductor device has a contact plug that is formed over a semiconductor substrate, a metal wiring that is coupled to the upper surface of the contact plug, and a slit that is formed in the metal wiring. Further, the contact plug is formed at an end of the metal wiring, and the slit is formed at a position apart from the contact plug in an X direction in a planar view. A distance between an edge of the upper surface at the end of the metal wiring and the upper surface of the slit in the X direction is equal to or larger than and twice or smaller than a first plug diameter of the upper surface of the contact plug in the X direction.

28. 发明公开

EP3279932A1 A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 审中-公开
标题翻译：一种半导体器件及其制造方法
公开(公告)号：EP3279932A1
公开(公告)日：2018-02-07
申请号：EP17184174.5
申请日：2017-08-01
申请人： Semiconductor Manufacturing International Corporation (Beijing) , Semiconductor Manufacturing International Corporation (Shanghai)
发明人： PENG, Shimin
IPC分类号： H01L21/768
CPC分类号： H01L21/76816 , H01L21/76804 , H01L21/76805 , H01L21/76814 , H01L21/76826 , H01L21/7684 , H01L21/76877 , H01L21/76895 , H01L23/528 , H01L23/53257 , H01L23/53295 , H01L23/535 , H01L2221/1063
摘要： A semiconductor device and its manufacturing method are presented. The manufacturing method entails: forming a dielectric layer on a semiconductor substrate; forming a functional layer on the dielectric layer; forming a hard mask layer on the functional layer; patterning the semiconductor substrate to form an opening on the semiconductor substrate, wherein the opening goes through the hard mask layer, the functional layer and extends into the dielectric layer; performing an oxidization process on side surfaces of the functional layer inside the opening to form oxide layers; performing a first process on the semiconductor substrate to remove a portion of the dielectric layer underneath the opening to expose the semiconductor substrate; and removing the oxide layers on the side surfaces of the functional layer to form a contact hole. The contact hole has a wider opening in the upper part than in the lower part.
摘要翻译：介绍了一种半导体器件及其制造方法。该制造方法需要：在半导体衬底上形成电介质层; 在介电层上形成功能层; 在功能层上形成硬掩模层; 图案化所述半导体衬底以在所述半导体衬底上形成开口，其中所述开口穿过所述硬掩模层，所述功能层并且延伸到所述电介质层中; 在开口内部的功能层的侧表面上执行氧化工艺以形成氧化物层; 在所述半导体衬底上执行第一工艺以去除所述开口下方的所述电介质层的一部分以暴露所述半导体衬底; 去除功能层侧面的氧化层形成接触孔。接触孔在上部具有比下部更宽的开口。

29. 发明公开

EP3155650A1 SEAM HEALING OF METAL INTERCONNECTS 审中-公开
标题翻译： NAHTHEILUNG VON METALLVERBINDUNGEN
公开(公告)号：EP3155650A1
公开(公告)日：2017-04-19
申请号：EP14894934.0
申请日：2014-06-16
申请人： Intel Corporation
发明人： CHEBIAM, Ramanan V. , JEZEWSKI, Christopher J. , INDUKURI, Tejaswi K. , CLARKE, James S. , PLOMBON, John J.
IPC分类号： H01L21/20 , H01L21/31 , H01L21/28
CPC分类号： H01L23/5226 , H01L21/321 , H01L21/76807 , H01L21/76838 , H01L21/76882 , H01L21/76883 , H01L23/53209 , H01L23/53242 , H01L23/53257 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the present disclosure describe removing seams and voids in metal interconnects and associated techniques and configurations. In one embodiment, a method includes conformally depositing a metal into a recess disposed in a dielectric material to form an interconnect, wherein conformally depositing the metal creates a seam or void in the deposited metal within or directly adjacent to the recess and heating the metal in the presence of a reactive gas to remove the seam or void, wherein the metal has a melting point that is greater than a melting point of copper. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述了去除金属互连中的接缝和空隙以及相关技术和配置。在一个实施例中，一种方法包括将金属共形沉积到设置在电介质材料中的凹槽中以形成互连，其中共形沉积金属在沉积的金属中在凹陷内或直接邻近凹部产生接缝或空隙，并将金属加热存在反应气体以除去接缝或空隙，其中金属具有大于铜的熔点的熔点。可以描述和/或要求保护其他实施例。

30. 发明公开

EP2951862A4 NON-VOLATILE MEMORY WITH SILICIDED BIT LINE CONTACTS 审中-公开
标题翻译： NICHTFLÜCHTIGERSPEICHER MIT SILIZITENTEN BITLEITUNGSKONTAKTEN
公开(公告)号：EP2951862A4
公开(公告)日：2017-03-15
申请号：EP14745500
申请日：2014-01-30
申请人： CYPRESS SEMICONDUCTOR CORP
发明人： LU CHING-HUANG , CHAN SIMON SIU-SING , SHIRAIWA HIDEHIKO , XUE LEI
IPC分类号： H01L21/28 , H01L27/11568 , H01L29/423 , H01L29/66 , H01L29/792
CPC分类号： H01L27/11568 , H01L21/0214 , H01L21/02164 , H01L21/0228 , H01L21/265 , H01L21/26513 , H01L21/28282 , H01L21/32053 , H01L23/528 , H01L23/53209 , H01L23/53257 , H01L29/4234 , H01L29/513 , H01L29/518 , H01L29/6653 , H01L29/66553 , H01L29/66833 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.
摘要翻译：使用与存储器件中的底层衬底不相干的硅化位线触点的方法。该方法提供了在位线接触区域中形成硅化物的方法，该工艺利用了与氧化物 - 氮化物 - 氧化物（ONO）氮化物边缘自对准的优点。该方法的另一个优点是可以消除位线接触注入和快速温度退火工艺。这种方法适用于嵌入式闪存，集成高密度设备和高级逻辑过程。

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