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1. 发明公开

EP0437307A3 High resistance polysilicon load resistor 失效
标题翻译：高电阻多晶硅负载电阻
公开(公告)号：EP0437307A3
公开(公告)日：1991-10-30
申请号：EP91300026.1
申请日：1991-01-02
申请人： PARADIGM TECHNOLOGY, INC.
发明人： Godinho, Norman , Lee, Frank Tsu-Wei , Chen, Hsiang-Wen , Motta, Richard F. , Tsang, Juine-Kai , Tzou, Joseph , Baik, Jai-Man , Yen, Ting-Pwu
IPC分类号： H01L27/11 , H01L21/82 , H01L21/3205
CPC分类号： H01L21/82 , H01L27/1112 , H01L2924/0002 , Y10S257/915 , H01L2924/00
摘要： A load resistor for use in a semiconductor integrated circuit consists of two portions of conductive material, typically strips of either a silicide or a composite polycrystalline silicon layer and silicide layer formed thereon, formed on a semiconductor substrate and separated from each other by a selected distance. An electrically conductive dopant diffusion barrier is formed on the first and second portions of conductive material. A polycrystalline silicon material is then placed on the structure such that one portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the first portion of conductive material and the other portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the second portion of conductive material. Typically the polycrystalline silicon material is placed on an insulation layer formed on the semiconductor substrate in the portion of the substrate between the two portions of conductive material. The diffusion barrier prevents any dopant from the conductive material from diffusing into the polycrystalline silicon material thereby allowing the polycrystalline silicon material to function as a load resistor having a high resistance in the giga-ohms range. Subsequent high temperature processing of the structure does not change the resistance of the polycrystalline silicon because the dopant diffusion barrier prevents any dopant from the underlying conductive material from diffusing into the polycrystalline silicon material.

2. 发明公开

EP0672299A1 TRANSISTOR FABRICATION METHODS AND METHODS OF FORMING MULTIPLE LAYERS OF PHOTORESIST 失效
标题翻译：用于生产的晶体管和方法的形成多层PHOTO涂料。
公开(公告)号：EP0672299A1
公开(公告)日：1995-09-20
申请号：EP94901678.0
申请日：1993-11-30
申请人： PARADIGM TECHNOLOGY, INC.
发明人： YEN, Ting-Pwu , CHEN, Hsiang-Wen
IPC分类号： H01L21 , H01L27 , H01L29
CPC分类号： H01L29/66765 , H01L27/11 , H01L27/1108 , H01L29/78621 , H01L29/78624
摘要： Transistor fabrication methods are provided for transistors with current carrying elements above a semiconductor substrate. Only few mask alignments define critical dimensions such as the channel length of a MOS transistor. In one embodiment, where the channel region (154) overlies the gate (110), a first mask (126) is formed over the channel region (154), and an LDD implant is carried out. A second mask (158) is formed over the LDD portion of the drain region (150). The second mask (158) is allowed to extend over the first mask (126). A heavy doping implant is carried out. An LDD structure is provided on the drain but not on the source side with only the first mask (126) defining the channel length (134). In some embodiments, both masks include photoresist. The first photoresist mask (126) is hardened to prevent its lifting during development of the resist of the second mask (158).

3. 发明公开

EP0437306A2 Self-aligning contact and interconnect structure 失效
标题翻译： Selbstjustierender Kontakt und Verbindungsstrukturen。
公开(公告)号：EP0437306A2
公开(公告)日：1991-07-17
申请号：EP91300024.6
申请日：1991-01-02
申请人： PARADIGM TECHNOLOGY, INC.
发明人： Godinho, Norman , Lee, Frank Tsu-Wei , Chen, Hsiang-Wen , Motta, Richard F. , Tsang, Juine-Kai , Tzou, Joseph , Baik, Jai-Man , Yen, Ting-Pwu
IPC分类号： H01L21/60 , H01L21/3205 , H01L21/90 , H01L23/485
CPC分类号： H01L21/76897 , H01L21/76895 , H01L21/823864 , H01L21/823871 , H01L23/53257 , H01L23/53271 , H01L27/11 , H01L27/1104 , H01L2924/0002 , H01L2924/00
摘要： An MOS transistor for use in an integrated circuit, particularly CMOS integrated circuits, is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density.
Self-aligning source and drain contacts overlap the gate but are prevented from a short circuiting to the gate by oxide insulation between the source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of titanium silicide encapulated by a thin film of titanium nitride.
摘要翻译：用于集成电路的MOS晶体管，特别是CMOS集成电路，其制造具有允许更高封装密度的自对准接触和互连结构。自对准源极和漏极触点与栅极重叠，但是通过源极/漏极接触和栅极之间的氧化物绝缘以及栅极上方的氮化硅层来防止与栅极的短路。在晶体管的有源区域上在栅极的顶部形成与栅极的触点，因为源极和漏极区域在蚀刻绝缘体以暴露栅极触点期间被硬化的光致抗蚀剂层保护。源极，漏极和栅极触点由一层硅化钛保护，使得互连不需要完全覆盖这些区域。低电阻互连由氮化钛薄膜包围的硅化钛形成。

4. 发明公开

EP0540578A4 COMPACT SRAM CELL LAYOUT 失效
标题翻译：紧凑型SRAM单元布局
公开(公告)号：EP0540578A4
公开(公告)日：1995-07-05
申请号：EP91913226
申请日：1991-07-12
申请人： PARADIGM TECHNOLOGY INC
发明人： GODINHO NORMAN , LEE FRANK TSU-WEI , CHEN HSIANG-WEN , MOTTA RICHARD F , TSANG JUINE-KAI , TZOU JOSEPH , BAIK JAI-MAN , YEN TING-PWU
IPC分类号： H01L21/60 , H01L21/768 , H01L21/8238 , H01L21/8244 , H01L23/532 , H01L27/11 , H01L27/02 , G11C11/00
CPC分类号： H01L27/11 , H01L21/768 , H01L21/76895 , H01L21/76897 , H01L21/823864 , H01L21/823871 , H01L23/53257 , H01L23/53271 , H01L27/1104 , H01L27/1112 , H01L2924/0002 , Y10S257/904 , H01L2924/00
摘要： A compact cell design for a static random access memory cell is achieved. The cell has two transistors with gates (30a, 30b) substantially parallel to each other. One interconnect (45) connects the gate (30b) of one transistor to an electrode (35a) of the other transistor. Another interconnect (46) connects the gate (30a) of the other transistor to an electrode (35b) of the first transistor. The two gates and the two interconnects form substantially a rectangle. A power supply circuit line (47) is disposed outside the rectangle. This line and the two interconnects are formed from one conductive layer. Also, in an array of memory cells, some circuit lines (37) are formed in the substrate, and other circuit lines (47) are formed directly above those in-the-substrate lines (37). The in-the-substrate lines (37) are provided with extensions (42a, 42b) that permit to contact these lines (37) without contacting the other, overlying lines (47).
摘要翻译：实现了用于静态随机存取存储器单元的紧凑型单元设计。电池具有两个晶体管，栅极基本上彼此平行。一个互连将一个晶体管的栅极连接到另一个晶体管的电极。另一个互连将另一晶体管的栅极连接到第一晶体管的电极。两个门和两个互连形成大致矩形。电源线环绕在矩形外面。该线和两个互连由一个导电层形成。

5. 发明公开

EP0540578A1 COMPACT SRAM CELL LAYOUT 失效
标题翻译： SRAM单元布局紧凑。
公开(公告)号：EP0540578A1
公开(公告)日：1993-05-12
申请号：EP91913226.0
申请日：1991-07-12
申请人： PARADIGM TECHNOLOGY, INC.
发明人： GODINHO, Norman , LEE, Frank, Tsu-Wei , CHEN, Hsiang-Wen , MOTTA, Richard, F. , TSANG, Juine-Kai , TZOU, Joseph , BAIK, Jai-Man , YEN, Ting-Pwu
IPC分类号： H01L21 , H01L23 , H01L27
CPC分类号： H01L27/11 , H01L21/768 , H01L21/76895 , H01L21/76897 , H01L21/823864 , H01L21/823871 , H01L23/53257 , H01L23/53271 , H01L27/1104 , H01L27/1112 , H01L2924/0002 , Y10S257/904 , H01L2924/00
摘要： On a élaboré une structure de cellule mémoire compacte pour cellule mémoire à accès sélectif statique. La cellule possède deux transistors ayant des portes (30a, 30b) qui sont pratiquement parallèles l'une par rapport à l'autre. Une première interconnexion (45) connecte la porte (30b) d'un premier transistor à une électrode (35a) du second transistor. Une seconde interconnexion (46) connecte la porte (30a) du second transistor à une électrode (35b) du premier transistor. Les deux portes et les deux interconnexions forment pratiquement un rectangle. Une ligne (47) de circuit d'alimentation en courant est placée à l'extérieur du rectangle. Cette ligne et les deux interconnexions sont formées à partir d'une couche conductrice. En outre, dans un réseau de cellules mémoires, certaines lignes (37) de circuit sont formées dans le substrat, et d'autres lignes (47) de circuit sont formées directement au-dessus desdites lignes (37) formées dans le substrat. Les lignes (37) formées dans le substrat sont pourvues de prolongements (42a, 42b) qui permettant le contact desdites lignes (37) sans qu'il y ait contact avec les autres lignes (47) situées au-dessus.

6. 发明公开

EP0437307A2 High resistance polysilicon load resistor 失效
标题翻译： Polysilizlastwiderstand mit hohem Widerstand。
公开(公告)号：EP0437307A2
公开(公告)日：1991-07-17
申请号：EP91300026.1
申请日：1991-01-02
申请人： PARADIGM TECHNOLOGY, INC.
发明人： Godinho, Norman , Lee, Frank Tsu-Wei , Chen, Hsiang-Wen , Motta, Richard F. , Tsang, Juine-Kai , Tzou, Joseph , Baik, Jai-Man , Yen, Ting-Pwu
IPC分类号： H01L27/11 , H01L21/82 , H01L21/3205
CPC分类号： H01L21/82 , H01L27/1112 , H01L2924/0002 , Y10S257/915 , H01L2924/00
摘要： A load resistor for use in a semiconductor integrated circuit consists of two portions of conductive material, typically strips of either a silicide or a composite polycrystalline silicon layer and silicide layer formed thereon, formed on a semiconductor substrate and separated from each other by a selected distance. An electrically conductive dopant diffusion barrier is formed on the first and second portions of conductive material. A polycrystalline silicon material is then placed on the structure such that one portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the first portion of conductive material and the other portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the second portion of conductive material. Typically the polycrystalline silicon material is placed on an insulation layer formed on the semiconductor substrate in the portion of the substrate between the two portions of conductive material. The diffusion barrier prevents any dopant from the conductive material from diffusing into the polycrystalline silicon material thereby allowing the polycrystalline silicon material to function as a load resistor having a high resistance in the giga-ohms range. Subsequent high temperature processing of the structure does not change the resistance of the polycrystalline silicon because the dopant diffusion barrier prevents any dopant from the underlying conductive material from diffusing into the polycrystalline silicon material.
摘要翻译：用于半导体集成电路的负载电阻器由导电材料的两部分组成，通常形成在半导体衬底上并分离了一定距离的硅化物或复合多晶硅层和形成在其上的硅化物层的条带。在导电材料的第一和第二部分上形成导电掺杂剂扩散阻挡层。然后将多晶硅材料放置在结构上，使得多晶硅材料的一部分通过扩散阻挡层与导电材料的第一部分欧姆接触，并且多晶硅材料的另一部分通过扩散与欧姆接触阻挡导电材料的第二部分。通常，多晶硅材料被放置在形成在半导体衬底上的导电材料的两部分之间的衬底部分中的绝缘层上。扩散阻挡层防止导电材料中的任何掺杂剂扩散到多晶硅材料中，从而允许多晶硅材料用作千兆欧范围内具有高电阻的负载电阻器。结构的随后的高温处理不会改变多晶硅的电阻，因为掺杂剂扩散阻挡层阻止来自下面的导电材料的任何掺杂剂扩散到多晶硅材料中。

7. 发明公开

EP0672299A4 TRANSISTOR FABRICATION METHODS AND METHODS OF FORMING MULTIPLE LAYERS OF PHOTORESIST. 失效
标题翻译：用于生产的晶体管和方法的形成多层PHOTO涂料。
公开(公告)号：EP0672299A4
公开(公告)日：1997-02-19
申请号：EP94901678
申请日：1993-11-30
申请人： PARADIGM TECHNOLOGY INC
发明人： YEN TING-PWU , CHEN HSIANG-WEN
IPC分类号： H01L21/8238 , H01L21/265 , H01L21/336 , H01L21/8244 , H01L27/092 , H01L27/11 , H01L29/78 , H01L29/786 , H01L21/266
CPC分类号： H01L29/66765 , H01L27/11 , H01L27/1108 , H01L29/78621 , H01L29/78624
摘要： Transistor fabrication methods are provided for transistors with current carrying elements above a semiconductor substrate. Only few mask alignments define critical dimensions such as the channel length of a MOS transistor. In one embodiment, where the channel region (154) overlies the gate (110), a first mask (126) is formed over the channel region (154), and an LDD implant is carried out. A second mask (158) is formed over the LDD portion of the drain region (150). The second mask (158) is allowed to extend over the first mask (126). A heavy doping implant is carried out. An LDD structure is provided on the drain but not on the source side with only the first mask (126) defining the channel length (134). In some embodiments, both masks include photoresist. The first photoresist mask (126) is hardened to prevent its lifting during development of the resist of the second mask (158).
摘要翻译：提供晶体管制造方法的是适于，例如，对于具有高于半导体衬底的电流承载元件的晶体管。只有少数掩模对准定义的临界尺寸：诸如MOS晶体管的沟道长度。在一个实施例，其中所述沟道区覆盖在栅极，第一掩模形成在所述沟道区，然后到LDD注入被执行。第二掩模然后，在漏区的LDD部分形成。第二掩模被允许延伸过所述第一掩模。然后，将重掺杂注入被执行。 THUS LDD结构的只能与一个掩模的第一掩模通道限定长度提供在漏极侧上而不是在源极侧。在一些实施方案中，两个掩模包括光致抗蚀剂。所述第一光致抗蚀剂掩模被硬化，以防止所述第二掩模的抗蚀剂显影时其提升，此外，LDD注入之后，第一光致抗蚀剂掩模被除气，以提高第二光致抗蚀剂掩模的粘合性。在另一实施例中，第二掩模被用于图案化第一掩模。图案化蚀刻底切所述第二掩模。重掺杂注入后，将第二掩模被去除，并且该LDD注入，执行与所述第一掩模掩蔽所述沟道区。

8. 发明公开

EP0437306A3 Self-aligning contact and interconnect structure 失效
标题翻译：自对准接触和互连结构
公开(公告)号：EP0437306A3
公开(公告)日：1993-03-31
申请号：EP91300024.6
申请日：1991-01-02
申请人： PARADIGM TECHNOLOGY, INC.
发明人： Godinho, Norman , Lee, Frank Tsu-Wei , Chen, Hsiang-Wen , Motta, Richard F. , Tsang, Juine-Kai , Tzou, Joseph , Baik, Jai-Man , Yen, Ting-Pwu
IPC分类号： H01L21/60 , H01L21/3205 , H01L21/90 , H01L23/485
CPC分类号： H01L21/76897 , H01L21/76895 , H01L21/823864 , H01L21/823871 , H01L23/53257 , H01L23/53271 , H01L27/11 , H01L27/1104 , H01L2924/0002 , H01L2924/00
摘要： An MOS transistor for use in an integrated circuit, particularly CMOS integrated circuits, is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from a short circuiting to the gate by oxide insulation between the source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of titanium silicide encapulated by a thin film of titanium nitride.

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