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21. 发明授权

EP0074541B1 Method for the production of a semiconductor device comprising dielectrically isolating regions 失效
标题翻译：制造包含电介质隔离区域的半导体器件的方法
公开(公告)号：EP0074541B1
公开(公告)日：1989-03-01
申请号：EP82107889.6
申请日：1982-08-27
申请人： FUJITSU LIMITED
发明人： Ogawa, Tetsuya , Toyokura, Nobuo
IPC分类号： H01L21/76 , H01L21/324 , H01L21/90
CPC分类号： H01L21/28512 , H01L21/3245 , H01L21/743 , H01L21/76 , H01L21/76224 , H01L21/76801 , H01L21/76829

22. 发明授权

EP0162860B1 FABRICATION OF InP CONTAINING SEMICONDUCTOR DEVICES HAVING HIGH AND LOW RESISTIVITY REGIONS 失效
标题翻译：具有高电阻和低电阻率区域的包含半导体器件的制造
公开(公告)号：EP0162860B1
公开(公告)日：1988-01-27
申请号：EP84903874.0
申请日：1984-10-18
申请人： AT&T Corp.
发明人： CAPASSO, Federico , FOCHT, Marlin, Wilbert , MACRANDER, Albert, Tiemen , SCHWARTZ, Bertram
IPC分类号： H01L21/265 , H01L21/76 , H01L21/74
CPC分类号： H01L21/3245 , H01L21/2654 , H01L21/266 , H01L21/743 , H01L21/7605 , H01L21/8252 , Y10S148/084
摘要： The property of materials in the InP system, whereby helium ion or deuteron bombarded p-type material becomes highly resistive but n-type material remains relatively conductive, is utlized to fabricate integrated circuits which include buried semiconductor interconnections or bus bars (14) between devices (D1-D2).

23. 发明公开

EP0112657A3 Field effect transistor and process for fabricating it 失效
标题翻译：场效应晶体管及其制作方法
公开(公告)号：EP0112657A3
公开(公告)日：1986-11-26
申请号：EP83307213
申请日：1983-11-25
申请人： FUJITSU LIMITED
发明人： Kawata, Haruo , Nishi, Hidetoshi , Onodera, Hiroyuki , Yokoyama, Naoki
IPC分类号： H01L29/10 , H01L29/80 , H01L21/265 , H01L21/318
CPC分类号： H01L29/66878 , H01L21/26546 , H01L21/26553 , H01L21/318 , H01L21/3245 , H01L29/1029 , H01L29/36 , H01L29/475 , H01L29/812
摘要： A field effect transistor (FET) comprises a source (8), a drain (9), and a control gate (6) on a compound semiconductor (e. g. GaAs) substrate (1). The FET has an ion-implanted channel layer (4) in the substrate adjacent the top surface thereof, below the control gate. The concentration of ions (i. e. the carrier concentration) in the channel layer has an maximum value at the top surface and decreases monotonically from that surface towards the inside thereof. This is achieved by ion implantation for the channel layer through an insulating layer (2) on the substrate. The insulating layer is preferably an A1 N layer, since such a layer has no adverse effects on the GaAs substrate during ion implantation and during subsequent heat treatment, and so allows higher uniformity of the threshold voltages of the FETs. FETs formed by this throug-implantation process have a high transconductance.

24. 发明公开

EP0196897A1 Thermal etching of a compound semiconductor 失效
标题翻译： ThermischesÄtzeneines Verbindungshalbleiters。
公开(公告)号：EP0196897A1
公开(公告)日：1986-10-08
申请号：EP86302355.2
申请日：1986-03-27
申请人： FUJITSU LIMITED
发明人： Saito, Junji
IPC分类号： H01L21/324 , H01L21/302 , C30B23/02
CPC分类号： H01L21/3245 , C30B23/02 , C30B29/42 , H01L21/02392 , H01L21/02395 , H01L21/02398 , H01L21/02463 , H01L21/02546 , H01L21/02576 , H01L21/02631 , H01L21/02658 , H01L21/2633
摘要： A process for thermally etching a CaAs substrate prior to molecular beam epitaxy comprises the steps of: heating the GaAs substrate to above 750°C.- at which temperature both Ga and As are evaporated from the GaAs substrate- whilst irradiating it with an As molecular beam, thereby removing contamination adhering to the surface of the GaAs substrate. As the substrate evaporates it carries with it the contamination. The process can be performed by an apparatus comprising a prechamber (2), in which the surface is evaporated, connected to a growth chamber (6), in which an epitaxial layer is grown.
摘要翻译：在分子束外延之前对CaAs衬底进行热蚀刻的方法包括以下步骤：将GaAs衬底加热至高于750℃，在该温度下，Ga和As从GaAs衬底蒸发，同时用As分子从而去除附着在GaAs衬底表面上的污染物。当基底蒸发时，它携带污染物。该方法可以通过包括其中表面蒸发的预室（2）的设备连接到其中生长外延层的生长室（6）进行。

25. 发明授权

EP0055140B1 Method of manufacturing a GaAs field effect transistor 失效
标题翻译：制造GAAS场效应晶体管的方法
公开(公告)号：EP0055140B1
公开(公告)日：1986-02-26
申请号：EP81306110.8
申请日：1981-12-23
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Toyoda, Nobuyuki , Hojo, Akimichi
IPC分类号： H01L21/28 , H01L21/64
CPC分类号： H01L29/66863 , H01L21/3245 , H01L29/80

26. 发明公开

EP0139435A3 Improving compound semiconductor crystal by heat treatment and crystals improved thereby 失效
标题翻译：通过热处理和晶体改善化合物半导体晶体
公开(公告)号：EP0139435A3
公开(公告)日：1985-12-27
申请号：EP84306036
申请日：1984-09-04
申请人： NIPPON TELEGRAPH AND TELEPHONE CORPORATION , SUMITOMO ELECTRIC INDUSTRIES LIMITED
发明人： Miyazawa, Shintaro , Murai, Shigeo c/o OSAKA WORKS OF SUMITOMO
IPC分类号： H01L21/324
CPC分类号： H01L21/26546 , H01L21/265 , H01L21/3245 , Y10S148/084
摘要： The quality of a compound semiconductor crystal such as gallium arsenide used for an integrated circuit is upgraded by a method comprising optionally forming a protective film on the obverse surface and reverse surface of a substrate consisting of a compound semiconductor crystal, subjecting the substrate to a heat treatment in an inert atmosphere at a temperature of at least same as the activating temperature after ion implantation into the substrate and then optionally removing the protective film.

27. 发明公开

EP0111085A3 Ion implantation process for compound semiconductor 失效
标题翻译：复合半导体离子注入工艺
公开(公告)号：EP0111085A3
公开(公告)日：1985-05-15
申请号：EP83109941
申请日：1983-10-05
申请人： International Business Machines Corporation
发明人： Hodgson, Rodney Trevor , Jackson, Thomas Nelson , Rupprecht, Hans Stephan , Woodall, Jerry MacPherson
IPC分类号： H01L21/265 , H01L21/324
CPC分类号： H01L21/3245 , H01L21/26546 , H01L21/314
摘要： Implanted impurity ions are activated in a compound semiconductor crystal wafer (1, 3), such as GaAs over a broad integrated circuit device area (4) by providing a uniform solid layer (5) (eg 10 A to 500 A thick) of the most volatile element of the compound over the surface (2) of the device area (4) and annealing the crystal wafer at a temperature of 800°C to 900°C for a period of 1 to 20 seconds. The layer (5) of the most volatile element may either be formed on a backing substrate (6) or formed as a coating on the surface (2) of the crystal wafer (1, 3).

28. 发明公开

EP0112657A2 Field effect transistor and process for fabricating it 失效
标题翻译： Feldeffekttransistor和Verfahren zu seiner Herstellung。
公开(公告)号：EP0112657A2
公开(公告)日：1984-07-04
申请号：EP83307213.5
申请日：1983-11-25
申请人： FUJITSU LIMITED
发明人： Kawata, Haruo , Nishi, Hidetoshi , Onodera, Hiroyuki , Yokoyama, Naoki
IPC分类号： H01L29/10 , H01L29/80 , H01L21/265 , H01L21/318
CPC分类号： H01L29/66878 , H01L21/26546 , H01L21/26553 , H01L21/318 , H01L21/3245 , H01L29/1029 , H01L29/36 , H01L29/475 , H01L29/812
摘要： A field effect transistor (FET) comprises a source (8), a drain (9), and a control gate (6) on a compound semiconductor (e. g. GaAs) substrate (1). The FET has an ion-implanted channel layer (4) in the substrate adjacent the top surface thereof, below the control gate. The concentration of ions (i. e. the carrier concentration) in the channel layer has an maximum value at the top surface and decreases monotonically from that surface towards the inside thereof. This is achieved by ion implantation for the channel layer through an insulating layer (2) on the substrate. The insulating layer is preferably an A1 N layer, since such a layer has no adverse effects on the GaAs substrate during ion implantation and during subsequent heat treatment, and so allows higher uniformity of the threshold voltages of the FETs. FETs formed by this throug-implantation process have a high transconductance.
摘要翻译：场效应晶体管（FET）包括在化合物半导体（例如GaAs）衬底（1）上的源极（8），漏极（9）和控制栅极（6）。 FET在衬底附近具有离子注入沟道层（4），其位于控制栅极下方的顶部附近。沟道层中的离子浓度（即载流子浓度）在顶表面具有最大值，并从该表面朝向其内部单调减小。这通过离子注入通过衬底上的绝缘层（2）来实现。绝缘层优选为AlN层，因为这样的层在离子注入期间和后续热处理期间对GaAs衬底没有不利影响，因此允许FET的阈值电压更高的均匀性。通过该注入工艺形成的FET具有高的跨导。

29. 发明公开

EP3349238A1 METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR SUBSTRATE, NITRIDE SEMICONDUCTOR SUBSTRATE, AND DEVICE FOR HEATING SAME 审中-公开
公开(公告)号：EP3349238A1
公开(公告)日：2018-07-18
申请号：EP16844489.1
申请日：2016-09-09
申请人： Mie University
发明人： MIYAKE, Hideto
IPC分类号： H01L21/20 , C23C16/18 , C23C16/34 , C30B29/38 , H01L21/205 , H01L21/324
CPC分类号： C23C16/18 , C23C16/34 , C30B29/38 , C30B29/406 , H01L21/02172 , H01L21/02205 , H01L21/02304 , H01L21/02389 , H01L21/0254 , H01L21/20 , H01L21/205 , H01L21/324 , H01L21/3245
摘要： A method for manufacturing a nitride semiconductor substrate (1) includes: a preparation step (S10) of preparing a sapphire substrate (2); and a buffer layer forming step (S16) of forming an AIN buffer layer (3) on the sapphire substrate (2), wherein the buffer layer forming step (S16) includes: a group III nitride semiconductor forming step (S16a) of forming a precursor (3a) of an AIN buffer layer on the sapphire substrate (2); and an annealing step (S16b) of annealing the sapphire substrate (2) on which the precursor (3a) of the AIN buffer layer is formed in a gas-tight state in which a principal surface of the precursor (3a) of the AIN buffer layer is covered with a cover member (such as a sapphire substrate (102)) for inhibiting a component of the group III nitride semiconductor from dissociating from the principal surface of the formed precursor (3a) of the AIN buffer layer.

30. 发明公开

EP2963674A1 PROCÉDÉ DE RÉALISATION D'UN DISPOSITIF MICROÉLECTRONIQUE 审中-实审
标题翻译：微电子器件的制备过程
公开(公告)号：EP2963674A1
公开(公告)日：2016-01-06
申请号：EP15174396.0
申请日：2015-06-29
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
发明人： AUGENDRE, Emmanuel , BARON, Thierry
IPC分类号： H01L21/02 , H01L29/66
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02452 , H01L21/02458 , H01L21/02463 , H01L21/02532 , H01L21/02535 , H01L21/0254 , H01L21/02546 , H01L21/02598 , H01L21/02636 , H01L21/02639 , H01L21/30604 , H01L21/30612 , H01L21/3081 , H01L21/31 , H01L21/31116 , H01L21/324 , H01L21/3245 , H01L21/823431 , H01L29/04 , H01L29/165 , H01L29/2003 , H01L29/205 , H01L29/66795 , H01L29/7849 , H01L29/785
摘要： L'invention concerne un procédé de réalisation d'une couche cristalline à partir d'un substrat (100) cristallin en un premier matériau sur lequel a préalablement été déposée une couche de masquage (200) ; ladite couche de masquage (200) comprenant au moins une tranchée formant un accès au substrat (100), caractérisé en ce que la tranchée présente une profondeur au moins égale à une valeur Hc telle que Hc= K.S.tan(θ) où K est au moins supérieur à 0.7, S est la largeur de la tranchée et θ est l'angle des dislocations par rapport au plan du substrat (100) et en ce le procédé comprend les étapes suivantes :
- formation d'une couche tampon (300) cristalline située en partie au moins dans la tranchée de la couche de masquage (200), s'étendant depuis le substrat (100) et formant saillie au-delà de la couche de masquage (200) de sorte à ce qu'une partie supérieure des flancs latéraux de ladite couche tampon (300) soit laissée à découvert, l'étape de formation comprenant une croissance de la couche tampon (300) à partir du substrat (100) de manière à donner à la couche tampon (300) la structure cristalline du substrat (100) cristallin,
- formation d'une couche épitaxiale (500) cristalline en un deuxième matériau, différent du matériau de la couche tampon (300), par croissance à partir de ladite partie supérieure des flancs latéraux de la couche tampon (300) laissée à découvert,
et la formation de la couche tampon (300) est effectuée de manière à laisser à découvert une face supérieure de la couche tampon (300) en plus de ladite partie supérieure des flancs latéraux de la couche tampon (300) et en ce que, préalablement à la formation de la couche épitaxiale (500), on réalise la formation d'une couche de protection (400) sur ladite face supérieure de la couche tampon (300) de sorte à laisser découvert uniquement ladite partie supérieure des flancs latéraux de la couche tampon (300) laissée à découvert.

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