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11. 发明公开

EP0294614A3 m bit to n bit code converting circuit 失效
标题翻译： M位转码转换电路
公开(公告)号：EP0294614A3
公开(公告)日：1991-09-18
申请号：EP88107734.1
申请日：1988-05-13
申请人： FUJITSU LIMITED
发明人： Hongo, Yoshiyuki , Takatsu, Kazuo , Otsuka, Masanori
IPC分类号： H03M7/20
CPC分类号： H04L25/4908 , H03M7/20
摘要： An mBnB code converting circuit for converting an input m bits data into an n bits code including a status check/hold means (80) which is setting and holding a status bit corresponding to a mark ratio of an input m bits data with an input m bits data. After setting and checking a status bit are complete, the status bit is transmitted to the code converter (3) in order to control the code converter (3), and the held input m bits data is also transmitted to an output selection circuit (4) with an n bits code from the code converter (3). An mBnB code converting circuit for decoding an input n bits code into an m bits data is also provided in the same manner.

12. 发明公开

EP2893534A1 DIFFERENTIAL VECTOR STORAGE FOR DYNAMIC RANDOM ACCESS MEMORY 有权
标题翻译： SPEICHERUNG DIFFERENTIELLER VEKTORENFÜRDYNAMISCHE DIREKTZUGRIFFSPEICHER
公开(公告)号：EP2893534A1
公开(公告)日：2015-07-15
申请号：EP13765641.9
申请日：2013-09-06
申请人： Kandou Labs S.A.
发明人： CRONIE, Harm , SHOKROLLAHI, Amin
IPC分类号： G11C7/10 , G11C11/406 , G11C11/56 , H03M7/20
CPC分类号： G11C11/4087 , G11C7/1006 , G11C11/406 , G11C11/4096 , G11C11/565 , H03M7/20
摘要： A storage device stores data in groups of memory cells using vectors corresponding to voltage code codewords, each codeword having k entries. Entries have values selected from a set of at least three entry values and 2n distinct inputs can be encoded into k-entry codewords for some n>k. A vector storage element comprising k cells can store an k electrical quantities (voltage, current, etc.) corresponding to a codeword. The voltage code is such that, for at least one position of a vector, there are at least three vectors having distinct entry values at that position and, for at least a subset of the possible codewords, the sum of the entry values over the positions of the each vector is constant from vector to vector in that subset. The storage device might be an integrated circuit device, a discrete memory device, or a device having embedded memory.
摘要翻译：存储装置使用与电压代码字对应的向量来存储存储单元组的数据，每个码字具有k个条目。条目具有从一组至少三个条目值中选择的值，并且对于某些n> k，2n个不同的输入可被编码为k个入口码字。包括k个单元的矢量存储元件可以存储对应于码字的k个电量（电压，电流等）。电压代码使得对于向量的至少一个位置，存在至少三个在该位置处具有不同入口值的向量，并且对于至少一个可能码字的子集，在位置上的入口值之和的每个向量在该子集中从向量到向量是恒定的。存储设备可以是集成电路设备，分立存储设备或具有嵌入式存储器的设备。

13. 发明公开

EP2885875A1 PROCEDE D'ENCODAGE DE DONNEES SUR UNE CARTE A PUCE PAR DES CODES DE POIDS CONSTANT 审中-公开
标题翻译： VERFAHREN ZUR DATENCODIERUNG AUF EINER CHIPKARTE MITTELS GEWICHTSKONSTANTER代码
公开(公告)号：EP2885875A1
公开(公告)日：2015-06-24
申请号：EP14701692.7
申请日：2014-01-17
申请人： Morpho
发明人： BRINGER, Julien , SERVANT, Victor
IPC分类号： H03M7/20 , G06K19/07 , G06F11/08
CPC分类号： G06F21/75 , G06F11/10 , G06K19/07309 , G09C1/00 , H03M7/20 , H04L9/003 , H04L9/004 , H04L9/06 , H04L2209/34
摘要： The invention relates to a data-processing method that includes encoding a plurality of data of n bits into code words having a predefined constant Hamming weight, characterized in that said method also includes using (4000) encryption operations or arithmetic operations on the resulting code word(s) and also in that encoding each datum includes: decomposing (100) the datum into a plurality of m bit sequences to be encoded, m strictly being less than n; encoding (300) each bit sequence into a partial code word, each having a predefined Hamming weight, such that the sum of the Hamming weights of the partial code words are equal to the Hamming weights of the code word; and concatenating (300) the partial code words such as to produce the code word corresponding to the datum. The invention also relates to a data transmission method and to an electronic circuit configured to implement said methods.
摘要翻译：本发明涉及一种数据处理方法，其包括将n位的多个数据编码为具有预定义恒定汉明权重的码字，其特征在于，所述方法还包括对所得到的码字进行（4000）加密操作或算术运算并且还在于每个数据的编码包括：将数据分解（100）到要被编码的多个m位序列，m严格小于n; 将每个比特序列编码（300）到部分码字中，每个具有预定的汉明权重，使得部分码字的汉明权重的和等于码字的汉明权重; 并连接（300）部分代码字，以产生对应于该数据的代码字。本发明还涉及一种数据传输方法和一种被配置为实现所述方法的电子电路。

14. 发明公开

EP2208327A4 SIMPLIFIED RECEIVER FOR USE IN MULTI-WIRE COMMUNICATION 审中-公开
标题翻译：简化接收机中使用，在多线通信
公开(公告)号：EP2208327A4
公开(公告)日：2012-01-04
申请号：EP08836641
申请日：2008-09-30
申请人： RAMBUS INC
发明人： ABBASFAR ALIAZAM
IPC分类号： H04L25/49 , H03M7/20 , H03M13/37
CPC分类号： H03M13/3761 , H03M7/20

15. 发明授权

EP2129063B1 Signal processing apparatus, signal processing system and signal processing method 有权
标题翻译：信号处理装置，信号处理系统及信号处理方法
公开(公告)号：EP2129063B1
公开(公告)日：2011-11-30
申请号：EP09161320.8
申请日：2009-05-28
申请人： Sony Corporation
发明人： Sugita, Takehiro
IPC分类号： H04L25/493 , H04L25/49 , H03M5/20
CPC分类号： H04L25/4917 , H03M5/20 , H03M7/20 , H04L25/493

16. 发明公开

EP2129063A3 Signal processing apparatus, signal processing system and signal processing method 有权
标题翻译：信号处理装置，信号处理系统及信号处理方法
公开(公告)号：EP2129063A3
公开(公告)日：2010-08-11
申请号：EP09161320.8
申请日：2009-05-28
申请人： Sony Corporation
发明人： Sugita, Takehiro
IPC分类号： H04L25/493 , H04L25/49 , H03M5/20
CPC分类号： H04L25/4917 , H03M5/20 , H03M7/20 , H04L25/493
摘要： A signal processing apparatus (234) is provided, which generates a data signal having a signal waveform corresponding to a first bit value of a signal waveform transitioning from a high level to a low level or a signal waveform transitioning from a low level to a high level, a pre-transition signal level corresponding to a second bit value of one of a plurality of high levels and a plurality of low levels, and a post-transition signal level corresponding to a third bit value of the other.

17. 发明公开

EP2127145A1 MECHANISM FOR CHANNEL SYNCHRONIZATION 失效转让
标题翻译：机构通道同步
公开(公告)号：EP2127145A1
公开(公告)日：2009-12-02
申请号：EP08728250.5
申请日：2008-01-25
申请人： Cisco Technology, Inc.
发明人： SHARMA, Neil , LAWSON, Matthew Todd , JACOBS, Mick R.
IPC分类号： H04B7/212
CPC分类号： H04J3/0685 , H03K5/135 , H03M5/04 , H03M7/20 , H03M9/00 , H04J3/0602 , H04J3/0635 , H04L7/041 , H04L25/0264
摘要： A channel synchronization method in which local serializers serially transmits first n-bit codes, respectively, to remote deserializers, respectively. Also local deserializers serially receive first n-bit codes, respectively, from remote serializers, respectively. One of the first n-bit codes transmitted to one of the remote serializers indicates one of the local deserializers is not link aligned.

18. 发明公开

EP1391040A2 8B/10B ENCODING AND DECODING FOR HIGH SPEED APPLICATIONS 审中-公开
标题翻译： 8B / 10B编码和解码FOR FAST赫哲族SIMPLICITY申请
公开(公告)号：EP1391040A2
公开(公告)日：2004-02-25
申请号：EP02734126.2
申请日：2002-04-30
申请人： International Business Machines Corporation
发明人： WIDMER, Albert, X.
IPC分类号： H03M5/14 , H04L25/49
CPC分类号： H03M7/20 , H03M5/14
摘要： During decoding and encoding, the starting disparity of a current block is computed by using a disparity at some previous reference point and disparity characteristics of bytes from the reference point to a current block boundary. The characteristics of the bytes are whether the bytes are unbalanced coded vectors and whether the number of unbalanced vectors is even or odd. Alternately, the characteristics of the bytes are whether the bytes are balanced and how many balanced coded vectors exist. New classifications are created for encoding and decoding 3B/4B and 5B/6B transmission codes. Separate functions are created that address specifically disparity aspects. A dispartiy violation at the front of a byte is detected during decoding by comparing a required front-end disparity of the byte with the actual running disparity by assuming the actual running disparity is equivalent to an exit disparity of the next preceding byte that is disparity dependent.

19. 发明公开

EP0965172A2 DEVICE FOR ENCODING/DECODING N-BIT SOURCE WORDS INTO CORRESPONDING M-BIT CHANNEL WORDS, AND VICE VERSA 有权
标题翻译： DEVICE FOR n位源字编码/解码为相应的m位信道字与反之亦
公开(公告)号：EP0965172A2
公开(公告)日：1999-12-22
申请号：EP99900067.0
申请日：1999-01-08
申请人： Koninklijke Philips Electronics N.V.
发明人： KAHLMAN, Josephus, A., H., M.
IPC分类号： G11B20 , H03M5 , H03M7
CPC分类号： H03M5/145 , H03M7/20
摘要： A device is disclosed for encoding a stream of databits of a binary source signal into a stream of databits of a binary channel signal. The device comprises a merging unit (4') for merging a 1-bit merging word at equidistant positions in the serial datastream of the binary source signal, so as to obtain a composite binary source signal. A shuffling step is carried out on the composite binary source signal in a shuffling unit (8'). Next a conversion is carried out in a converter unit (10'), resulting in the channel signal (Fig. 2). Further, a decoding device is disclosed for decoding the channel signal obtained by means of the encoding device.

20. 发明公开

EP0294614A2 m bit to n bit code converting circuit 失效
标题翻译：沙尔贡·祖尔·辛辛格（Kertung zur Hinsetzung）
公开(公告)号：EP0294614A2
公开(公告)日：1988-12-14
申请号：EP88107734.1
申请日：1988-05-13
申请人： FUJITSU LIMITED
发明人： Hongo, Yoshiyuki , Takatsu, Kazuo , Otsuka, Masanori
IPC分类号： H03M7/20
CPC分类号： H04L25/4908 , H03M7/20
摘要： An mBnB code converting circuit for converting an input m bits data into an n bits code including a status check/hold means (80) which is setting and holding a status bit corresponding to a mark ratio of an input m bits data with an input m bits data.
After setting and checking a status bit are complete, the status bit is transmitted to the code converter (3) in order to control the code converter (3), and the held input m bits data is also transmitted to an output selection circuit (4) with an n bits code from the code converter (3).
An mBnB code converting circuit for decoding an input n bits code into an m bits data is also provided in the same manner.
摘要翻译：一种用于将输入的m位数据转换为包括状态检查/保持装置（80）的n位代码的mBnB代码转换电路，该状态检查/保持装置（80）正在设置并保持与输入m位数据的标记比相对应的状态位与输入m 位数据。在设置和检查状态位完成之后，将状态位发送到代码转换器（3），以便控制代码转换器（3），并且保持的输入m位数据也被发送到输出选择电路（4））与来自代码转换器（3）的n位代码。用于将输入的n位代码解码为m位数据的mBnB代码转换电路也以相同的方式提供。

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