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1. 发明授权

EP2893534B1 DIFFERENTIAL VECTOR STORAGE FOR DYNAMIC RANDOM ACCESS MEMORY 有权
公开(公告)号：EP2893534B1
公开(公告)日：2019-03-20
申请号：EP13765641.9
申请日：2013-09-06
申请人： Kandou Labs S.A.
发明人： CRONIE, Harm , SHOKROLLAHI, Amin
IPC分类号： G11C7/10 , G11C11/406 , G11C11/56 , H03M7/20

2. 发明公开

EP3116261A4 METHOD FOR TRANSMITTING PHYSICAL LAYER DATA AND DATA TRANSMISSION DEVICE 审中-公开
标题翻译： VERFAHREN ZURÜBERTRAGUNGVON PL-DATEN UNDDATENÜBERTRAGUNGSVORRICHTUNG
公开(公告)号：EP3116261A4
公开(公告)日：2017-03-08
申请号：EP14887092
申请日：2014-03-24
申请人： HUAWEI TECH CO LTD
发明人： WANG JUEPING , ZHANG SI , ZOU ZHIQIANG , JIANG YAJUN , GONG XIAONIAN
IPC分类号： H04W28/06 , H03M7/20 , H03M7/30
CPC分类号： H04W72/00 , H03M7/20 , H03M7/3059 , H03M7/3064 , H04L1/0001

3. 发明授权

EP0691750B1 Digital modulating/demodulating method and apparatus using same 失效
标题翻译：一种用于数字调制/解调及其装置的使用过程
公开(公告)号：EP0691750B1
公开(公告)日：2002-04-17
申请号：EP95304776.8
申请日：1995-07-07
申请人： VICTOR COMPANY OF JAPAN, LIMITED
发明人： Mori, Takaro , Matsui, Kazunari , Hayashiyama, Takumi
IPC分类号： H03M7/20 , G11B5/09
CPC分类号： H04L25/4915 , G11B20/1426 , H03M5/145

4. 发明授权

EP0214261B1 SIGNAL GENERATION 失效
标题翻译：信号发生
公开(公告)号：EP0214261B1
公开(公告)日：1990-08-08
申请号：EP86901922.4
申请日：1986-03-06
申请人： BRITISH TELECOMMUNICATIONS public limited company
发明人： HOOPER, Raymond, Charles 3 Netherwood Court
IPC分类号： H03M7/20 , G11B20/14 , H04L25/49
CPC分类号： G02B6/2938 , G02B6/2861 , G02B6/29352 , G02B6/29395 , H03M5/145 , H04J14/08
摘要： A method and apparatus for generating signals representing a plurality (p) of n bit words corresponding to respective input signals. The apparatus comprises a basic word generator (7) for generating first signals representing m basic words (A-D) whereby the p words are the same as or are cyclic rearrangements of the n bits of the m basic words. Control means including combinatorial logic (33) determines the one of the p words corresponding to each input signal and generates corresponding control signals. Selection means including optical modulators (10-13, 20-25) are responsive to the control signals for selecting the appropriate first signal, if necessary after recycling by imposing selected delays, to constitute an output signal corresponding to the determined one of the p words.

5. 发明授权

EP3804246B1 SKEW DETECTION AND CORRECTION FOR ORTHOGONAL DIFFERENTIAL VECTOR SIGNALING CODES 有权转让
公开(公告)号：EP3804246B1
公开(公告)日：2023-08-16
申请号：EP19734970.7
申请日：2019-06-07
发明人： HORMATI, Ali
IPC分类号： H04L25/02 , H04L7/00 , H04L25/49 , H03M7/20 , H04B3/02 , H04L1/00 , H04L25/08 , H04L25/14

6. 发明授权

EP0797826B1 APPARATUS FOR DECODING A CHANNEL SIGNAL INTO AN INFORMATION SIGNAL AND REPRODUCING ARRANGEMENT PROVIDED WITH THE APPARATUS 失效
标题翻译：用于解码的设备信道信号的信息信号和重放设备
公开(公告)号：EP0797826B1
公开(公告)日：2002-01-09
申请号：EP96931195.0
申请日：1996-10-03
申请人： Koninklijke Philips Electronics N.V.
发明人： DE ANDRADE RIBEIRO FILHO, Milton , SCHOUHAMER IMMINK, Kornelis, A.
IPC分类号： G11B20/14 , H03M7/20 , H03M13/00 , H04L7/04
CPC分类号： H04L7/042 , G11B20/1403 , G11B20/1426 , G11B20/1876 , G11B27/3027
摘要： An apparatus for decoding a channel signal into an information signal is disclosed. The channel signal comprises subsequent blocks (BLOCK) of information, a block of information comprising a sync word (SYNC) and a plurality of channel words (cw1, cw2, ...). The information signal comprising subsequent information words. The apparatus comprising an input terminal (1) for receiving the channel signal, a conversion unit (3) for converting the channel words into the information words. Further, an error concealment unit (6) is present. The information signal obtained is supplied to an output terminal (8). The conversion unit (3) comprises a channel word detector (in 20) for establishing whether channel words received are channel words not belonging to a group of valid channel words. If so, the channel word detector is adapted to supply a detection signal upon such detection. This enables the detection signals to be counted so as to establish a mis-synchronization of the decoding apparatus.

7. 发明公开

EP0557601A1 N-bit parallel input to variable-bit parallel output shift register 失效
标题翻译：移位寄存器N位平行Eingang和变量位Parallelausgang。
公开(公告)号：EP0557601A1
公开(公告)日：1993-09-01
申请号：EP92120809.6
申请日：1992-12-05
申请人： ALCATEL N.V.
发明人： Peters, Richard William
IPC分类号： H03M7/00 , H03M7/20 , H03M9/00
CPC分类号： H04J3/076
摘要： n-parallel bits of data are input to a parallel in - parallel out shift register made of n+m n:1 parallel multiplexers and n-parallel bits of either pure data or combined stuff and data bits are output where, for cycles in which stuff bits are inserted, the non-outputted data bits are recirculated for output on a subsequent cycle followed by newly incoming data bits; such is shown used to advantage in a bit stuffing technique where a synchronous payload envelope pattern may be started at a selected location in a synchronous transport signal frame by monitoring a frame starting signal and providing a pattern starting signal at a selected point after the occurrence of the frame starting signal.
摘要翻译： n并行数据位被输入到由n + mn：1个并行多路复用器构成的并行输出移位寄存器，并且输出纯数据或组合填充和数据位的n个并行位，其中，插入未被输出的数据位，并在随后的周期再循环输出数据，随后再输入数据位; 这被示出用于位填充技术中，其中可以在同步传输信号帧中的选定位置处启动同步有效负载包络图案，通过监视帧起始信号并在发生后的选定点提供模式启动信号帧启动信号。

8. 发明公开

EP0493044A3 Digital modulation 失效
标题翻译：数字调制
公开(公告)号：EP0493044A3
公开(公告)日：1992-08-26
申请号：EP91311908.7
申请日：1991-12-20
申请人： SONY CORPORATION
发明人： Isozaki, Masaaki, c/o Patents Division
IPC分类号： H03M7/14 , H03M7/20 , H03M7/40
CPC分类号： H03M5/145 , G11B20/1426 , H04L25/4908
摘要： A digital modulation system is disclosed in which a string of input data is divided at an interval of eight bits and the resulting 8-bit data is converted into 16-bit modulated digital code data. Code conversion is so made that the resulting 16-bit modulation code has two or more consecutive numbers between the first and 16th bits, four or less consecutive numbers between the 13th and the 16th bits, the CDS of the totality of 16 bits in the modulation code block is not more than four, and the DSV from the leading bit to an arbitrary bit in the modulation code block is not more than five, so that the number of consecutive numbers in any portion of the digital data is not less than two and not more than five and the absolute value of the DSV is not more than three.

9. 发明公开

EP0493044A2 Digital modulation 失效
标题翻译：数字调制
公开(公告)号：EP0493044A2
公开(公告)日：1992-07-01
申请号：EP91311908.7
申请日：1991-12-20
申请人： SONY CORPORATION
发明人： Isozaki, Masaaki, c/o Patents Division
IPC分类号： H03M7/14 , H03M7/20 , H03M7/40
CPC分类号： H03M5/145 , G11B20/1426 , H04L25/4908
摘要： A digital modulation system is disclosed in which a string of input data is divided at an interval of eight bits and the resulting 8-bit data is converted into 16-bit modulated digital code data. Code conversion is so made that the resulting 16-bit modulation code has two or more consecutive numbers between the first and 16th bits, four or less consecutive numbers between the 13th and the 16th bits, the CDS of the totality of 16 bits in the modulation code block is not more than four, and the DSV from the leading bit to an arbitrary bit in the modulation code block is not more than five, so that the number of consecutive numbers in any portion of the digital data is not less than two and not more than five and the absolute value of the DSV is not more than three.
摘要翻译：公开了一种数字调制系统，其中一串输入数据以八位的间隔被划分，所得到的8位数据被转换成16位调制数字码数据。这样做的代码转换使得所得到的16位调制码在第一和第十六位之间具有两个或更多个连续的数字，在第十三和第十六位之间的四个或更少的连续数，调制中总共16位的CDS 码块不超过4个，调制码块中从前导位到任意位的DSV不超过5个，使数字数据的任意部分的连续数不少于2个，不超过5个，DSV的绝对值不超过3个。

10. 发明公开

EP0392506A2 Digital modulation method 有权
标题翻译：数字调制器
公开(公告)号：EP0392506A2
公开(公告)日：1990-10-17
申请号：EP90106948.4
申请日：1990-04-11
申请人： NIPPON HOSO KYOKAI
发明人： Uehara, Toshihiro, c/o NHK Science and , Minaguchi, Hotaka, c/o NHK Science and , Oba, Yoshinobu, c/o NHK Science and
IPC分类号： G11B20/14 , H03M7/20 , H03M5/14
CPC分类号： H03M5/145
摘要： A digital modulation method for modulating 8-bit digital data into 14-bit digital modulation codes. The number of consecutive identical bits in a series of 14-bit digital modulation codes is restricted to 2 - 7. The absolute value of DSV at the end of each 14-bit digital modulation code is restricted to 2 or less, and the absolute value of DSV at each bit of any 14-bit digital modulation codes is limited to 7 or less. The direct current component of the 14-bit modulation codes can be effectively reduced.
摘要翻译：一种用于将8位数字数据调制成14位数字调制码的数字调制方法。一系列14位数字调制码中连续相同位的数目限制在2〜7个。每个14位数字调制码结束时的DSV绝对值限制在2以下，绝对值的任何14位数字调制码的每个位的DSV限制在7以下。可以有效地降低14位调制码的直流分量。

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