专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP4455828A1 SYNCHRONIZATION OF MULTIPLE CLOCK DIVIDERS BY USING LOWER-FREQUENCY CLOCKS AND SLIPPING CYCLES 审中-公开
公开(公告)号：EP4455828A1
公开(公告)日：2024-10-30
申请号：EP24172083.8
申请日：2024-04-24
申请人： Avago Technologies International Sales Pte. Limited
发明人： Schell, Robert
IPC分类号： G06F1/12 , H03K5/135 , H03L7/081
CPC分类号： G06F1/12 , H03L7/0812 , H03K5/135
摘要： Systems and methods for synchronizing multiple of output clocks. The system includes: a plurality of frequency dividers configured to receive a plurality of input clock signals and produce a plurality of output clock signals, wherein each of the plurality of output clock signals are lower in frequency than a corresponding input clock signal; and a circuit. The circuit is configured to: compare a first output clock signal of the plurality of output clock signals to a second output clock signal of the plurality of output clock signals to determine whether the first output clock signal is synchronized with the second output clock signal, generate a slip signal in response to determining that the first output clock signal is not synchronized with the second output clock signal, and apply the slip signal to the second output clock signal to synchronize the second output clock signal with the first output clock signal.

2. 发明授权

EP3675359B1 PHASE INTERPOLATOR 有权
公开(公告)号：EP3675359B1
公开(公告)日：2024-10-09
申请号：EP19219260.7
申请日：2019-12-23
IPC分类号： H03K5/135 , H03K5/00
CPC分类号： H03K2005/0005220130101 , H03K5/135

3. 发明公开

EP4380057A1 ENHANCEMENT OF LINEARITY FOR DIGITALLY CONTROLLED DELAY LINE 审中-公开
公开(公告)号：EP4380057A1
公开(公告)日：2024-06-05
申请号：EP23211398.5
申请日：2023-11-22
申请人： MediaTek Inc.
发明人： ELMALLAH, Ahmed Safwat Mohamed Aboelenein , KHASHABA, Amr Tarek Ahmed Abdelrazik , ABDULLATIF, Mohammed Mohsen Abdulsalam , ALI, Tamer Mohammed
IPC分类号： H03L7/081 , H03L7/08 , H03K5/131 , H03K5/133 , H03K5/135
CPC分类号： H03L7/081 , H03L7/08 , H03K5/131 , H03K5/133 , H03K5/135
摘要： A digitally controlled delay device includes a plurality of first delay stages connected in series between a first input port and a first output port, and a plurality of second delay stages connected in series between a second input port and a second output port. Each first delay stage of the plurality of first delay stages includes a plurality of first delay elements and each second delay stage of the plurality of second delay stages includes a corresponding plurality of second delay elements. A controller performs complementary control based on a digital control signal by controlling one or more of the plurality of first delay elements to be in a first control state and controlling a corresponding one or more of the plurality of second delay elements to be in a second control state, opposite the first control state.

4. 发明公开

EP3408938A1 PHASE INTERPOLATOR AND METHOD OF IMPLEMENTING A PHASE INTERPOLATOR 有权
公开(公告)号：EP3408938A1
公开(公告)日：2018-12-05
申请号：EP16816469.7
申请日：2016-11-16
申请人： Xilinx, Inc.
发明人： HEARNE, Catherine , UPADHYAYA, Parag , GEARY, Kevin
IPC分类号： H03K5/135 , H03K5/00
CPC分类号： H03K5/135 , H03K2005/00052 , H03K2005/00058
摘要： A phase interpolator implemented in an integrated circuit to generate a clock signal is described. The phase interpolator comprises a plurality of inputs coupled to receive a plurality of clock signals; a plurality of transistor pairs, each transistor pair having a first transistor coupled to a first output node and a second transistor coupled to a second output node, wherein a first clock signal associated with the transistor pair is coupled to a gate of the first transistor and an inverted first clock signal associated with the transistor pair is coupled to a gate of the second transistor; a first active inductor load coupled to the first output node; and a second active inductor load coupled to the second output node.

5. 发明公开

EP3353608A1 CALIBRATION OF DYNAMIC ERROR IN HIGH RESOLUTION DIGITAL-TO-TIME CONVERTERS 审中-公开
公开(公告)号：EP3353608A1
公开(公告)日：2018-08-01
申请号：EP16758049.7
申请日：2016-08-22
申请人： Intel IP Corporation
发明人： RAVI, Ashoke , DEGANI, Ofir , BANIN, Rotem , BEN-BASSAT, Assaf
IPC分类号： G04F10/00 , H03K5/135 , H03M1/10 , H03M1/82
CPC分类号： H04L7/042 , G04F10/005 , H03K5/135 , H03M1/1061 , H03M1/82 , H04B1/0475 , H04L7/0054
摘要： A calibration system operates to calibrate or correct a digital-to-time converter (DTC) that comprises a detector component and a distortion correction component. The DTC can receive one or more signals and a digital code to generate a modulation signal by controlling an offset of the one or more signals based on the digital code. The detector component can comprise a TDC or another DTC that operates to measure a dynamic behavior in response to detecting nonlinearities of the modulation signal. The distortion correction component can generate a set of distortion data that removes the dynamic behavior from an output of the DTC based on the measurement.

6. 发明公开

EP3327929A2 RC OSCILLATOR, MOTOR-DRIVEN INTEGRATED CIRCUIT, AND MOTOR DEVICE 审中-公开
公开(公告)号：EP3327929A2
公开(公告)日：2018-05-30
申请号：EP17199949.3
申请日：2017-11-03
申请人： Johnson Electric S.A.
发明人： Sun, Chiping , Wong, Ken , Guo, Huimin , Lai, Yat Tung , Huang, Shujuan
IPC分类号： H03B5/04 , H03B5/26
CPC分类号： H02P6/17 , H02P27/08 , H03B5/04 , H03B5/06 , H03B5/24 , H03B5/26 , H03K5/135
摘要： A RC oscillator (301) comprises a resistor unit (310). The resistor unit (310) can comprise at least one set of compensation resistor (312). Each set of compensation resistor (312) comprises a positive temperature coefficient resistor (Rl) and a negative temperature coefficient resistor (R2) coupled in series with the positive temperature coefficient resistor (Rl).

7. 发明授权

EP2959582B8 STATE MACHINE FOR LOW-NOISE CLOCKING OF HIGH FREQUENCY CLOCK 有权转让
公开(公告)号：EP2959582B8
公开(公告)日：2018-05-02
申请号：EP14754976.0
申请日：2014-02-06
申请人： Advanced Micro Devices, Inc.
发明人： KOMMRUSCH, Steven, J. , JUSUFOVIC, Zihno
IPC分类号： H03K5/15 , H03K19/177 , G06F1/10 , H03K5/135
CPC分类号： H03K21/023 , G06F1/10 , H03K5/135 , H03K19/00346
摘要： Methods, apparatus, and fabrication techniques relating to management of noise arising from capacitance in a clock tree of an integrated circuit. In some embodiments, the methods comprise receiving a signal to adjust a clock having a first rate to a second rate; and ramping, in response to receiving the signal, the clock from the first rate to the second rate, wherein the ramping comprises changing the frequency of the clock to at least one third rate between the first and second rates.

8. 发明公开

EP3226231A1 GATE DRIVE CIRCUIT AND DISPLAY APPARATUS 有权
标题翻译：门驱动电路和显示装置
公开(公告)号：EP3226231A1
公开(公告)日：2017-10-04
申请号：EP15777598.2
申请日：2015-03-13
申请人： BOE Technology Group Co., Ltd.
发明人： MA, Zhanjie
IPC分类号： G09G3/32
CPC分类号： G09G3/3291 , G09G3/3225 , G09G3/3266 , G09G2310/0286 , G09G2310/0289 , G09G2310/08 , G11C19/28 , H03K5/00 , H03K5/135 , H03K5/1506
摘要： An embodiment of the present invention discloses a gate drive circuit comprising several stages of unit circuits, wherein each unit circuit comprises: a high level terminal, a low level terminal, a first clock terminal, a second clock terminal, a gate output terminal, a logic turn-on input terminal, a logic turn-on output terminal, a control module, a first gating module and a second gating module. An embodiment of the present invention also provides a display device comprising the gate drive circuit. A gate drive circuit with interlaced output is realized, ensuring no suspended state in time sequence between interlaced lines, while maintaining an original dual time sequence (i.e., eliminating suspended state between interlaced lines, and ensuring a stable output of the shifting register).
摘要翻译：本发明实施例公开了一种包括多级单元电路的栅极驱动电路，其中每个单元电路包括：高电平端，低电平端，第一时钟端，第二时钟端，栅极输出端，逻辑导通输入端，逻辑导通输出端，控制模块，第一门控模块和第二门控模块。本发明的实施例还提供了一种包括栅极驱动电路的显示装置。实现了具有隔行输出的栅极驱动电路，在保持原始双时序（即，消除隔行线之间的暂停状态，并确保移位寄存器的稳定输出）的同时，确保隔行线之间不存在按时间顺序的暂停状态。

9. 发明公开

EP3152834A1 IMPROVING LINEARITY OF PHASE INTERPOLATORS BY COMBINING CURRENT CODING AND SIZE CODING 审中-公开
标题翻译：改善PHASEINTERPOLATOREN的线性按组合电力法规和尺寸编码
公开(公告)号：EP3152834A1
公开(公告)日：2017-04-12
申请号：EP15726448.2
申请日：2015-05-13
申请人： QUALCOMM Incorporated
发明人： SUN, Li , ZHU, Zhi , KONG, Xiaohua , ARCUDIA, Kenneth Luis , CHEN, Zhiqin
IPC分类号： H03K5/135
CPC分类号： H04L7/0331 , H03K5/135 , H03K2005/00065 , H03L7/099
摘要： A phase interpolator, including: a first portion including a first plurality of branches and a plurality of tail current sources, each branch including a differential pair of transistors, source terminals of the differential pair of transistors connect to form a source node, wherein each tail current source couples to one of the source nodes, and wherein the differential pair of transistors and the corresponding tail current source are configured in a current coding scheme; a second portion including a second plurality of branches and a fixed current source coupled to the second plurality of branches, each branch of the second plurality of branches including a second plurality of differential pairs of transistors and a plurality of switches configured in a size coding scheme; wherein the first portion and the second portion are coupled to each other and to a pair of load resistors.
摘要翻译：相位内插器，包括：包括分支的第一多个和的尾电流源复数，每个分支包含一个差分对晶体管的第一部分，所述差分对晶体管的源极端子连接，以形成源节点，worin每个尾电流源耦合到所述源节点中的一个，和worin所述差分对晶体管的和对应的尾电流源被配置成在当前的编码方案; 的第二部分，其包括分支的第二多个和耦合到分支的第二多个，分支包括晶体管的差分对的第二多个，并在尺寸编码方案配置开关的多个第二多个的每个分支固定电流源 ; worin所述第一部分和所述第二部分被连接到彼此和一对负载电阻器。

10. 发明授权

EP2666239B1 LOW-POWER OSCILLATOR 有权
标题翻译：具有低功耗振荡器
公开(公告)号：EP2666239B1
公开(公告)日：2015-11-18
申请号：EP12702067.5
申请日：2012-01-19
申请人： Nordic Semiconductor ASA
发明人： BRUSET, Ola , VEDAL, Tor Øyvind
IPC分类号： H03K5/135 , G06F1/08
CPC分类号： H03L7/24 , G06F1/08 , H03B5/20 , H03B5/32 , H03B2201/025 , H03K5/135

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式