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1. 发明授权

EP2453618B1 POWER REDUCTION IN SWITCHED-CURRENT LINE-DRIVERS 有权
标题翻译：电源功率减小交换线路DRIVERS
公开(公告)号：EP2453618B1
公开(公告)日：2016-09-14
申请号：EP11188114.0
申请日：2011-11-07
申请人： NXP B.V.
发明人： den Besten, Gerrit
IPC分类号： H04L25/02
CPC分类号： H04L25/0272 , H04L25/0264

2. 发明授权

EP1940026B1 Method and apparatus for recognizing a change-of-state in communication signals of electronic circuits 有权
标题翻译：用于检测在电子电路的通信信号的状态变化的方法和装置
公开(公告)号：EP1940026B1
公开(公告)日：2016-07-27
申请号：EP07123552.7
申请日：2007-12-19
申请人： GENERAL ELECTRIC COMPANY
发明人： Jaffer, Adil , Finney, Dale , Mao, Zhihong
IPC分类号： H03K5/1252 , H04L25/02 , H03K17/615 , H03K17/795
CPC分类号： H03K5/1252 , H03K17/615 , H03K17/7955 , H04L25/0264

3. 发明公开

EP2833559A3 Compact dual all-outdoor point-to-point microwave radio architecture 审中-公开
标题翻译：紧凑型双点至点微波无线电架构户外
公开(公告)号：EP2833559A3
公开(公告)日：2015-05-27
申请号：EP14178188.0
申请日：2014-07-23
申请人： ZTE (USA), Inc.
发明人： Nguyen, Thanh Hung , Shen, Ying , Kochetkov, Andrey
IPC分类号： H04B7/08
CPC分类号： H04L25/0264 , H04B1/40 , H04B7/06 , H04B7/0682 , H04B7/08 , H04B7/0871 , H04B7/10 , H04L1/06
摘要： An outdoor radio communication system housed in a single enclosure comprises a first transceiver, a second transceiver, a communication interface unit, an RF in-phase transmit combiner, an antenna coupling unit and a receive filter. The first transceiver includes a first receiver and a first transmitter. The second transceiver includes a second receiver and a second transmitter. The two transceivers are communicatively coupled with the communication interface unit. The RF in-phase transmit combiner, communicatively coupled to the first transmitter and the second transmitter, receives a phase-aligned RF signal from each transmitter, to create a third RF signal with enhanced signal gain. The two phase-aligned RF signals originate from the same source in the communication interface unit. The antenna coupling unit is communicatively coupled to the RF in-phase transmit combiner and the first receiver, and the receive filter is communicatively coupled to the second receiver.

4. 发明公开

EP2866348A1 System and method of clock generation in high speed serial communication 审中-公开
标题翻译：系统与Verfahren zur Takterzeugung bei serieller Hochgeschwindigkeitskommunikation
公开(公告)号：EP2866348A1
公开(公告)日：2015-04-29
申请号：EP14188712.5
申请日：2014-10-13
申请人： Analog Devices Global
发明人： Elliott, Michael R. , Jeffries, Brad P. , Keane, Michael D. , Mansson, Johan H. , Petersson, Axel Zafra
IPC分类号： H03L7/081 , H03L7/097 , H04L25/02
CPC分类号： H03K17/16 , H03L7/0812 , H03L7/097 , H04L25/0264
摘要： A transmission system may include an oscillator (110), a serializer (120), and a driver (130). The oscillator (110) may generate at least two clock signals (I,Q). The serializer (120) may modulate a plurality of data streams (S1,S2) based upon the at least two clock signals (I,Q) and a plurality of channels of data (D1,D2). The driver (130) may receive and combine the plurality of data streams into a single output data stream, wherein the single output data stream has a clock frequency higher than frequency of each of the at least two clock signals.
摘要翻译：传输系统可以包括振荡器（110），串行器（120）和驱动器（130）。振荡器（110）可以产生至少两个时钟信号（I，Q）。串行器（120）可以基于至少两个时钟信号（I，Q）和多个数据通道（D1，D2）来调制多个数据流（S1，S2）。驱动器（130）可以将多个数据流接收并组合成单个输出数据流，其中单个输出数据流的时钟频率高于至少两个时钟信号中的每一个的频率。

5. 发明公开

EP2809048A1 TRANSMISSION METHOD, TRANSMISSION DEVICE, TRANSMISSION PROGRAM, AND TRANSMISSION SYSTEM 有权
标题翻译： ÜBERTRAGUNGSVERFAHREN，ÜBERTRAGUNGSVORRICHTUNG，ÜBERTRAGUNGSPROGRAMMUNDÜBERTRAGUNGSSYSTEM
公开(公告)号：EP2809048A1
公开(公告)日：2014-12-03
申请号：EP13741463.7
申请日：2013-01-11
申请人： NEC Infrontia Corporation
发明人： NAGASE, Tomohiro
IPC分类号： H04L29/08 , H04L5/16
CPC分类号： H03G3/20 , H04L1/0007 , H04L1/1692 , H04L1/1858 , H04L1/189 , H04L5/16 , H04L25/0264 , H04L25/03885 , H04L43/0864
摘要： To keep communication even if a distance between transmission devices is farther and a transmission distance therebetween is longer.
A transmission device for alternately performing transmission and reception to/from a communication destination transmission device transmits transmit data to the communication destination transmission device. It receives return data transmitted by the communication destination transmission device after the transmit data reaches the communication destination transmission device. A predetermined period of time is assumed as one time unit, one transmission of transmit data and one reception of return data are tried within the one time unit, and when it is determined that one transmission of transmit data and one reception of return data do not fall within the one time unit, the transmission device is controlled such that N number of transmit data are continuously transmitted and then N number of return data are continuously received within N (N is an integer of two or more) time units.
摘要翻译：为了保持通信，即使传输设备之间的距离更远，并且其间的传输距离更长。用于向/从通信目的地发送装置交替地进行发送的发送装置向通信目的地发送装置发送发送数据。在发送数据到达通信目的地发送装置之后，接收由通信目的地发送装置发送的返回数据。假设一个预定的时间段是一个时间单位，在一个时间单位内尝试发送数据的一次发送和返回数据的一次接收，并且当确定发送数据的一次发送和一个接收返回数据不是控制在一个时间单位内，发送装置被控制成使得N个发送数据被连续发送，然后在N（N是两个或更多个的整数）时间单位内连续接收N个返回数据。

6. 发明公开

EP2680521A2 Single wire signal regeneration transmitting apparatus and method and serially connected single wire signal regeneration transmitting apparatuses 有权
标题翻译： EinadrigeSignalwiederherstellungsübertragungsvorrichtungund Verfahren und seriell verbundene einadrigeSignalwiederherstellungsübertragungsvorrichtungen
公开(公告)号：EP2680521A2
公开(公告)日：2014-01-01
申请号：EP13150357.5
申请日：2013-01-07
申请人： Macroblock, Inc.
发明人： Hsieh, Shun-Ching
IPC分类号： H04L25/24 , H04L5/24 , H04L25/02 , H04J3/07 , H04L7/04
CPC分类号： H04L29/02 , H04J3/07 , H04L5/24 , H04L25/0264 , H04L25/245 , H04L25/49 , H04L2007/045
摘要： A single wire signal regeneration transmitting apparatus receives a serial packet including a plurality of signal segments, and each of the signal segments includes a data field and a stuff time symbol. Each of the data fields, which is followed by each of the stuff time symbols, includes multiple logic 0/1 signal symbols, with accumulated numbers of the logic 0/1 signal symbols in each of the data fields being the same. The single wire signal regeneration transmitting apparatus is adapted to process the serial packet to sequentially output the signal segments, and after the single wire signal regeneration transmitting apparatus outputs the data field from a previously received signal segment, the single wire signal regeneration transmitting apparatus continues outputting the stuff time symbol until starting to process a next received signal segment received subsequent to a currently received signal segment in the received serial package.
摘要翻译：单线信号再生发送装置接收包括多个信号段的串行分组，并且每个信号段包括数据字段和填充时间符号。每个填充时间符号之后的每个数据字段包括多个逻辑0/1信号符号，每个数据字段中的逻辑0/1信号符号的累加数相同。单线信号再生发送装置适于处理串行分组以顺序地输出信号段，并且在单线信号再生发送装置从先前接收到的信号段输出数据字段之后，单线信号再生发送装置继续输出填充时间符号，直到开始处理在所接收的串行包中的当前接收到的信号段之后接收的下一个接收信号段。

7. 发明授权

EP1961261B1 CONTROL CIRCUITRY FOR PROVIDING AN INTERFACE BETWEEN CONNECTABLE TERMINAL AND PERIPHERAL DEVICE CIRCUITRY 有权
标题翻译：控制电路部，连接终端和外围设备电路之间的接口。
公开(公告)号：EP1961261B1
公开(公告)日：2013-03-13
申请号：EP06841041.4
申请日：2006-12-15
申请人： Nokia Corporation
发明人： LINDLAR, Heribert , SATTLER, Stefan
IPC分类号： H04L25/02 , H04W52/02
CPC分类号： H04W52/0229 , H04L25/0264 , Y02D70/00
摘要： Control circuitry for providing an interface between connectable terminal and peripheral device circuitry, wherein the peripheral device circuitry comprises a bus line for transferring data and power between the peripheral device circuitry and the terminal device circuitry; a charge storage device arranged to receive power from the terminal device circuitry over the bus line and to supply the power to the control circuitry; wherein the control circuitry is operable to connect the charge storage device to the bus line to receive power for storage in response to the terminal device circuitry transmitting a first data value represented by a higher voltage level and to disconnect the charge storage device from the bus line in response to the terminal device circuitry transmitting a second data value represented by a lower voltage level, to prevent the charge storage device from discharging over the bus.

8. 发明公开

EP2555125A1 A device for interfacing to a bidirectional bus line of the I2C type 有权
标题翻译：公司简体中文繁体中文简体中文
公开(公告)号：EP2555125A1
公开(公告)日：2013-02-06
申请号：EP12178880.6
申请日：2012-08-01
申请人： Indesit Company S.p.A.
发明人： Burzella, Luciano
IPC分类号： G06F13/40 , H03K19/00
CPC分类号： G06F13/4045 , G06F2213/0016 , H04L25/0264
摘要： A device for interfacing to a bidirectional bus line of the IIC type, comprising: a first pin (IIC_uC) connected to a port of a device adapted to communicate through an IIC bus, and normally kept at a first high logic potential (V_uC High); a second pin (IIC_Bus) connected to an IIC bus, and normally kept at a second high logic potential (V_Bus High), first switching means (Q25) having an output (Q25_e) directly connected to said second pin (IIC_Bus), a control input (Q25_b) connected to said second pin (IIC_Bus) through a first polarization resistor (R42), and a first terminal (Q25_c) connected to a first reference potential (0), and drive means (Q20) connected to the control input (Q25_b) of said first switching means (Q25), adapted to set said first switching means (Q25) to conduction when said first pin (IIC_uC) is set to a low logic level (V_uC Low).
摘要翻译：一种用于与IIC类型的双向总线接口的设备，包括：连接到适于通过IIC总线通信并且通常保持在第一高逻辑电位（V_uC High）的设备的端口的第一引脚（IIC_uC） ; 连接到IIC总线并且通常保持在第二高逻辑电位（V_Bus High）的第二引脚（IIC_Bus），具有直接连接到所述第二引脚（IIC_Bus）的输出（Q25_e）的第一开关装置（Q25），控制通过第一偏振电阻器（R42）连接到所述第二引脚（IIC_Bus）的输入端（Q25_b）和连接到第一参考电位（0）的第一端子（Q25_c）以及连接到控制输入端的驱动装置（Q20）所述第一开关装置（Q25）的所述第一开关装置（Q25_b）适于将所述第一开关装置（Q25）设置为导通，当所述第一引脚（IIC_uC）被设置为低逻辑电平（V_uC低）时。

9. 发明公开

EP2449678A2 TECHNIQUES FOR ADJUSTING CLOCK SIGNALS TO COMPENSATE FOR NOISE 审中-公开
标题翻译：过程设置时钟信号噪声补偿
公开(公告)号：EP2449678A2
公开(公告)日：2012-05-09
申请号：EP10800210.6
申请日：2010-05-31
申请人： Rambus Inc.
发明人： ZERBE, Jared , BATRA, Pradeep , LEIBOWITZ, Brian
IPC分类号： H03K19/0175 , H04L25/02 , H03K5/1252
CPC分类号： H04L25/0264 , G06F1/10 , H03K5/1252
摘要： A first integrated circuit (IC) has an adjustable delay circuit and a first interface circuit. A first clock signal is provided to the adjustable delay circuit to produce a delayed clock signal provided to the first interface circuit. A second IC has a supply voltage sense circuit and a second interface circuit that transfers data with the first IC. The supply voltage sense circuit provides a noise signal to the first IC that is indicative of noise in a supply voltage of the second IC. The adjustable delay circuit adjusts a delay of the delayed clock signal based on the noise signal. In other embodiments, edge-colored clock signals reduce the effects of high frequency jitter in the transmission of data between integrated circuits (ICs) by making the high frequency jitter common between the ICs. In other embodiments, a supply voltage is used to generate clocks signals on multiple ICs.

10. 发明授权

EP2118760B1 A BI-DIRECTIONAL INTERFACE CIRCUIT HAVING A SWITCHABLE CURRENT-SOURCE BIAS 有权
标题翻译：可切换电流源BIAS双向接口电路
公开(公告)号：EP2118760B1
公开(公告)日：2012-02-22
申请号：EP08730945.6
申请日：2008-02-28
申请人： Rambus Inc.
发明人： BEST, Scott C.
IPC分类号： G06F13/38 , H04B15/00 , H04L5/14 , H04L5/16
CPC分类号： H04L25/0264 , G06F13/4072 , H04L5/1469 , H04L5/16
摘要： A bi-directional interface circuit includes a transmitter portion, a receiver portion, a current source bias circuit, and a switch. When the interface circuit is transmitting data, the switch steers the bias current generated by the current source bias circuit to the transmitter portion of the interface. When the interface is receiving data, the switch steers the bias current to the receiver portion of the interface. Thus, the current-source bias circuit is kept on regardless of whether the interface is transmitting or receiving data. Because the current-source bias circuit is not turned on and off, the switching noise generated when the interface transitions between transmitting and receiving operations is eliminated or reduced. Consequently, any dead time inserted for such a transition can be minimized, and the effective bandwidth of the interface is increased.

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