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11. 发明公开

EP1979937A2 METHODS OF FORMING FIELD EFFECT TRANSISTORS AND METHODS OF FORMING INTEGRATED CIRCUITRY COMPRISING A TRANSISTOR GATE ARRAY AND CIRCUITRY PERIPHERAL TO THE GATE ARRAY 有权
标题翻译：法成型FELDEFFFEKTTRANSISTOREN AND METHOD FOR制造集成电路用FOR GATE对准晶体管栅极校准和电路PERIPHERRIEGERÄT
公开(公告)号：EP1979937A2
公开(公告)日：2008-10-15
申请号：EP07749192.6
申请日：2007-01-23
申请人： Micron Technology, Inc.
发明人： KIM, Young Pil , PAREKH, Kunal, R.
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238 , H01L21/10
CPC分类号： H01L21/823462 , H01L21/823456 , H01L21/823487 , H01L29/4236 , H01L29/42376 , H01L29/66621
摘要： The invention includes methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates. In one implementation, a method of forming a field effect transistor includes forming masking material over semiconductive material of a substrate. A trench is formed through the masking material and into the semiconductive material. Gate dielectric material is formed within the trench in the semiconductive material. Gate material is deposited within the trench in the masking material and within the trench in the semiconductive material over the gate dielectric material. Source/drain regions are formed. Other aspects and implementations are contemplated.

12. 发明公开

EP1575093A3 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：EP1575093A3
公开(公告)日：2006-03-01
申请号：EP05250878.5
申请日：2005-02-16
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Ohta, Sougo
IPC分类号： H01L27/146
CPC分类号： H01L27/146 , H01L21/823443 , H01L21/823456 , H01L21/823468 , H01L21/823475
摘要： A semiconductor device includes a semiconductor substrate (100), an isolation film (4) that is provided in one principal surface of the semiconductor substrate, wiring (1) that is arranged on the isolation film, a diffusion layer (16) that is formed inside the semiconductor substrate and located in the vicinity of the isolation film, and an insulating film (8) that covers the diffusion layer (16) over the one principal surface of the semiconductor substrate (100). The insulating film further covers a portion of the isolation film (4) near to the diffusion layer and comes into contact with the side of the wiring (1) near to the diffusion layer.

13. 发明公开

EP1612861A1 SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：EP1612861A1
公开(公告)日：2006-01-04
申请号：EP03816642.7
申请日：2003-04-10
申请人： FUJITSU LIMITED
发明人： EMA, Taiji, c/o FUJITSU LIMITED , KOJIMA, Hideyuki, c/o FUJITSU LIMITED , ANEZAKI, Toru, c/o FUJITSU LIMITED
IPC分类号： H01L27/088
CPC分类号： H01L21/823412 , H01L21/823456 , H01L21/823493 , H01L21/823807 , H01L21/823857 , H01L21/823878 , H01L21/823892
摘要： Multiple kinds of transistors exhibiting desired characteristics are manufactured in fewer processes. A semiconductor device includes an isolation region reaching a first depth, first and second wells of first conductivity type, a first transistor formed in the first well and having a gate insulating film of a first thickness, and a second transistor formed in the second well and having a gate insulating film of a second thickness less than the first thickness. The first well has a first impurity concentration distribution having an extremum maximum value only at the depth equal to or greater than the first depth. The second well has a second impurity concentration distribution which is superposition of the first impurity concentration distribution, and another impurity concentration distribution which shows an extremum maximum value at a second depth less than the first depth, the superposition shows also an extremum maximum value at the second depth.
摘要翻译：显示期望特性的多种晶体管以较少的工艺制造。一种半导体器件包括：达到第一深度的隔离区，第一导电类型的第一和第二阱，形成在第一阱中并具有第一厚度的栅极绝缘膜的第一晶体管以及形成在第二阱中的第二晶体管，以及具有小于第一厚度的第二厚度的栅极绝缘膜。第一阱具有仅在等于或大于第一深度的深度处具有极值最大值的第一杂质浓度分布。第二阱具有第一杂质浓度分布的叠加的第二杂质浓度分布和在小于第一深度的第二深度处示出极值最大值的另一个杂质浓度分布，叠加还显示在第二阱处的极值最大值第二深度。

14. 发明授权

EP0731504B1 Process for the manufacturing of integrated circuits comprising lateral low-voltage and high-voltage DMOS-technology power devices and non-volatile memory cells 失效
标题翻译：一种用于制备具有高电压和低电压横向DMOS-技术功率器件和非易失性存储器单元intergrierten电路处理
公开(公告)号：EP0731504B1
公开(公告)日：2002-11-27
申请号：EP95830088.1
申请日：1995-03-09
申请人： STMicroelectronics S.r.l.
发明人： Contiero, Claudio , Galbiati, Paola , Palmieri, Michele
IPC分类号： H01L21/8234 , H01L21/336 , H01L21/8247 , H01L21/265 , H01L27/06 , H01L29/78
CPC分类号： H01L29/66659 , H01L21/823456 , H01L27/11526 , H01L27/11546 , H01L29/0847 , H01L29/66674 , H01L29/7816
摘要： A process for the manufacturing of an integrated circuit comprising lateral DMOS-technology power devices and non-volatile memory cells provides for: forming respective laterally displaced isolated semiconductor regions (R1,R2,R6), electrically insulated from each other and from a common semiconductor substrate (1), inside which the devices will be formed; forming conductive insulated gate regions (33,34,37) for the lateral DMOS-technology power devices and for the memory cells over the respective isolated semiconductor regions (R1,R2,R6); inside the isolated semiconductor regions (R1,R2) for the lateral DMOS-technology power devices, forming deep body regions (25,26) aligned with edges of the insulated gate regions (33,34), and channel regions (29,30) extending under the insulated gate regions (33,34). The deep body regions (25,26) are formed by means of a first implantation of a first dopant in a direction substantially orthogonal to a top surface of the integrated circuit, performed with an energy and with a dopant dose such that the concentration of the first dopant has a peak located at a prescribed distance from the surface of the isolated semiconductor regions (R1,R2). The channel regions (29,30) are formed by means of a second implantation of a second dopant along directions tilted of a prescribed angle with respect to a direction orthogonal to a top surface of the integrated circuit, in a dose and with an energy such that said channel regions (29,30) are formed directly after the implantation of the second dopant without performing a thermal diffusion at a high temperature of the second dopant.

15. 发明公开

EP0859401A3 Halbleiterkörper mit selbstjustierender Strukture 失效
标题翻译：半导体主体具有自动调心Strukture
公开(公告)号：EP0859401A3
公开(公告)日：1999-12-15
申请号：EP98100724.8
申请日：1998-01-16
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Stecher, Mattihas, Dr. , Peri, Hermann
IPC分类号： H01L21/033 , H01L21/336 , H01L21/8249
CPC分类号： H01L21/76897 , H01L21/823456 , H01L29/7809
摘要： Es wird ein Verfahren zum Herstellen eines Halbleiterkörpers mit einem eine selbstjustierende Struktur aufweisenden ersten Bereich (A) und einem übrigen zweiten Bereich (B) beschrieben. Die im ersten Bereich (A) auf einer Halbleiterschicht (24) sitzende Isolationsschicht (26) wird im zweiten Bereich (B) mittels Fototechnik und anschließendem Ätzvorgang vollständig entfernt. Anschließend oder gleichzeitig wird im ersten Bereich (A) die erforderliche Strukturierung der Halbleiterschicht (24) und der Isolationsschicht (26) vorgenommen. Vorteile: Höhere Packungsdichte im übrigen Bereich (B) des Halbleiterkörpers.

16. 发明公开

EP0859401A2 Halbleiterkörper mit selbstjustierender Strukture 失效
标题翻译： Halbleiterkörpermit selbstjustierender Struktur
公开(公告)号：EP0859401A2
公开(公告)日：1998-08-19
申请号：EP98100724.8
申请日：1998-01-16
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Stecher, Mattihas, Dr. , Peri, Hermann
IPC分类号： H01L21/033 , H01L21/336 , H01L21/8249
CPC分类号： H01L21/76897 , H01L21/823456 , H01L29/7809
摘要： Es wird ein Verfahren zum Herstellen eines Halbleiterkörpers mit einem eine selbstjustierende Struktur aufweisenden ersten Bereich (A) und einem übrigen zweiten Bereich (B) beschrieben. Die im ersten Bereich (A) auf einer Halbleiterschicht (24) sitzende Isolationsschicht (26) wird im zweiten Bereich (B) mittels Fototechnik und anschließendem Ätzvorgang vollständig entfernt. Anschließend oder gleichzeitig wird im ersten Bereich (A) die erforderliche Strukturierung der Halbleiterschicht (24) und der Isolationsschicht (26) vorgenommen. Vorteile: Höhere Packungsdichte im übrigen Bereich (B) des Halbleiterkörpers.
摘要翻译：在制造具有第一自对准结构区域（A）和剩余的第二区域（B）的半导体本体时，包括在主体前表面上施加和构造氧化物层（22），然后施加半导体层）和绝缘层（26），所述方法还包括：（a）通过光电技术和随后的蚀刻来构造绝缘层（26），以将其完全从第二区域（B）移除，同时将其留在第一区（A）的最少部分; 和（b）使用光电技术和随后的蚀刻来构造半导体层（24）和由绝缘层（26）和半导体层（24）组成的部分。优选地，多个DMOSFET集成在第一区域（A）中。

17. 发明公开

EP0355951A3 Semiconductor device with memory cell region and a peripheral circuit and method of manufacturing the same 失效
标题翻译：具有存储单元区域的半导体器件和外围电路及其制造方法
公开(公告)号：EP0355951A3
公开(公告)日：1992-02-19
申请号：EP89305217.5
申请日：1989-05-23
申请人： SEIKO EPSON CORPORATION
发明人： Maruo, Yukata
IPC分类号： H01L27/115 , H01L21/82 , H01L29/08 , G11C17/00
CPC分类号： H01L27/0925 , H01L21/823456 , H01L27/105 , Y10S257/90
摘要： A semi-conductor memory comprises a memory cell region and a peripheral circuit. The memory cell region includes a plurality of memory transistors (Qn, Qm) of a first conductivity type and a plurality of select transistors (Qn, Qw) of the first conductivity type. The peripheral circuit includes transistors (Qn) of the first conductivity type and also transistors (Qp) of a second conductivity type. The transistors of the first conductivity type each have a first off-set region (21, 121) defined by a low concentration impurity region having a substantially flat surface, the first off-set region being formed in a substrate (10, 110) adjacent to a first gate electrode (20, 120). The transistors of the second conductivity type each have a thick insulating film (15) provided adjacent to a second gate electrode (16) with a part thereof buried in the substrate, and a second off-set region (17) defined by a low concentration impurity region provided in a portion of the substrate under the thick insulating film.

18. 发明授权

EP0083783B1 Fabrication method for integrated circuit structures including field effect transistors of sub-micrometer gate length, and integrated circuit structure fabricated by this method 失效
标题翻译：用于集成电路结构的制造方法，其中包括小型门长度的场效应晶体管和本方法制成的集成电路结构
公开(公告)号：EP0083783B1
公开(公告)日：1987-11-11
申请号：EP82111970.8
申请日：1982-12-27
申请人： International Business Machines Corporation
发明人： de la Moneda, Francisco Homero , Dockerty, Robert Charles
IPC分类号： H01L21/82 , H01L21/76 , H01L27/08
CPC分类号： H01L21/76216 , H01L21/28132 , H01L21/823456 , H01L27/088 , Y10S438/947

19. 发明公开

EP4376088A1 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：EP4376088A1
公开(公告)日：2024-05-29
申请号：EP23191480.5
申请日：2023-08-15
申请人： Samsung Electronics Co., Ltd.
发明人： YOO, Hyumin , PARK, Beomjin , KANG, Myung Gil , KIM, Dongwon , KIM, Younggwon
IPC分类号： H01L29/06 , H01L27/088 , H01L29/423 , H01L21/336 , H01L29/775 , H01L29/78 , H01L21/285
CPC分类号： H01L29/66545 , H01L29/42392 , B82Y10/00 , H01L29/66439 , H01L29/0673 , H01L29/775 , H01L29/7848 , H01L27/088 , H01L29/0847 , H01L29/165 , H01L29/41766 , H01L29/42376 , H01L21/28518 , H01L29/78696 , H01L21/823456 , H01L21/823475 , H01L21/823418
摘要： Disclosed is a semiconductor device comprising a substrate including an active pattern, a channel pattern on the active pattern and including semiconductor patterns spaced apart from and vertically stacked on each other, a source/drain pattern connected to the semiconductor patterns having a p-type, a gate electrode on the semiconductor patterns and including inner electrodes between neighboring semiconductor patterns and an outer electrode on an uppermost semiconductor pattern, and a gate dielectric layer between the gate electrode and the semiconductor patterns and including an inner gate dielectric layer adjacent to the inner electrode and an outer gate dielectric layer that extends from bottom to lateral surfaces of the outer electrode. The outer electrode and the outer gate dielectric layer have an inverted T shape.

20. 发明公开

EP4369412A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 审中-实审
公开(公告)号：EP4369412A1
公开(公告)日：2024-05-15
申请号：EP23156290.1
申请日：2023-02-13
申请人： United Microelectronics Corp.
发明人： CHANG, Chu-Chun , VERMA, Purakh Raj , LIN, Chia-Huei , YANG, Kuo-Yuh
IPC分类号： H01L29/423 , H01L21/8234 , H01L29/78 , H01L21/336 , H01L21/28
CPC分类号： H01L29/66545 , H01L29/42376 , H01L29/78 , H01L29/66575 , H01L21/823456 , H01L21/28114 , H01L27/088
摘要： A method for fabricating semiconductor device includes first providing a substrate having a core region, a LNA region, a I/O region, and a PA region, forming a first gate structure on the LNA region, a second gate structure on the PA region, a third gate structure on the core region, and a fourth gate structure on the I/O region, forming an interlayer dielectric (ILD) layer on the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure, and then forming a first hard mask on the first gate structure and a second hard mask on the second gate structure. Preferably, a width of the first hard mask is greater than a width of the first gate structure.

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