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11. 发明公开

EP1612861A1 SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：EP1612861A1
公开(公告)日：2006-01-04
申请号：EP03816642.7
申请日：2003-04-10
申请人： FUJITSU LIMITED
发明人： EMA, Taiji, c/o FUJITSU LIMITED , KOJIMA, Hideyuki, c/o FUJITSU LIMITED , ANEZAKI, Toru, c/o FUJITSU LIMITED
IPC分类号： H01L27/088
CPC分类号： H01L21/823412 , H01L21/823456 , H01L21/823493 , H01L21/823807 , H01L21/823857 , H01L21/823878 , H01L21/823892
摘要： Multiple kinds of transistors exhibiting desired characteristics are manufactured in fewer processes. A semiconductor device includes an isolation region reaching a first depth, first and second wells of first conductivity type, a first transistor formed in the first well and having a gate insulating film of a first thickness, and a second transistor formed in the second well and having a gate insulating film of a second thickness less than the first thickness. The first well has a first impurity concentration distribution having an extremum maximum value only at the depth equal to or greater than the first depth. The second well has a second impurity concentration distribution which is superposition of the first impurity concentration distribution, and another impurity concentration distribution which shows an extremum maximum value at a second depth less than the first depth, the superposition shows also an extremum maximum value at the second depth.
摘要翻译：显示期望特性的多种晶体管以较少的工艺制造。一种半导体器件包括：达到第一深度的隔离区，第一导电类型的第一和第二阱，形成在第一阱中并具有第一厚度的栅极绝缘膜的第一晶体管以及形成在第二阱中的第二晶体管，以及具有小于第一厚度的第二厚度的栅极绝缘膜。第一阱具有仅在等于或大于第一深度的深度处具有极值最大值的第一杂质浓度分布。第二阱具有第一杂质浓度分布的叠加的第二杂质浓度分布和在小于第一深度的第二深度处示出极值最大值的另一个杂质浓度分布，叠加还显示在第二阱处的极值最大值第二深度。

12. 发明授权

EP0731504B1 Process for the manufacturing of integrated circuits comprising lateral low-voltage and high-voltage DMOS-technology power devices and non-volatile memory cells 失效
标题翻译：一种用于制备具有高电压和低电压横向DMOS-技术功率器件和非易失性存储器单元intergrierten电路处理
公开(公告)号：EP0731504B1
公开(公告)日：2002-11-27
申请号：EP95830088.1
申请日：1995-03-09
申请人： STMicroelectronics S.r.l.
发明人： Contiero, Claudio , Galbiati, Paola , Palmieri, Michele
IPC分类号： H01L21/8234 , H01L21/336 , H01L21/8247 , H01L21/265 , H01L27/06 , H01L29/78
CPC分类号： H01L29/66659 , H01L21/823456 , H01L27/11526 , H01L27/11546 , H01L29/0847 , H01L29/66674 , H01L29/7816
摘要： A process for the manufacturing of an integrated circuit comprising lateral DMOS-technology power devices and non-volatile memory cells provides for: forming respective laterally displaced isolated semiconductor regions (R1,R2,R6), electrically insulated from each other and from a common semiconductor substrate (1), inside which the devices will be formed; forming conductive insulated gate regions (33,34,37) for the lateral DMOS-technology power devices and for the memory cells over the respective isolated semiconductor regions (R1,R2,R6); inside the isolated semiconductor regions (R1,R2) for the lateral DMOS-technology power devices, forming deep body regions (25,26) aligned with edges of the insulated gate regions (33,34), and channel regions (29,30) extending under the insulated gate regions (33,34). The deep body regions (25,26) are formed by means of a first implantation of a first dopant in a direction substantially orthogonal to a top surface of the integrated circuit, performed with an energy and with a dopant dose such that the concentration of the first dopant has a peak located at a prescribed distance from the surface of the isolated semiconductor regions (R1,R2). The channel regions (29,30) are formed by means of a second implantation of a second dopant along directions tilted of a prescribed angle with respect to a direction orthogonal to a top surface of the integrated circuit, in a dose and with an energy such that said channel regions (29,30) are formed directly after the implantation of the second dopant without performing a thermal diffusion at a high temperature of the second dopant.

13. 发明公开

EP0859401A3 Halbleiterkörper mit selbstjustierender Strukture 失效
标题翻译：半导体主体具有自动调心Strukture
公开(公告)号：EP0859401A3
公开(公告)日：1999-12-15
申请号：EP98100724.8
申请日：1998-01-16
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Stecher, Mattihas, Dr. , Peri, Hermann
IPC分类号： H01L21/033 , H01L21/336 , H01L21/8249
CPC分类号： H01L21/76897 , H01L21/823456 , H01L29/7809
摘要： Es wird ein Verfahren zum Herstellen eines Halbleiterkörpers mit einem eine selbstjustierende Struktur aufweisenden ersten Bereich (A) und einem übrigen zweiten Bereich (B) beschrieben. Die im ersten Bereich (A) auf einer Halbleiterschicht (24) sitzende Isolationsschicht (26) wird im zweiten Bereich (B) mittels Fototechnik und anschließendem Ätzvorgang vollständig entfernt. Anschließend oder gleichzeitig wird im ersten Bereich (A) die erforderliche Strukturierung der Halbleiterschicht (24) und der Isolationsschicht (26) vorgenommen. Vorteile: Höhere Packungsdichte im übrigen Bereich (B) des Halbleiterkörpers.

14. 发明公开

EP0859401A2 Halbleiterkörper mit selbstjustierender Strukture 失效
标题翻译： Halbleiterkörpermit selbstjustierender Struktur
公开(公告)号：EP0859401A2
公开(公告)日：1998-08-19
申请号：EP98100724.8
申请日：1998-01-16
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Stecher, Mattihas, Dr. , Peri, Hermann
IPC分类号： H01L21/033 , H01L21/336 , H01L21/8249
CPC分类号： H01L21/76897 , H01L21/823456 , H01L29/7809
摘要： Es wird ein Verfahren zum Herstellen eines Halbleiterkörpers mit einem eine selbstjustierende Struktur aufweisenden ersten Bereich (A) und einem übrigen zweiten Bereich (B) beschrieben. Die im ersten Bereich (A) auf einer Halbleiterschicht (24) sitzende Isolationsschicht (26) wird im zweiten Bereich (B) mittels Fototechnik und anschließendem Ätzvorgang vollständig entfernt. Anschließend oder gleichzeitig wird im ersten Bereich (A) die erforderliche Strukturierung der Halbleiterschicht (24) und der Isolationsschicht (26) vorgenommen. Vorteile: Höhere Packungsdichte im übrigen Bereich (B) des Halbleiterkörpers.
摘要翻译：在制造具有第一自对准结构区域（A）和剩余的第二区域（B）的半导体本体时，包括在主体前表面上施加和构造氧化物层（22），然后施加半导体层）和绝缘层（26），所述方法还包括：（a）通过光电技术和随后的蚀刻来构造绝缘层（26），以将其完全从第二区域（B）移除，同时将其留在第一区（A）的最少部分; 和（b）使用光电技术和随后的蚀刻来构造半导体层（24）和由绝缘层（26）和半导体层（24）组成的部分。优选地，多个DMOSFET集成在第一区域（A）中。

15. 发明公开

EP0355951A3 Semiconductor device with memory cell region and a peripheral circuit and method of manufacturing the same 失效
标题翻译：具有存储单元区域的半导体器件和外围电路及其制造方法
公开(公告)号：EP0355951A3
公开(公告)日：1992-02-19
申请号：EP89305217.5
申请日：1989-05-23
申请人： SEIKO EPSON CORPORATION
发明人： Maruo, Yukata
IPC分类号： H01L27/115 , H01L21/82 , H01L29/08 , G11C17/00
CPC分类号： H01L27/0925 , H01L21/823456 , H01L27/105 , Y10S257/90
摘要： A semi-conductor memory comprises a memory cell region and a peripheral circuit. The memory cell region includes a plurality of memory transistors (Qn, Qm) of a first conductivity type and a plurality of select transistors (Qn, Qw) of the first conductivity type. The peripheral circuit includes transistors (Qn) of the first conductivity type and also transistors (Qp) of a second conductivity type. The transistors of the first conductivity type each have a first off-set region (21, 121) defined by a low concentration impurity region having a substantially flat surface, the first off-set region being formed in a substrate (10, 110) adjacent to a first gate electrode (20, 120). The transistors of the second conductivity type each have a thick insulating film (15) provided adjacent to a second gate electrode (16) with a part thereof buried in the substrate, and a second off-set region (17) defined by a low concentration impurity region provided in a portion of the substrate under the thick insulating film.

16. 发明授权

EP0083783B1 Fabrication method for integrated circuit structures including field effect transistors of sub-micrometer gate length, and integrated circuit structure fabricated by this method 失效
标题翻译：用于集成电路结构的制造方法，其中包括小型门长度的场效应晶体管和本方法制成的集成电路结构
公开(公告)号：EP0083783B1
公开(公告)日：1987-11-11
申请号：EP82111970.8
申请日：1982-12-27
申请人： International Business Machines Corporation
发明人： de la Moneda, Francisco Homero , Dockerty, Robert Charles
IPC分类号： H01L21/82 , H01L21/76 , H01L27/08
CPC分类号： H01L21/76216 , H01L21/28132 , H01L21/823456 , H01L27/088 , Y10S438/947

17. 发明授权

EP2434538B1 SEMICONDUCTOR SWITCH DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR SWITCH DEVICE 有权
公开(公告)号：EP2434538B1
公开(公告)日：2018-08-22
申请号：EP10777701.3
申请日：2010-05-14
申请人： Murata Manufacturing Co., Ltd.
发明人： SAIMEI Tsunekazu , KOBAYASHI Kazuya , HIMEDA Koshi , OKUDA Nobuyoshi
IPC分类号： H01L21/338 , H01L21/8232 , H01L27/06 , H01L27/095 , H01L29/812 , H01L29/423 , H01L29/66 , H01L29/20 , H01L21/8234 , H01L27/088
CPC分类号： H01L27/0883 , H01L21/823456 , H01L27/0605 , H01L27/095 , H01L29/20 , H01L29/42316 , H01L29/66863 , H01L29/812
摘要： A semiconductor switch device having an improved distortion characteristic and a method of manufacturing the semiconductor switch device are provided. The semiconductor switch device (1) includes semiconductor elements (E1, D1) formed on a single semiconductor substrate (2) with the provision of recesses (3A, 3B) for the semiconductor elements. The semiconductor element (D1) constitutes a switch circuit. The semiconductor elements (E1, D1) constitute a logic circuit. The semiconductor elements (E1, D1) include respectively gate electrodes (4A, 4B), drain electrodes (6A, 6B), and source electrodes (5A, 5B). The gate electrode (4B) has a rectangular external shape in section. The gate electrode (4A) has a V-like external shape in section.

18. 发明公开

EP3316282A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE PRODUCTION METHOD, AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路器件制造方法和半导体集成电路器件
公开(公告)号：EP3316282A1
公开(公告)日：2018-05-02
申请号：EP16834972.8
申请日：2016-07-26
申请人： Floadia Corporation
发明人： OWADA Fukuo , TANIGUCHI Yasuhiro , KAWASHIMA Yasuhiko , YOSHIDA Shinji , KASAI Hideo , SAKURAI Ryotaro , SHINAGAWA Yutaka , OKUYAMA Kosuke
IPC分类号： H01L21/336 , H01L21/8234 , H01L27/088 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/792 , H01L21/823456 , H01L27/092 , H01L27/11565 , H01L27/11573 , H01L29/42344
摘要： A method for producing semiconductor integrated circuit devices and a semiconductor integrated circuit device produced by the method are provided. In the method, when a first select gate electrode (G2a, G2b) and a second select gate electrode (G3a, G3b) that are independently controllable are formed in a production process, an extra dedicated photomask process for electrically separating the first select gate electrode (G2a, G2b) and the second select gate electrode (G3a, G3b) is not needed in addition to a conventional dedicated photomask process of fabricating a memory circuit region only, thereby achieving reduction in a production cost accordingly.
摘要翻译：提供了一种用于制造半导体集成电路器件的方法以及由该方法制造的半导体集成电路器件。在该方法中，当在制造工艺中形成可独立控制的第一选择栅极电极（G2a，G2b）和第二选择栅极电极（G3a，G3b）时，用于电分离第一选择栅极电极的额外专用光掩模工艺（G2a，G2b）和第二选择栅极电极（G3a，G3b），除了仅制造存储器电路区域的传统专用光掩模工艺之外，因此实现了生产成本的降低。

19. 发明公开

EP3279933A1 INCREASING THICKNESS OF FUNCTIONAL LAYER ACCORDING TO INCREASING RECESS AREA 审中-公开
标题翻译：根据不断增加的入口区域增加功能层的厚度
公开(公告)号：EP3279933A1
公开(公告)日：2018-02-07
申请号：EP17183769.3
申请日：2017-07-28
申请人： Semiconductor Manufacturing International Corporation (Shanghai) , Semiconductor Manufacturing International Corporation (Beijing)
发明人： LI, Yong , XU, Jianhua
IPC分类号： H01L21/8234 , H01L27/088 , H01L21/8238
CPC分类号： H01L27/0924 , H01L21/28556 , H01L21/823431 , H01L21/82345 , H01L21/823456 , H01L21/823821 , H01L21/82385 , H01L27/0886 , H01L29/401 , H01L29/4966 , H01L29/66795 , H01L29/7851
摘要： A method of manufacturing a semiconductor device includes providing a substrate having first and second semiconductor fins, forming an insulating layer on the substrate having first and second recesses exposing a portion of the respective first and second semiconductor fins, forming a gate dielectric layer on the first and second recesses and the exposed portions of the first and second semiconductor fins, forming a first work function adjustment layer on the gate dielectric layer, forming a functional layer on the first function adjustment layer, and forming first and second gates on portions of the functional layer of the respective first and second semiconductor fins. The opening area of the first recess is larger than the opening area of the second recess. The thickness of the functional layer on the first semiconductor fin is greater than the thickness of the functional layer on the second semiconductor fin.
摘要翻译：一种制造半导体器件的方法包括：提供具有第一半导体鳍和第二半导体鳍的衬底;在衬底上形成绝缘层，该绝缘层具有暴露相应第一半导体鳍和第二半导体鳍的一部分的第一凹陷和第二凹陷;在第一半导体鳍上形成栅极介电层以及第二凹陷和第一和第二半导体鳍的暴露部分;在栅极介电层上形成第一功函数调整层;在第一功能调整层上形成功能层;以及在功能的部分上形成第一和第二栅极相应的第一和第二半导体鳍的层。第一凹部的开口面积大于第二凹部的开口面积。第一半导体鳍片上的功能层的厚度大于第二半导体鳍片上的功能层的厚度。

20. 发明公开

EP3208831A1 METHOD FOR PRODUCING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES, AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：制造半导体集成电路器件的方法和半导体集成电路器件
公开(公告)号：EP3208831A1
公开(公告)日：2017-08-23
申请号：EP15850113.0
申请日：2015-10-06
申请人： Floadia Corporation
发明人： TANIGUCHI Yasuhiro , KAWASHIMA Yasuhiko , KASAI Hideo , SAKURAI Ryotaro , SHINAGAWA Yutaka , OKUYAMA Kosuke
IPC分类号： H01L21/336 , H01L21/8234 , H01L27/088 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/792 , H01L21/823456 , H01L27/088 , H01L27/11565 , H01L27/11573 , H01L29/42344
摘要： A method for producing a semiconductor integrated circuit device, and a semiconductor integrated circuit device are disclosed. In the method, a first select gate electrode (G2a, G2b) and a second select gate electrode (G3a, G3b) electrically insulated from each other are formed in a memory circuit region (ER1) through a photomask process of forming a logic gate electrode (G5, G6) in a peripheral circuit region (ER2). Thus, even when the first select gate electrode (G2a or G2b) and the second select gate electrode (G3a, G3b) are formed to be separately controllable, an extra dedicated photomask process of fabricating only the memory circuit region (ER1) does not need to be performed in addition to a conventional dedicated photomask process of fabricating only a memory circuit region. Thereby, production cost is reduced accordingly.
摘要翻译：公开了一种制造半导体集成电路器件的方法和半导体集成电路器件。在该方法中，通过形成逻辑栅电极的光掩模工艺在存储电路区域（ER1）中形成彼此电绝缘的第一选择栅电极（G2a，G2b）和第二选择栅电极（G3a，G3b）（G5，G6）在外围电路区域（ER2）中。因此，即使当第一选择栅极电极（G2a或G2b）和第二选择栅极电极（G3a，G3b）形成为可单独控制时，仅制造存储器电路区域（ER1）的额外专用光掩模工艺也不需要除了仅制造存储器电路区域的常规专用光掩模工艺之外，还要执行该工艺。由此，生产成本相应降低。

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