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11. 发明公开

EP3069347A2 MAGNETO-OPTICAL DEVICE 有权
标题翻译：磁光学设备
公开(公告)号：EP3069347A2
公开(公告)日：2016-09-21
申请号：EP14800173.8
申请日：2014-11-14
申请人： Stichting Katholieke Universiteit Nijmegen
发明人： RASING, Theodorus Henricus Maricus Maria , SAVOINI, Matteo
IPC分类号： G11C13/06 , G11C13/04 , G11C11/16 , G11B11/10
CPC分类号： G11C11/02 , G11C11/16 , G11C13/04 , G11C13/06
摘要： A magneto-optical device comprising a magnetic unit and an optical unit, an electronic device comprising the magneto-optical device, a method of energy saving using the magneto-optical device, an array comprising the magneto-optical devices, and a method of changing magnetic orientation.

12. 发明公开

EP2671229A4 METHOD OF WRITING TO A SPIN TORQUE MAGNETIC RANDOM ACCESS MEMORY 有权转让
标题翻译：方法写在一拧，扭矩磁直接访问存储器
公开(公告)号：EP2671229A4
公开(公告)日：2016-07-20
申请号：EP12742660
申请日：2012-01-31
申请人： EVERSPIN TECHNOLOGIES INC
发明人： ALAM SYED M , ANDRE THOMAS , CROFT MATTHEW R , SUBRAMANIAN CHITRA , LIN HALBERT
IPC分类号： G11C11/00 , G06F11/10 , G11C11/16 , G11C13/00 , G11C29/04
CPC分类号： G11C11/1675 , G06F11/1048 , G06F11/1076 , G11C11/00 , G11C11/16 , G11C11/1673 , G11C11/1693 , G11C2013/0076 , G11C2029/0411
摘要： A spin-torque magnetoresistive memory comprises an array (602) of spin-torque magnetoresistive memory bits; a plurality of latches (626); array read circuits (610) coupled to the array of bits (602) and the plurality of latches (626), wherein the array read circuits are configured to: sample bits in a page within the array of bits, wherein sampling provides a sampled voltage for each of the bits in the page, wherein the array read circuits are configured to sample each bit in the page by applying a first voltage across the bit and converting a current resulting from applying the first voltage to the sampled voltage; after sampling the bits in the page, apply a first write current pulse to each of the bits in the page to set all of the bits in the page to a first logic state; after applying the first write current pulse to each of the bits in the page, resample each of the bits in the page to provide a resampled voltage for each bit in the page, wherein the array read circuits are configured to resample each bit by reapplying the first voltage across the bit and adding an offset current to a current resulting from reapplying the first voltage across the bit, wherein the array read circuits are configured to generate the resampled voltage for each bit using the offset current and the current resulting from reapplying the first voltage across the bit; for each bit in the page, compare the resampled voltage with the sampled voltage to determine a bit state for the bit, wherein the bit state for each bit is either the first logic state or a second logic state; and store the bit state for each bit in the page in a corresponding latch of the plurality of latches (626). The memory comprises further array write circuits (612) coupled to the array of bits (602) and the plurality of latches (626), the array write circuits (612) configured to, for each of the bits in the page having the second logic state as stored in the plurality of latches (626), initiate a write-back to reset the bit to the second state in the array, wherein the write-back for each bit includes applying a second write current pulse to set the bit to the second state.
摘要翻译：一种方法，包括自旋扭矩磁性随机存取存储器的破坏性读出比特，并立即写回原来的或反转的值。写回位和写回比特的有条件的反演的大多数状态的检测被采用以减少回写脉冲的数量。在指定时间内或原始写入手术中止是开始将导致回写脉冲或原始写操作脉冲的部分之前接收到写命令。写在随后的写操作脉冲将遵循开采破坏性读期间写回位条件反转确定性。

13. 发明公开

EP2652741A4 MEMORY CONTROLLER AND METHOD FOR INTERLEAVING DRAM AND MRAM ACCESSES 有权转让
标题翻译：内存控制器和方法NESTING DRAM和MRAM的访问
公开(公告)号：EP2652741A4
公开(公告)日：2016-07-06
申请号：EP11847949
申请日：2011-12-16
申请人： EVERSPIN TECHNOLOGIES INC
发明人： ALAM SYED M , ANDRE THOMAS , GOGL DIETMAR
IPC分类号： G11C16/04 , G06F13/16
CPC分类号： G06F3/0659 , G06F3/0611 , G06F3/0685 , G06F12/0246 , G06F12/0638 , G06F13/1694 , G06F2212/205 , G06F2212/7201 , G11C7/1042 , G11C7/1072 , G11C8/04 , G11C11/005 , G11C11/16 , G11C11/1673 , G11C11/1675 , G11C11/4076 , G11C11/4091 , G11C11/4094 , G11C11/4096 , G11C14/0036
摘要： A memory controller and method for interleaving volatile and non-volatile memory different latencies and page sizes are described wherein a single DDR3 memory controller communicates with a number of memory modules comprising of at least non-volatile memory, e.g., spin torque magnetic random access memory, integrated in a different Rank or Channel with a volatile memory, e.g., dynamic random access memory (DRAM).

14. 发明公开

EP3028279A1 DISPOSITIF MEMOIRE AVEC SKYRMIONS MAGNETIQUES ET PROCEDE ASSOCIE 有权转让
标题翻译： SPEICHERUNGSVORRICHTUNG MIT MAGNETISCHEN SKYRMIONEN UNDZUGEHÖRIGESVERFAHREN
公开(公告)号：EP3028279A1
公开(公告)日：2016-06-08
申请号：EP14745171.0
申请日：2014-08-01
申请人： THALES , Centre National de la Recherche Scientifique (CNRS) , Universite Paris-Sud
发明人： CROS, Vincent , FERT, Albert , SAMPAIO, Joao , SENEOR, Pierre
IPC分类号： G11C11/16 , G11C19/08
CPC分类号： G11C11/1675 , G11C11/16 , G11C11/1673 , G11C11/18 , G11C19/08 , H01L43/10
摘要： The invention relates to a storage device (10), comprising at least one spintronic element (11) suitable for representing a state among at least n states associated with the spintronic element, n>1, characterised in that each of the n states is associated with at least one characteristic of a group of magnetic skyrmions (1) in the spintronic element, and in that said characteristic associated with a state n °i is different from said characteristic associated with a state n °j when the states n °i and j are two different states among the n states.
摘要翻译：一种存储装置，包括至少一个适于表示与所述自旋电子元件相关联的至少n个状态中的状态的自旋电子元件，n> 1，其特征在于，所述n个状态中的每一个与一组磁体的至少一个特性相关联在状态n oi和n oj是n个状态之间的两个不同状态时，与状态n oi相关联的所述特性不同于与状态n oj相关联的所述特征。

15. 发明公开

EP2909838A4 INVERTED ORTHOGONAL SPIN TRANSFER LAYER STACK 审中-公开
标题翻译： UMGEKEHRTER ORTHOGONALER旋转传递速度计
公开(公告)号：EP2909838A4
公开(公告)日：2016-06-01
申请号：EP13847226
申请日：2013-10-15
申请人： UNIV NEW YORK
发明人： KENT ANDREW , BACKES DIRK
IPC分类号： G11C11/16 , H01F10/32 , H01L43/08
CPC分类号： H01L37/00 , B82Y40/00 , G11C11/16 , G11C11/161 , H01F10/3272 , H01F10/3286 , H01F41/307 , H01L43/08
摘要： A magnetic device includes a pinned magnetic layer having a first fixed magnetization vector with a first fixed magnetization direction. The magnetic device also includes a free magnetic layer having a variable magnetization vector having at least a first stable state and a second stable state. The magnetic device also has a first non-magnetic layer and a reference. The first non-magnetic layer spatially separates the pinned magnetic layer and the free magnetic layer. The magnetic device also includes a second non-magnetic layer spatially separating the free magnetic layer and the reference magnetic layer. A magnetic tunnel junction, located below the pinned magnetic layer, is formed by the free magnetic layer, the second non-magnetic layer, and the reference magnetic layer. Application of a current pulse, having either positive or negative polarity and a selected amplitude and duration, through the magnetic device switches the variable magnetization vector.
摘要翻译：磁性装置包括具有第一固定磁化方向的第一固定磁化矢量的钉扎磁性层。磁性装置还包括具有至少第一稳定状态和第二稳定状态的可变磁化矢量的自由磁性层。磁性装置还具有第一非磁性层和参考。第一非磁性层空间地分离被钉扎的磁性层和自由磁性层。磁性装置还包括在空间上分离自由磁性层和参考磁性层的第二非磁性层。位于钉扎磁性层下方的磁性隧道结由自由磁性层，第二非磁性层和参考磁性层形成。通过磁性装置施加具有正极性或负极性以及所选择的幅度和持续时间的电流脉冲切换可变磁化矢量。

16. 发明授权

EP2276034B1 Self-referenced magnetic random access memory cell 有权转让
标题翻译：自相关的磁性随机存取存储器单元
公开(公告)号：EP2276034B1
公开(公告)日：2016-04-27
申请号：EP10168729.1
申请日：2010-07-07
申请人： Crocus Technology S.A.
发明人： Berger, Neal , Nozières, Jean-Pierre
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G11C11/16 , G11C11/1673

17. 发明公开

EP2987168A1 CELLULE MÉMOIRE AVEC MÉMORISATION DE DONNÉES NON VOLATILE 失效
标题翻译：具有非易失性内存内存CELL
公开(公告)号：EP2987168A1
公开(公告)日：2016-02-24
申请号：EP14722276.4
申请日：2014-04-15
申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives , Centre National de la Recherche Scientifique
发明人： DI PENDINA, Grégory
IPC分类号： G11C14/00 , G11C11/16 , G11C13/00
CPC分类号： G11C13/0069 , G11C11/16 , G11C11/1675 , G11C11/2275 , G11C13/0002 , G11C13/0004 , G11C14/0072 , G11C14/0081 , G11C14/009
摘要： The invention concerns a memory cell comprising first and second resistive elements (202, 204) coupled respectively between first and second storage nodes and first and second intermediate nodes, at least one of them being programmable to take up one of at least two resistive states (
Rmin' Rmax); a third transistor (220) coupled between the first and second intermediate nodes; a fourth transistor (502) coupled between the first storage node (206, 210) and a data input node (506); and a control circuit arranged, during a write phase, to activate the third and fourth transistors and to couple the data input node to a second supply voltage (VDD, GND) via a first circuit block (508) in order to generate a current in a first direction through the first and second resistive elements in order to programme the resistive state of at least one of the elements.

18. 发明授权

EP2593938B1 METHOD AND SYSTEM FOR PROVIDING MAGNETIC TUNNELING JUNCTION ELEMENTS HAVING LAMINATED FREE LAYERS AND MEMORIES USING SUCH MAGNETIC ELEMENTS 有权转让
标题翻译：方法和一种用于提供磁性隧道连接器，带层压自由层与显存采用这种磁性元素
公开(公告)号：EP2593938B1
公开(公告)日：2016-01-20
申请号：EP11807322.0
申请日：2011-07-08
申请人： Grandis, Inc.
发明人： LOTTIS, Daniel , CHEN, Eugene Youjun , TANG, Xueti , WATTS, Steven M.
IPC分类号： H01L43/08 , B82Y25/00 , G11C11/16 , H01F10/32
CPC分类号： H01L43/08 , B82Y25/00 , G11C11/16 , G11C11/1659 , H01F10/3254 , H01F10/3259 , H01F10/3263 , H01F10/3272 , H01F10/3286

19. 发明公开

EP2951835A1 ERROR DETECTION AND CORRECTION OF ONE-TIME PROGRAMMABLE ELEMENTS 审中-公开
标题翻译： FEHLERERKENNUNG UND-KORREKTUR VON EINMALIG PROGRAMMIERBAREN ELEMENTEN
公开(公告)号：EP2951835A1
公开(公告)日：2015-12-09
申请号：EP14703710.5
申请日：2014-01-22
申请人： Qualcomm Incorporated
发明人： KIM, Jung Pill , KIM, Taehyun , KIM, Sungryul
IPC分类号： G11C17/02 , G06F11/10 , G11C17/14 , G11C29/02 , G11C17/18
CPC分类号： G06F11/1048 , G11C11/16 , G11C17/02 , G11C17/146 , G11C17/18 , G11C29/027 , G11C2029/4402
摘要： A circuit includes a first one-time programmable (OTP) element and a second OTP element. The circuit also includes error detection circuitry coupled to receive a first representation of data from the first OTP element. The circuit further includes output circuitry responsive to an output of the error detection circuitry to output an OTP read result based on the first representation of the data or based on a second representation of the data from the second OTP element.
摘要翻译：电路包括第一一次可编程（OTP）元件和第二OTP元件。电路还包括耦合以从第一OTP元件接收数据的第一表示的错误检测电路。电路还包括响应于错误检测电路的输出的输出电路，以基于数据的第一表示或基于来自第二OTP元件的数据的第二表示来输出OTP读取结果。

20. 发明公开

EP2936493A1 INTEGRATED MRAM CACHE MODULE 有权
标题翻译：集成MRAM-CACHE-MODUL
公开(公告)号：EP2936493A1
公开(公告)日：2015-10-28
申请号：EP13822034.8
申请日：2013-12-20
申请人： Qualcomm Incorporated
发明人： DONG, Xiangyu , KIM, Jung Pill , SUH, Jungwon
IPC分类号： G11C11/16 , G06F12/08 , G11C15/00
CPC分类号： G11C11/16 , G11C11/1653 , G11C2211/5643 , Y10T29/49117
摘要： Systems and methods for integrated magnetoresistive random access memory (MRAM) modules. An integrated circuit includes a processor without a last level cache integrated on a first chip a MRAM module comprising a MRAM last level cache and a MRAM main memory integrated on a second chip, wherein the MRAM module is a unified structure fabricated as monolithic package or a plurality of packages. The second package further includes memory controller logic. A simplified interface structure is configured to couple the first and the second package. The MRAM module is designed for high speed, high data retention, aggressive prefetching between the MRAM last level cache and the MRAM main memory, improved page handling, and improved scalability.
摘要翻译：用于集成磁阻随机存取存储器（MRAM）模块的系统和方法。集成电路包括处理器，其没有集成在第一芯片上的最后一级高速缓存，MRAM模块包括MRAM最后一级高速缓存和集成在第二芯片上的MRAM主存储器，其中MRAM模块是制造为单片封装或多个包装。第二包还包括存储器控制器逻辑。简化的接口结构被配置为耦合第一和第二封装。 MRAM模块设计用于高速，高数据保留，MRAM最后一级缓存和MRAM主存储器之间的积极预取，改进的页面处理和改进的封印能力。

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