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11. 发明公开

EP1024426A2 High performance RISC microprocessor architecture 失效
标题翻译： HochleistungsarchitekturfürRISC-Mikroprozessor
公开(公告)号：EP1024426A2
公开(公告)日：2000-08-02
申请号：EP00109747.6
申请日：1992-07-07
申请人： SEIKO EPSON CORPORATION
发明人： Nguyen, Le Trong , Lentz, Derek J. , Miyayama, Yoshiyuki , Garg, Sanjiv , Hagiwara, Yasuaki , Wang, Johannes , Lau,Tei-Li , Trang, Quang H.
IPC分类号： G06F9/38
CPC分类号： G06F9/3822 , G06F9/30061 , G06F9/30072 , G06F9/30112 , G06F9/30116 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30167 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3806 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
摘要： The high-performance, RISC core based microprocessor architecture permits concurrent execution of instructions obtained from memory through an instruction prefetch unit having multiple prefetch paths allowing for the main program instruction stream, a target conditional branch instruction stream and a procedural instruction stream. The target conditional branch prefetch path allows both possible instruction streams for a conditional branch instruction to be prefetched. The procedural instruction prefetch path allows a supplementary instruction stream to be accessed without clearing the main or target prefetch buffers.
Each instruction set includes a plurality of fixed length instructions. An instruction FIFO is provided for buffering instruction sets in a plurality of instruction set buffers including a first buffer and a second buffer.
An instruction execution unit including a register file and a plurality of functional units is provided with an instruction control unit capable of examining the instruction sets within the first and second buffers and scheduling any of the instructions for execution by available functional units. Multiple data paths between the functional units and the register file allow multiple independent accesses to the register file by the functional units as necessary for the execution of the respective instructions.
The register file includes an additional set of temporary data registers. These temporary data registers are utilized by the instruction execution control unit to receive data processed by the functional units by the out-of-order execution of instructions in advance of the completed execution of a conditional branch instruction or any instruction that requires additional functional unit processing cycles to complete. The data stored in the temporary data registers is selectively held, cleared or retired to the register file depending on the actual state of the instruction stream at the point where all prior instructions have been executed.
摘要翻译：高性能，基于RISC核心的微处理器架构允许通过具有允许主程序指令流，目标条件转移指令流和程序性指令流的多个预取路径的指令预取单元从存储器中获得的指令的并发执行。目标条件分支预取路径允许预取条件分支指令的可能指令流。程序性指令预取路径允许访问辅助指令流而不清除主或预取预取缓冲器。每个指令集包括多个固定长度指令。提供指令FIFO用于缓冲包括第一缓冲器和第二缓冲器的多个指令集缓冲器中的指令集。包括寄存器文件和多个功能单元的指令执行单元设置有能够检查第一和第二缓冲器内的指令集的指令控制单元，并且调度任何指令以供可用功能单元执行。功能单元和寄存器文件之间的多个数据路径允许功能单元对寄存器文件进行多次独立访问，以便执行相应的指令。寄存器文件包括一组附加的临时数据寄存器。这些临时数据寄存器被指令执行控制单元利用，以便在完成执行条件转移指令或需要额外的功能单元处理的任何指令之前通过指令的无序执行来接收由功能单元处理的数据循环完成。存储在临时数据寄存器中的数据根据在执行所有先前的指令的点的指令流的实际状态被有选择地保持，清除或退出到寄存器文件。

12. 发明公开

EP0834816A3 Microprocessor architecture capable of supporting multiple heterogenous processors 无效转让
标题翻译：微处理器架构能够支持多个异构处理器
公开(公告)号：EP0834816A3
公开(公告)日：1998-04-22
申请号：EP97119364.4
申请日：1992-07-07
申请人： SEIKO EPSON CORPORATION
发明人： Lentz, Derek J. , Hagiwara, Yasuaki , Tang, Cheng-Long , Lau, Te-Li
IPC分类号： G06F15/16
CPC分类号： G06F12/0813 , G06F12/0215 , G06F12/0831 , G06F12/0855 , G06F13/18 , G06F13/4022 , G06F15/167 , G06F15/17 , G06F15/173
摘要： A computer system comprising a microprocessor architecture capable of supporting multiple processors comprising a memory array unit (MAU), an MAU system bus comprising data, address and control signal buses, an I/O bus comprising data, address and control signal buses, a plurality of I/O devices and a plurality of microprocessors. Data transfers between data and instruction caches and I/O devices and a memory and other I/O devices are handled using a switch network port data and instruction cache and I/O interface circuits. Access to the memory buses is controlled by arbitration circuits which utilize fixed and dynamic priority schemes. A test and set bypass circuit is provided for preventing a loss of memory bandwidth due to spin-locking. A content addressable memory (CAM) is used to store the address of the semaphore and is checked by devices attempting to access the memory to determine whether the memory is available before an address is placed on the memory bus. Writing to the region protected by the semaphore clears the semaphore and the CAM. A row match comparison circuit is provided for reducing memory latency by giving an increased priority to successive requests for access to memory locations having the same row address. Dynamic switch/port arbitration is provided by changing the priority of the devices based on the intrinsic priority of the device, the number of times that a request has been serviced based on a row match, the number of times that a device has been denied service and the number of times that a device has been serviced. Circuits are also provided for invalidation and intervention such that master and slave devices are operating with the most current information. Circuits are also included to provide dynamic memory refresh on an automatic basis by signals from any one of the processors since each of the processors keep track when a memory refresh has occurred and the lapse time between refresh requests.
摘要翻译：包括能够支持包括存储器阵列单元（MAU）的多个处理器的微处理器架构的计算机系统，包括数据，地址和控制信号总线的MAU系统总线，包括数据的I / O总线，地址和控制信号总线，多个的I / O设备和多个微处理器。数据和指令高速缓存和I / O设备以及存储器和其他I / O设备之间的数据传输使用交换机网络端口数据和指令高速缓存以及I / O接口电路进行处理。对存储器总线的访问是由使用固定和动态优先级方案的仲裁电路控制的。提供测试和设置旁路电路，用于防止由于自旋锁定导致的存储器带宽损失。内容可寻址存储器（CAM）用于存储信号量的地址，并由尝试访问存储器的设备检查，以确定在将地址放置在存储器总线上之前，存储器是否可用。写入受信号量保护的区域会清除信号量和CAM。行匹配比较电路被提供用于通过给连续访问具有相同行地址的存储器位置的连续请求增加优先级来减少存储器等待时间。动态交换机/端口仲裁是通过根据设备的固有优先级改变设备的优先级，基于行匹配的请求已被服务的次数，设备被拒绝服务的次数以及设备已被维修的次数。还提供了用于失效和干预的电路，以便主设备和从设备使用最新的信息进行操作。还包括电路以便通过来自任何一个处理器的信号自动地提供动态存储器刷新，因为每个处理器在存储器刷新已经发生时以及刷新请求之间的流逝时间保持跟踪。

13. 发明公开

EP1526446A3 Extensible RISC microprocessor architecture 失效
标题翻译： RISC处理器与可膨胀结构
公开(公告)号：EP1526446A3
公开(公告)日：2007-04-04
申请号：EP05001561.9
申请日：1992-07-07
申请人： SEIKO EPSON CORPORATION
发明人： Nguyen, Le Trong , Miyayama, Yoshiyuki , Lentz, Derek J. , Garg, Sanjiv , Hagiwara, Yasuaki , Wang, Johannes , Lau, Tei-Li , Trang, Quang H.
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/30167 , G06F9/30054 , G06F9/30101 , G06F9/30105 , G06F9/30112 , G06F9/30116 , G06F9/3012 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30141 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3824 , G06F9/3828 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3853 , G06F9/3857 , G06F9/3861 , G06F9/3865 , G06F9/3885
摘要： The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of functional units. The fetch unit generally maintains a predetermined number of instructions in an instruction buffer. The execution unit includes an instruction selection unit, coupled to the instruction buffer, for selecting instructions for execution, and a plurality of functional units for performing instruction specified functional operations. A unified instruction scheduler, within the instruction selection unit, initiates the processing of instructions through the functional units when instructions are determined to be available for execution and for which at least one of the functional units implementing a necessary computational function is available. Unified scheduling is performed across multiple execution data paths, where each execution data path, and corresponding functional units, is generally optimized for the type of computational function that is to be performed on the data: integer, floating point, and boolean. The number, type and computational specifics of the functional units provided in each data path, and as between data paths, are mutually independent.

14. 发明公开

EP1526446A2 Extensible RISC microprocessor architecture 失效
标题翻译：可扩展的RISC微处理器架构
公开(公告)号：EP1526446A2
公开(公告)日：2005-04-27
申请号：EP05001561.9
申请日：1992-07-07
申请人： SEIKO EPSON CORPORATION
发明人： Nguyen, Le Trong , Miyayama, Yoshiyuki , Lentz, Derek J. , Garg, Sanjiv , Hagiwara, Yasuaki , Wang, Johannes , Lau, Tei-Li , Trang, Quang H.
IPC分类号： G06F9/38
CPC分类号： G06F9/30167 , G06F9/30054 , G06F9/30101 , G06F9/30105 , G06F9/30112 , G06F9/30116 , G06F9/3012 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30141 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3824 , G06F9/3828 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3853 , G06F9/3857 , G06F9/3861 , G06F9/3865 , G06F9/3885
摘要： The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of functional units. The fetch unit generally maintains a predetermined number of instructions in an instruction buffer. The execution unit includes an instruction selection unit, coupled to the instruction buffer, for selecting instructions for execution, and a plurality of functional units for performing instruction specified functional operations. A unified instruction scheduler, within the instruction selection unit, initiates the processing of instructions through the functional units when instructions are determined to be available for execution and for which at least one of the functional units implementing a necessary computational function is available. Unified scheduling is performed across multiple execution data paths, where each execution data path, and corresponding functional units, is generally optimized for the type of computational function that is to be performed on the data: integer, floating point, and boolean. The number, type and computational specifics of the functional units provided in each data path, and as between data paths, are mutually independent.
摘要翻译：基于RISC核心的高性能微处理器架构包括用于从指令存储器取出指令集的指令取出单元和通过并行功能单元阵列实现多个指令的并行执行的执行单元。提取单元通常在指令缓冲器中保持预定数量的指令。执行单元包括耦合到指令缓冲器，用于选择用于执行的指令的指令选择单元，以及用于执行指令指定的功能操作的多个功能单元。在指令选择单元内的统一指令调度器在确定指令可用于执行时启动对通过功能单元的指令的处理，并且实现必要计算功能的功能单元中的至少一个可用。在多个执行数据路径上执行统一调度，其中每个执行数据路径和相应的功能单元通常针对要在数据上执行的计算函数的类型（整数，浮点和布尔值）进行优化。每个数据路径中以及数据路径之间提供的功能单元的数量，类型和计算细节是相互独立的。

15. 发明授权

EP1024426B1 High performance RISC microprocessor architecture 失效
标题翻译：对于RISC微处理器高性能架构
公开(公告)号：EP1024426B1
公开(公告)日：2004-02-25
申请号：EP00109747.6
申请日：1992-07-07
申请人： SEIKO EPSON CORPORATION
发明人： Nguyen, Le Trong , Lentz, Derek J. , Miyayama, Yoshiyuki , Garg, Sanjiv , Hagiwara, Yasuaki , Wang, Johannes , Lau,Tei-Li , Trang, Quang H.
IPC分类号： G06F12/08 , G06F9/38
CPC分类号： G06F9/3822 , G06F9/30061 , G06F9/30072 , G06F9/30112 , G06F9/30116 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30167 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3806 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885

16. 发明公开

EP1385085A1 High performance risc microprocessor architecture 失效
标题翻译：高性能risc微处理器架构
公开(公告)号：EP1385085A1
公开(公告)日：2004-01-28
申请号：EP03024585.6
申请日：1992-07-07
申请人： SEIKO EPSON CORPORATION
发明人： Nguyen, Le Trong , Lentz, Derek J. , Miyayama, Yoshiyuki , Garg, Sanjiv , Hagiwara, Yasuaki , Wang, Johannes , Lau, Tei-Li , Trang, Quang H.
IPC分类号： G06F9/38
CPC分类号： G06F9/3822 , G06F9/30061 , G06F9/30072 , G06F9/30112 , G06F9/30116 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30167 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3806 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
摘要： The high-performance, RISC core based microprocessor architecture permits concurrent execution of instructions obtained from memory through an instruction prefetch unit having multiple prefetch paths allowing for the main program instruction stream, a target conditional branch instruction stream and a procedural instruction stream. The target conditional branch prefetch path allows both possible instruction streams for a conditional branch instruction to be prefetched. The procedural instruction prefetch path allows a supplementary instruction stream to be accessed without clearing the main or target prefetch buffers.
Each instruction set includes a plurality of fixed length instructions. An instruction FIFO is provided for buffering instruction sets in a plurality of instruction set buffers including a first buffer and a second buffer.
An instruction execution unit including a register file and a plurality of functional units is provided with an instruction control unit capable of examining the instruction sets within the first and second buffers and scheduling any of the instructions for execution by available functional units. Multiple data paths between the functional units and the register file allow multiple independent accesses to the register file by the functional units as necessary for the execution of the respective instructions.
The register file includes an additional set of temporary data registers. These temporary data registers are utilized by the instruction execution control unit to receive data processed by the functional units by the out-of-order execution of instructions in advance of the completed execution of a conditional branch instruction or any instruction that requires additional functional unit processing cycles to complete. The data stored in the temporary data registers is selectively held, cleared or retired to the register file depending on the actual state of the instruction stream at the point where all prior instructions have been executed.
摘要翻译：基于RISC核心的高性能微处理器架构允许通过具有允许主程序指令流，目标条件分支指令流和程序指令流的多个预取路径的指令预取单元从存储器获得的指令的并行执行。目标条件分支预取路径允许预取两个可能的指令流用于条件分支指令。过程指令预取路径允许访问补充指令流而不清除主或预取缓冲区。每个指令集包括多个固定长度的指令。提供指令FIFO用于缓冲包括第一缓冲器和第二缓冲器的多个指令集缓冲器中的指令集。包括寄存器文件和多个功能单元的指令执行单元设置有指令控制单元，该指令控制单元能够检查第一和第二缓冲器内的指令集并调度任何指令以由可用功能单元执行。功能单元和寄存器文件之间的多个数据路径允许功能单元根据执行相应指令的需要多次独立地访问寄存器文件。寄存器文件包含一组附加的临时数据寄存器。这些临时数据寄存器被指令执行控制单元用来在完成执行条件分支指令之前通过指令的乱序执行来接收由功能单元处理的数据，或者需要附加功能单元处理的任何指令周期完成。存储在临时数据寄存器中的数据根据指令流的实际状态在所有先前指令已被执行的位置被选择性地保存，清除或退出到寄存器文件。

17. 发明公开

EP1024426A3 High performance RISC microprocessor architecture 失效
标题翻译：对于RISC微处理器高性能架构
公开(公告)号：EP1024426A3
公开(公告)日：2001-08-08
申请号：EP00109747.6
申请日：1992-07-07
申请人： SEIKO EPSON CORPORATION
发明人： Nguyen, Le Trong , Lentz, Derek J. , Miyayama, Yoshiyuki , Garg, Sanjiv , Hagiwara, Yasuaki , Wang, Johannes , Lau,Tei-Li , Trang, Quang H.
IPC分类号： G06F12/08 , G06F9/38
CPC分类号： G06F9/3822 , G06F9/30061 , G06F9/30072 , G06F9/30112 , G06F9/30116 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30167 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3806 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
摘要： The high-performance, RISC core based microprocessor architecture permits concurrent execution of instructions obtained from memory through an instruction prefetch unit having multiple prefetch paths. Each instruction set includes a plurality of fixed length instructions. An instruction FIFO is provided for buffering instruction sets in a plurality of instruction set buffers including a first buffer and a second buffer. An instruction execution unit including a register file and a plurality of functional units is provided with an instruction control unit capable of examining the instruction sets within the first and second buffers and scheduling any of the instructions for execution by available functional units. The register file includes an additional set of temporary data registers. These temporary data registers are utilized by the instruction execution control unit to receive data processed by the functional units by the out-of-order execution of instructions in advance of the completed execution of a conditional branch instruction or any instruction that requires additional functional unit processing cycles to complete. The data stored in the temporary data registers is selectively held, cleared or retired to the register file depending on the actual state of the instruction stream at the point where all prior instructions have been executed.

18. 发明公开

EP0945787A2 Risc microprocessor architecture implementing fast trap and exception state 失效
标题翻译： RISC微处理器架构，快速中断和异常情况
公开(公告)号：EP0945787A2
公开(公告)日：1999-09-29
申请号：EP99112833.1
申请日：1992-07-07
申请人： SEIKO EPSON CORPORATION
发明人： Nguyen, Le Trong , Miyayama, Yoshiyuki , Garg, Sanjiv , Trang, Quang H. , Lentz, Derek J. , Hagiwara, Yasuaki , Wang, Johannes , Lau, Tei-Li
IPC分类号： G06F9/38
CPC分类号： G06F9/3865 , G06F9/3017 , G06F9/32 , G06F9/322 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3836 , G06F9/384 , G06F9/3857 , G06F9/3861 , G06F9/3885 , G06F9/462 , G06F9/4812 , G06F15/7842
摘要： Fast trap mechanism for a microprocessor, wherein a vector trap table is maintained which contains space for a plurality of instructions in each table entry. When a fast trap occurs, control is transferred directly into the table entry corresponding to the trap number. The trap handler can be located completely inside the table entry, or it can transfer control to additional handler code.

19. 发明公开

EP0886225A1 Microprocessor architecture capable of supporting multiple heterogenous processors 有权转让
标题翻译：微处理器架构能够支持多个异构处理器
公开(公告)号：EP0886225A1
公开(公告)日：1998-12-23
申请号：EP98115836.3
申请日：1992-07-07
申请人： SEIKO EPSON CORPORATION
发明人： Lentz, Derek J. , Hagiwara, Yasuaki , Tang, Cheng-Long , Lau, Te-Li
IPC分类号： G06F15/173
CPC分类号： G06F12/0813 , G06F12/0215 , G06F12/0831 , G06F12/0855 , G06F13/18 , G06F13/4022 , G06F15/167 , G06F15/17 , G06F15/173
摘要： A multiprocessor system, comprising a plurality of microprocessors; and a memory array unit (MAU); wherein each of said microprocessors comprises master devices and slave devices, said slave devices including a memory port coupled to said MAU, and a memory control unit (MCU) for controlling access to said memory port; wherein said MCU comprises: a switch network for transferring data between said master devices and said memory port; a memory port interface circuit; means for coupling said memory port interface circuit between said memory port and said switch network; switch arbitration means for arbitrating for said switch network; port arbitration means for arbitrating for said memory port; means for transferring to said port arbitration means a request to transfer data via said memory port through said switch network and said port interface circuit; means for transferring a port available signal from said port arbitration means to said switch arbitration means when said port interface circuit is free to process said request; and means responsive to said port available signal for transferring a switch available signal from said switch arbitration means to the source of said request and to said port arbitration means which said switch network is free to process said request.

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