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131. 发明公开

EP0534910A2 Row-decoder for nand-type rom 失效
标题翻译： ZeilendekodiererfürUND-NICHT-ROM-Speichertyp。
公开(公告)号：EP0534910A2
公开(公告)日：1993-03-31
申请号：EP92830457.5
申请日：1992-08-27
申请人： SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Pascucci, Luigi
IPC分类号： G11C17/12 , G11C8/00
CPC分类号： G11C17/123 , G11C8/10 , G11C17/12
摘要： A decoder for a ROM matrix organized in selectable NAND parcels of cells utilizes four selection means driven through five buses for implementing a two-level decoding, thus driving a fractionary number of rows through a plurality of selectable drivers. The architecture of the row decoder, based on a subdivision into a plurality of row drivers renders the circuitry physically compatible with the geometrical constraints imposed by a particularly small pitch of the cells. Subdivision of row drivers has positive effects also on access time, reliability and overall performance of the memory as compared to a memory provided with a decoder of the prior art driving in parallel all the homonymous rows of all the selectable NAND parcels of cells.
摘要翻译：用于组合在可选择的NAND小区中的ROM矩阵的解码器利用通过五个总线驱动的四个选择装置来实现两级解码，从而通过多个可选择的驱动器驱动少量的行数。行解码器的架构基于对多个行驱动器的细分，使得电路与由单元的特别小间距施加的几何约束物理上兼容。与现有技术的解码器配备的存储器相比，行驱动器的细分也对存储器的存取时间，可靠性和整体性能具有积极的影响，并行地并行地驱动所有可选择NAND单元组的所有同行。

132. 发明公开

EP0522539A2 Mask programmable read only memory device with multi-level memory cell array and process of fabrication thereof 失效
标题翻译： Maskenprogrammierbare Festwertspeicheranordnung mit einer Mehrpegelspeicherzellenmatrix und ihr Herstellungsverfahren。
公开(公告)号：EP0522539A2
公开(公告)日：1993-01-13
申请号：EP92111609.1
申请日：1992-07-08
申请人： NEC CORPORATION
发明人： Koyama, Shoji, NEC Corporation
IPC分类号： G11C11/56 , G11C17/12 , H01L27/112
CPC分类号： G11C16/0483 , G11C7/18 , G11C11/56 , G11C11/5692 , G11C16/24 , G11C17/123 , H01L27/0688 , H01L27/112
摘要： A mask programmable read only memory device comprises a plurality of memory cell blocks each (12a) having a plurality of first series combinations (12d/ 12e) of memory transistors (Qm4 to Qm6/ Qm10 to Qm12) and a plurality of second series combinations (12b; 12c) of memory transistors (Qm1 to Qm3/ Qm7 to Qm9), and each of the memory transistors is operative in either enhancement or depletion mode, wherein the plurality of first series combinations are respectively overlapped with the plurality of second series combinations so as to share word lines (WL1 to WLx) therebetween, thereby increasing the integration density without sacrifice of the real estate.
摘要翻译：掩模可编程只读存储器件包括多个存储单元块，每个存储单元块具有存储晶体管（Qm4至Qm6 / Qm10至Qm12）的多个第一串联组合（12d / 12e）和多个第二串联组合存储晶体管（Qm1至Qm3 / Qm7至Qm9）的每个存储晶体管（12b; 12c）），并且每个存储晶体管以增强或耗尽模式工作，其中多个第一串联组合分别与多个第二串联组合重叠为了在它们之间共享字线（WL1至WLx），从而增加集成密度而不牺牲房地产。

133. 发明公开

EP0424964A3 Read only memory device 失效
标题翻译：只读存储设备
公开(公告)号：EP0424964A3
公开(公告)日：1992-11-19
申请号：EP90120599.7
申请日：1990-10-26
申请人： SONY CORPORATION
发明人： Nakagawara, Akira, c/o Sony Corporation
IPC分类号： G11C17/12 , H01L27/112
CPC分类号： G11C17/126 , Y10S438/981
摘要： read-only memory device includes a number of MIS transistors forming memory cells arranged in a matrix configuration (1) to provide a NOR type memory device with high current driving capability for the memory cells. Bit lines (B i to B 3 ) and column lines (C 1 ,C 2 ) are arrayed alternately in common in each cell column so as to be used in common by adjacent memory cells in the word line extending direction. The bit lines for reading out signals from the memory cells function as the sources or drains of the MIS transistors of the memory cells, whereas the column lines for supplying the constant voltage to the memory cells function as the drains or sources of the MIS transistors of the memory cells. For column selection, there is provided a first selection switch (2) for selecting a group consisting of a plurality of bit lines and a plurality of column lines. A second selection switch and (Ti to T 4 ) a third selection switch (T s to Tg) are provided for selecting the bit line and the column line of the group, respectively. Since the bit lines and the column lines may be used fixedly, the second and the third selection switches may be arranged with a layout allowance and, if these second and third selection switches are formed by MIS transistors similar to those of the memory cells, the direction in common with the memory cells may be the channel direction to contribute to improved circuit integration. The MIS transistor constituting the memory cell may be of such a construction in which the source and drain regions may be provided below the thick insulating film formed on the substrate surface, such as field oxide film. This results in more effective utilization of the area on the substrate to realize a higher degree of integration. The self-alignment process promotes the circuit integration more effectively.
摘要翻译：只读存储器件包括形成排列成矩阵结构（1）的存储单元的多个MIS晶体管，以便为存储单元提供高电流驱动能力的NOR型存储器件。位线（Bi到B3）和列线（C1，C2）在每个单元列中交替地共同排列，以便由字线延伸方向上的相邻存储单元共同使用。用于从存储单元读出信号的位线用作存储单元的MIS晶体管的源极或漏极，而用于向存储单元提供恒定电压的列线用作MIS晶体管的漏极或源极存储单元。对于列选择，提供了用于选择由多个位线和多个列线组成的组的第一选择开关（2）。提供第二选择开关和（Ti至T4）第三选择开关（Ts至Tg）以分别选择组的位线和列线。由于位线和列线可以固定使用，所以第二和第三选择开关可以布置有布局容差，并且如果这些第二和第三选择开关由与存储单元类似的MIS晶体管形成，与存储器单元共同的方向可以是有助于改进电路集成的通道方向。构成存储单元的MIS晶体管可以是这样一种结构，其中源区和漏区可以设置在衬底表面上形成的厚绝缘膜之下，例如场氧化膜。这导致更有效地利用衬底上的区域来实现更高的集成度。自对准过程更有效地促进了电路集成。

134. 发明公开

EP0496523A2 Sense amplifier circuit 失效
标题翻译： Leseverstärkerschaltung。
公开(公告)号：EP0496523A2
公开(公告)日：1992-07-29
申请号：EP92300328.9
申请日：1992-01-15
申请人： NEC CORPORATION
发明人： Okamoto, Toshiyuki, c/o NEC Corporation
IPC分类号： G11C17/12 , G11C7/00 , G11C7/06
CPC分类号： G11C17/12 , G11C7/067 , G11C7/12
摘要： A sense amplifier circuit for sensing a datum read from a mask ROM intended for shortening delays in read time due to the stray capacity of the bit line (B1) is disclosed. The circuit has a charging circuit (2, 3) and a discharging-current path (4, 5, 6). At the beginning of a read cycle, the charging circuit is connected to the bit line to promptly precharge the stray capacity. Subsequently an addressing signal is applied to a word line. If the addressed memory cell is an OFF bit, then the electric potential level of the bit line remains unchanged. If the memory cell is an ON bit, then the discharging-current path turns on, thereby enabling prompt discharge.
摘要翻译：公开了一种读出放大器电路，用于感测由掩模ROM读取的数据，该掩模ROM用于缩短由于位线（B1）的杂散容量引起的读取时间的延迟。电路具有充电电路（2,3）和放电电流通路（4,5,6）。在读周期开始时，充电电路连接到位线，以便对杂散容量进行预充电。随后，寻址信号被施加到字线。如果寻址的存储单元是OFF位，则位线的电位电平保持不变。如果存储单元是ON位，则放电电流路径导通，从而能够迅速放电。

135. 发明公开

EP0488672A3 Memory device with current mirror type sense amplifiers 失效
标题翻译：具有电流型电感式放大器的存储器件
公开(公告)号：EP0488672A3
公开(公告)日：1992-07-15
申请号：EP91310916.1
申请日：1991-11-27
申请人： NEC CORPORATION
发明人： Ban, Akira, c/o NEC IC MICROCOMPUTER SYSTEM, LTD
IPC分类号： G11C17/12 , G11C7/06 , G11C7/00
CPC分类号： G11C7/14 , G11C7/062 , G11C17/12 , G11C17/123
摘要： A plurality of reference memory cell units are arranged to be connected to rows of matrix-patterned information memory cell units. Each of the reference memory cell units comprises a selection cell of an NMOS transistor, and three reference memory cells of depletion type NMOS transistors, and each of the information memory cell units comprises a selection cell of an NMOS transistor, and three information memory cells of NMOS transistors, one of which is of a depletion type. The selection cells are connected between the reference and information memory cells by a common selection line, and the reference and information memory cells are connected therebetween by common word lines. This avoids the occurrence of the unevenness of characteristics resulting from the fabrication process.

136. 发明公开

EP0467607A2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：EP0467607A2
公开(公告)日：1992-01-22
申请号：EP91306365.7
申请日：1991-07-15
申请人： NEC CORPORATION
发明人： Kohno, Takaki, c/o NEC CORPORATION
IPC分类号： G11C17/12
CPC分类号： G11C17/123
摘要： Electric field stress applied to memory cells (107) is relieved in a semiconductor memory device. For this purpose, an X-decoder circuit (104) applies a low level signal to a selected memory cell in a selected memory cell block of a selected memory cell matrix, and a high level signal to non-selected memory cells in the selected memory cell block, while the X-decoder circuit applies the low level signal to memory cells of non-selected memory cell blocks of the selected memory cell matrix and memory cells of non-selected memory cell matrices.
摘要翻译：施加到存储器单元（107）的电场应力在半导体存储器件中被减轻。为此，X解码器电路（104）将低电平信号施加到所选存储器单元矩阵的所选存储器单元块中的选定存储器单元，并将高电平信号施加到所选存储器中的未选择存储器单元而X解码器电路将低电平信号施加到所选择的存储器单元矩阵的未选择的存储器单元块的存储器单元和未选择的存储器单元矩阵的存储器单元。

137. 发明公开

EP0444524A1 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：EP0444524A1
公开(公告)日：1991-09-04
申请号：EP91102499.0
申请日：1991-02-21
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Hara, Hiroyuki , Watanabe, Yoshinori
IPC分类号： G11C7/00 , G11C17/12
CPC分类号： H01L27/11896 , G11C7/1048 , G11C7/12 , G11C17/12
摘要： Disclosed is a semiconductor integrated circuit of a bipolar CMOS gate array type having a plurality of basic cells (8, 9, 10, and11)arranged in a matrix, each of which comprising MOS transistors (P1 to P4 and N1 to N4) as memory cells, a bipolar transistor (NPN1), and a resistance (R1) and bit lines for transferring data stored in the memory cells to the outside, and the semiconductor integrated circuit is characterized by that the basic cells (8, 9, 10, and 11) are grouped into a plurality of blocks (BLOCK A and BLOCK B), the bipolar NPN transistor (NPN1 or NPN4) in each block is used as a driver for reading operations of the data stored in the memory cells (P1 to P8 or N1 to N8) in each block (BLOCK A or BLOCK B), and the output line (OUTPUT LINE B or OUTPUT LINE D) is kept at a logic state "0" before reading operations for the memory cells (P1 to P8 or N1 to N8).
摘要翻译：公开了一种双极型CMOS门阵列型半导体集成电路，其具有多个排列成矩阵的基本单元（8,9,10和11），每个基本单元包括作为存储器的MOS晶体管（P1到P4和N1到N4）单元，双极晶体管（NPN1）和电阻（R1）以及用于将存储在存储单元中的数据传输到外部的位线，并且半导体集成电路的特征在于，基本单元（8,9,10和 11）被分组为多个块（块A和块B），每个块中的双极NPN晶体管（NPN1或NPN4）被用作用于读取存储在存储单元（P1至P8或（P1至P8或N1）的读操作之前，输出线（输出线B或输出线D）保持在逻辑状态“0”，在每个块（块A或块B）到N8）。

138. 发明公开

EP0434104A1 Integrated semiconductor circuit of the master slice type 失效
标题翻译： Integrierte Halbleiterschaltung vom Master-slice-Typ。
公开(公告)号：EP0434104A1
公开(公告)日：1991-06-26
申请号：EP90202962.8
申请日：1990-11-09
申请人： Philips Electronics N.V.
发明人： van den Elshout, Andreas Antonius Johannes Maria , Veendrick, Hendrikus Josephius Maria , Harberts, Dirk Willem
IPC分类号： G11C11/00 , G11C17/12
CPC分类号： G11C11/005
摘要： A master slice semiconductor circuit comprising ROM memory cells which consist of NMOS-transistors as well as PMOS-transistors. In order to increase the integration density on the master slice, the NMOS-transistors and the PMOS-transistors (memory cells) in one and the same row are controlled via one and the same word line. The circuit comprises row selection means, for example an exclusive-OR circuit for each row, for selecting either a single row of NMOS cells or a single row of PMOS cells.
摘要翻译：包括由NMOS晶体管以及PMOS晶体管组成的ROM存储单元的主分片半导体电路。为了提高母片上的积分密度，同一行中的NMOS晶体管和PMOS晶体管（存储单元）通过同一字线进行控制。电路包括行选择装置，例如用于每行的异或电路，用于选择单行NMOS单元或单行PMOS单元。

139. 发明授权

EP0182717B1 A read only memory circuit 失效
标题翻译：只读存储器电路
公开(公告)号：EP0182717B1
公开(公告)日：1991-01-30
申请号：EP85402244.9
申请日：1985-11-20
申请人： FUJITSU LIMITED
发明人： Wakimoto, Hideyuki , Yoshida, Masanobu
IPC分类号： G11C16/02 , G11C17/12
CPC分类号： G11C16/0441

140. 发明公开

EP0399362A2 A sense amplifier circuit 失效
标题翻译： Leseverstärkerschaltung。
公开(公告)号：EP0399362A2
公开(公告)日：1990-11-28
申请号：EP90109264.3
申请日：1990-05-16
申请人： FUJITSU LIMITED
发明人： Kasa, Yasushi
IPC分类号： G11C7/00 , G11C7/06 , G11C16/06 , G11C17/12
CPC分类号： G11C7/067 , G11C7/12 , G11C16/26 , G11C17/12
摘要： A sense amplifier circuit for use in a ROM comprises an excess charge detecting circuit (24) for producing a detection output when a potential of a bit line (BL) exceeds a normal value, and an excess charge discharging circuit (25) which operates in response to said excess charge detecting circuit (24) for discharging a bit line charge and for returning the bit line potential to the normal value.
The excess charge detecting circuit and the excess charge discharge circuit can be realized by a diode-connected transistor (24d,25c) connected between the bit line (BL) and an inverter (23) of the sense amplifier. When the bit line potential is about to exceed the predetermined value, the transistor turns on to prevent the bit line potential from exceeding the predetermined value.
摘要翻译：在ROM中使用的读出放大器电路包括：当位线（BL）的电位超过正常值时产生检测输出的过剩电荷检测电路（24）和在位线响应于用于放电位线电荷并将位线电位恢复到正常值的所述过剩电荷检测电路（24）。过剩电荷检测电路和过剩充电放电电路可以通过连接在位线（BL）和读出放大器的反相器（23）之间的二极管连接的晶体管（24d，25c）来实现。当位线电位将要超过预定值时，晶体管导通，以防止位线电位超过预定值。

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