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1. 发明授权

US08570823B2 Sense amplifier with low sensing margin and high device variation tolerance 有权
标题翻译：感测放大器具有低感测裕度和高器件变化公差
公开(公告)号：US08570823B2
公开(公告)日：2013-10-29
申请号：US12708108
申请日：2010-02-18
申请人： Yen-Huei Chen , Hsien-Yu Pan , Shao-Yu Chou
发明人： Yen-Huei Chen , Hsien-Yu Pan , Shao-Yu Chou
IPC分类号： G11C7/00
CPC分类号： G11C7/065 , G11C7/08 , G11C2207/005
摘要： In an embodiment related to a sense amplifier, the sense amplifier includes a pair of transistors (e.g., transistors P2 and P3) that, when appropriate, enables data on input lines DL and DLB to be preset directly to the internal nodes (e.g., nodes S and SB) of the sense amplifier, from which the data can be read out. In addition, this pair of transistors P2 and P3 also allows the internal nodes S and SB to share the pre-charge mechanisms of lines DL and DLB.
摘要翻译：在与感测放大器相关的实施例中，读出放大器包括一对晶体管（例如，晶体管P2和P3），其适当时使得能够将输入线DL和DLB上的数据直接预设到内部节点（例如，节点 S和SB），从中读出数据。此外，这对晶体管P2和P3也允许内部节点S和SB共享线DL和DLB的预充电机制。

2. 发明授权

US08077517B2 Distributed VDC for SRAM memory 有权
标题翻译：分布式VDC用于SRAM存储器
公开(公告)号：US08077517B2
公开(公告)日：2011-12-13
申请号：US12338732
申请日：2008-12-18
申请人： Li-Wen Wang , Yen-Huei Chen , Chen-Lin Yang , Hsien-Yu Pan , Shao-Yu Chou , Hung-Jen Liao
发明人： Li-Wen Wang , Yen-Huei Chen , Chen-Lin Yang , Hsien-Yu Pan , Shao-Yu Chou , Hung-Jen Liao
IPC分类号： G11C11/34
CPC分类号： G11C11/413 , G11C5/04 , G11C5/147
摘要： An integrated circuit structure includes a memory. The memory includes a first memory macro and a second memory macro identical to the first memory macro. A first power block is connected to the first memory macro and is configured to provide a regulated voltage to the first memory macro. The first power block has a first input and a first output. A second power block substantially identical to the first power block is connected to the second memory macro and is configured to provide the regulated voltage to the second memory macro. The second power block has a second input and a second output. The first input and the second input are interconnected. The first output and the second output are interconnected.
摘要翻译：集成电路结构包括存储器。存储器包括与第一存储器宏相同的第一存储器宏和第二存储器宏。第一功率块连接到第一存储器宏，并被配置为向第一存储器宏提供调节电压。第一功率块具有第一输入和第一输出。基本上与第一功率块相同的第二功率块连接到第二存储器宏，并且被配置为向第二存储器宏提供调节电压。第二功率块具有第二输入和第二输出。第一输入和第二输入互连。第一个输出和第二个输出相互连接。

3. 发明授权

US08928113B2 Layout scheme and method for forming device cells in semiconductor devices 有权
标题翻译：用于在半导体器件中形成器件单元的布局方案和方法
公开(公告)号：US08928113B2
公开(公告)日：2015-01-06
申请号：US13082497
申请日：2011-04-08
申请人： Hsien-Yu Pan , Jung-Hsuan Chen , Shao-Yu Chou , Yen-Huei Chen , Hung-Jen Liao
发明人： Hsien-Yu Pan , Jung-Hsuan Chen , Shao-Yu Chou , Yen-Huei Chen , Hung-Jen Liao
IPC分类号： H01L23/52 , H01L27/108 , H01L29/94 , H01L21/70 , H01L27/02 , H01L27/11 , H01L27/118
CPC分类号： H01L27/1116 , H01L21/768 , H01L27/0207 , H01L27/11 , H01L2027/11887
摘要： A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.
摘要翻译：用于形成字线解码器装置和具有字线解码器单元的其它装置的方法和布局提供了使用非DPL光刻操作形成金属互连层，并且使用下部或中间金属层或下部导电材料提供了用于缝合的远端布置的晶体管。晶体管可以设置在纵向布置的字线解码器或其他单元中或其附近，并且使用金属或导电材料的导电耦合降低晶体管之间的栅极电阻并避免RC信号延迟。

4. 发明申请

US20110199847A1 SENSE AMPLIFIER WITH LOW SENSING MARGIN AND HIGH DEVICE VARIATION TOLERANCE 有权
标题翻译：具有低感测尺寸和高设备变化公差的感测放大器
公开(公告)号：US20110199847A1
公开(公告)日：2011-08-18
申请号：US12708108
申请日：2010-02-18
申请人： Yen-Huei CHEN , Hsien-Yu Pan , Shao-Yu Chou
发明人： Yen-Huei CHEN , Hsien-Yu Pan , Shao-Yu Chou
IPC分类号： G11C7/06
CPC分类号： G11C7/065 , G11C7/08 , G11C2207/005
摘要： In an embodiment related to a sense amplifier, the sense amplifier includes a pair of transistors (e.g., transistors P2 and P3) that, when appropriate, enables data on input lines DL and DLB to be preset directly to the internal nodes (e.g., nodes S and SB) of the sense amplifier, from which the data can be read out. In addition, this pair of transistors P2 and P3 also allows the internal nodes S and SB to share the pre-charge mechanisms of lines DL and DLB.
摘要翻译：在与感测放大器相关的实施例中，读出放大器包括一对晶体管（例如，晶体管P2和P3），其适当时使得能够将输入线DL和DLB上的数据直接预设到内部节点（例如，节点 S和SB），从中读出数据。此外，这对晶体管P2和P3也允许内部节点S和SB共享线DL和DLB的预充电机制。

5. 发明申请

US20120256235A1 LAYOUT SCHEME AND METHOD FOR FORMING DEVICE CELLS IN SEMICONDUCTOR DEVICES 有权
标题翻译：用于在半导体器件中形成器件电池的布局方案和方法
公开(公告)号：US20120256235A1
公开(公告)日：2012-10-11
申请号：US13082497
申请日：2011-04-08
申请人： Hsien-Yu Pan , Jung-Hsuan Chen , Shao-Yu Chou , Yen-Huei Chen , Hung-Jen Liao
发明人： Hsien-Yu Pan , Jung-Hsuan Chen , Shao-Yu Chou , Yen-Huei Chen , Hung-Jen Liao
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L27/1116 , H01L21/768 , H01L27/0207 , H01L27/11 , H01L2027/11887
摘要： A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.
摘要翻译：用于形成字线解码器装置和具有字线解码器单元的其它装置的方法和布局提供了使用非DPL光刻操作形成金属互连层，并且使用下部或中间金属层或下部导电材料提供了用于缝合的远端布置的晶体管。晶体管可以设置在纵向布置的字线解码器或其他单元中或其附近，并且使用金属或导电材料的导电耦合降低晶体管之间的栅极电阻并避免RC信号延迟。

6. 发明申请

US20100157692A1 Distributed VDC for SRAM Memory 有权
标题翻译：分布式VDC用于SRAM存储器
公开(公告)号：US20100157692A1
公开(公告)日：2010-06-24
申请号：US12338732
申请日：2008-12-18
申请人： Li-Wen Wang , Yen-Huei Chen , Chen-Lin Yang , Hsien-Yu Pan , Shao-Yu Chou , Hung-Jen Liao
发明人： Li-Wen Wang , Yen-Huei Chen , Chen-Lin Yang , Hsien-Yu Pan , Shao-Yu Chou , Hung-Jen Liao
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C11/413 , G11C5/04 , G11C5/147
摘要： An integrated circuit structure includes a memory. The memory includes a first memory macro and a second memory macro identical to the first memory macro. A first power block is connected to the first memory macro and is configured to provide a regulated voltage to the first memory macro. The first power block has a first input and a first output. A second power block substantially identical to the first power block is connected to the second memory macro and is configured to provide the regulated voltage to the second memory macro. The second power block has a second input and a second output. The first input and the second input are interconnected. The first output and the second output are interconnected.
摘要翻译：集成电路结构包括存储器。存储器包括与第一存储器宏相同的第一存储器宏和第二存储器宏。第一功率块连接到第一存储器宏，并被配置为向第一存储器宏提供调节电压。第一功率块具有第一输入和第一输出。基本上与第一功率块相同的第二功率块连接到第二存储器宏，并且被配置为向第二存储器宏提供调节电压。第二功率块具有第二输入和第二输出。第一输入和第二输入互连。第一个输出和第二个输出相互连接。

7. 发明授权

US08358165B2 Ultra-low voltage level shifting circuit 有权
标题翻译：超低电压电平移位电路
公开(公告)号：US08358165B2
公开(公告)日：2013-01-22
申请号：US13308035
申请日：2011-11-30
申请人： Shao-Yu Chou , Yen-Huei Chen , Jui-Jen Wu
发明人： Shao-Yu Chou , Yen-Huei Chen , Jui-Jen Wu
IPC分类号： H03L5/00
CPC分类号： H03K3/356113 , H03K3/356182
摘要： A voltage level shifter having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) includes a first PMOS transistor and a second PMOS transistor each with a source connected to the VCCH, a gate of the first PMOS transistor being coupled to a drain of the second PMOS transistor, and a gate of the second PMOS transistor being coupled to a drain of the first PMOS transistor. The voltage level shifter further includes a first NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a first blocking device coupled between the drain of the first PMOS transistor and a drain of the first NMOS transistor, such that the voltage level shifter can operate at a lower VCCL.
摘要翻译：具有内部低电压电源（VCCL）和外部高压电源（VCCH）的电压电平移位器包括：第一PMOS晶体管和第二PMOS晶体管，每个PMOS晶体管和第二PMOS晶体管的源极连接到VCCH，第一PMOS晶体管的栅极耦合到第二PMOS晶体管的漏极，并且第二PMOS晶体管的栅极耦合到第一PMOS晶体管的漏极。电压电平移位器还包括第一NMOS晶体管，源极连接到地（VSS），栅极连接到在VCCL和VSS之间摆动的第一信号，以及耦合在第一PMOS晶体管的漏极之间的第一阻断装置以及第一NMOS晶体管的漏极，使得电压电平移位器可以在较低VCCL下工作。

8. 发明申请

US20120306537A1 ULTRA-LOW VOLTAGE LEVEL SHIFTING CIRCUIT 有权
标题翻译：超低电压电平移位电路
公开(公告)号：US20120306537A1
公开(公告)日：2012-12-06
申请号：US13308035
申请日：2011-11-30
申请人： Shao-Yu Chou , Yen-Huei Chen , Jui-Jen Wu
发明人： Shao-Yu Chou , Yen-Huei Chen , Jui-Jen Wu
IPC分类号： H03K19/0175
CPC分类号： H03K3/356113 , H03K3/356182
摘要： A voltage level shifter having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) includes a first PMOS transistor and a second PMOS transistor each with a source connected to the VCCH, a gate of the first PMOS transistor being coupled to a drain of the second PMOS transistor, and a gate of the second PMOS transistor being coupled to a drain of the first PMOS transistor. The voltage level shifter further includes a first NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a first blocking device coupled between the drain of the first PMOS transistor and a drain of the first NMOS transistor, such that the voltage level shifter can operate at a lower VCCL.
摘要翻译：具有内部低电压电源（VCCL）和外部高压电源（VCCH）的电压电平移位器包括：第一PMOS晶体管和第二PMOS晶体管，每个PMOS晶体管和第二PMOS晶体管的源极连接到VCCH，第一PMOS晶体管的栅极耦合到第二PMOS晶体管的漏极，并且第二PMOS晶体管的栅极耦合到第一PMOS晶体管的漏极。电压电平移位器还包括第一NMOS晶体管，源极连接到地（VSS），栅极连接到在VCCL和VSS之间摆动的第一信号，以及耦合在第一PMOS晶体管的漏极之间的第一阻断装置以及第一NMOS晶体管的漏极，使得电压电平移位器可以在较低VCCL下工作。

9. 发明授权

US08391097B2 Memory word-line driver having reduced power consumption 有权
标题翻译：存储器字线驱动器具有降低的功耗
公开(公告)号：US08391097B2
公开(公告)日：2013-03-05
申请号：US12786791
申请日：2010-05-25
申请人： Wei Min Chan , Yen-Huei Chen , Chen-Lin Yang , Hsiu-Hui Yang , Shao-Yu Chou
发明人： Wei Min Chan , Yen-Huei Chen , Chen-Lin Yang , Hsiu-Hui Yang , Shao-Yu Chou
IPC分类号： G11C11/34 , G11C7/00
CPC分类号： G11C16/30 , G11C8/08
摘要： A word-line driving circuit for driving a word-line in a memory array includes a NAND circuit having a pair of address inputs and an output, an output inverter circuit having an inverter power supply node, an input coupled to the output of the NAND circuit and an output for providing a word line signal, a power gate coupled between a first power supply node and the inverter power supply node, and a control circuit coupled to the power gate. The control circuit controls the power gate to place the word line driver circuit in active or standby mode in response to the output of the NAND circuit.
摘要翻译：用于驱动存储器阵列中的字线的字线驱动电路包括具有一对地址输入和输出的NAND电路，具有反相器电源节点的输出反相器电路，耦合到NAND的输出的输入电路和用于提供字线信号的输出，耦合在第一电源节点和逆变器电源节点之间的电源栅极以及耦合到电源门的控制电路。控制电路控制电源门以响应于NAND电路的输出将字线驱动电路置于有效或待机模式。

10. 发明申请

US20110292754A1 MEMORY WORD-LINE DRIVER HAVING REDUCED POWER CONSUMPTION 有权
标题翻译：具有降低功耗的存储器字线驱动器
公开(公告)号：US20110292754A1
公开(公告)日：2011-12-01
申请号：US12786791
申请日：2010-05-25
申请人： Wei Min Chan , Yen-Huei Chen , Chen-Lin Yang , Hsiu-Hui Yang , Shao-Yu Chou
发明人： Wei Min Chan , Yen-Huei Chen , Chen-Lin Yang , Hsiu-Hui Yang , Shao-Yu Chou
IPC分类号： G11C8/08
CPC分类号： G11C16/30 , G11C8/08
摘要： A word-line driving circuit for driving a word-line in a memory array includes a NAND circuit having a pair of address inputs and an output, an output inverter circuit having an inverter power supply node, an input coupled to the output of the NAND circuit and an output for providing a word line signal, a power gate coupled between a first power supply node and the inverter power supply node, and a control circuit coupled to the power gate. The control circuit controls the power gate to place the word line driver circuit in active or standby mode in response to the output of the NAND circuit.
摘要翻译：用于驱动存储器阵列中的字线的字线驱动电路包括具有一对地址输入和输出的NAND电路，具有反相器电源节点的输出反相器电路，耦合到NAND的输出的输入电路和用于提供字线信号的输出，耦合在第一电源节点和逆变器电源节点之间的电源栅极以及耦合到电源门的控制电路。控制电路控制电源门以响应于NAND电路的输出将字线驱动电路置于有效或待机模式。

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