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1. 发明授权

US08675418B2 Memory write assist 有权
标题翻译：内存写帮助
公开(公告)号：US08675418B2
公开(公告)日：2014-03-18
申请号：US12872135
申请日：2010-08-31
申请人： Jui-Jen Wu , Shau-Wei Lu , Robert Lo , Kun-Hsi Li
发明人： Jui-Jen Wu , Shau-Wei Lu , Robert Lo , Kun-Hsi Li
IPC分类号： G11C7/10
CPC分类号： G11C7/10 , G11C7/1015 , G11C11/412 , G11C11/413
摘要： A memory includes a memory cell, two word lines coupled to the memory cell, two bit lines coupled to the memory cell, and a write assist cell. The write assist cell is configured to transfer data of one bit line in a write operation to the other bit line in a read operation when one word line is used for the write operation, the other word line is used for the read operation, and the two word lines are asserted simultaneously.
摘要翻译：存储器包括存储器单元，耦合到存储器单元的两个字线，耦合到存储器单元的两个位线以及写入辅助单元。写入辅助单元被配置为当一个字线用于写入操作时，在读取操作中将写入操作中的一个位线的数据传送到另一个位线，另一个字线用于读取操作，并且两个字线同时被断言。

2. 发明授权

US08462540B2 Static random access memory cell 有权
标题翻译：静态随机存取存储单元
公开(公告)号：US08462540B2
公开(公告)日：2013-06-11
申请号：US13284532
申请日：2011-10-28
申请人： Meng-Fan Chang , Lai-Fu Chen , Jui-Jen Wu , Hiroyuki Yamauchi
发明人： Meng-Fan Chang , Lai-Fu Chen , Jui-Jen Wu , Hiroyuki Yamauchi
IPC分类号： G11C11/412
CPC分类号： G11C11/412
摘要： A static random access memory cell comprising a first inverter, a second inverter, a first transistor, a second transistor, and a third transistor. The first inverter is cross-coupled with the second inverter. The first transistor is connected with a write word line, a write bit line, and a first output node of the first inverter. The second transistor is connected with a complementary write bit line, the write word line, and a second output node of the second inverter. The third transistor is connected with a read bit line, a read word line, and the first input node of the first inverter to form a read port transistor, and a read port is formed. The read port transistor has a feature of asymmetric threshold voltage, and the read bit line swing can be expanded by the decrease of clamping current or the boosted read bit line.
摘要翻译：一种静态随机存取存储单元，包括第一反相器，第二反相器，第一晶体管，第二晶体管和第三晶体管。第一个反相器与第二个反相器交叉耦合。第一晶体管与第一反相器的写字线，写位线和第一输出节点连接。第二晶体管与第二反相器的互补写位线，写字线和第二输出节点连接。第三晶体管与读位线，读字线和第一反相器的第一输入节点连接，形成读端口晶体管，形成读端口。读端口晶体管具有不对称阈值电压的特征，并且可以通过钳位电流或升压读位线的减小来扩展读位线摆幅。

3. 发明申请

US20120243290A1 MULTI-LEVEL ELECTRICAL FUSE USING ONE PROGRAMMING DEVICE 有权
标题翻译：使用一个编程器件的多级电气保险丝
公开(公告)号：US20120243290A1
公开(公告)日：2012-09-27
申请号：US13492635
申请日：2012-06-08
申请人： Yung-Lung Lin , Jui-Jen Wu , Shine Chung , Fu-Lung Hsueh
发明人： Yung-Lung Lin , Jui-Jen Wu , Shine Chung , Fu-Lung Hsueh
IPC分类号： G11C17/16
CPC分类号： G11C11/5692 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A method for programming a multi-level electrical fuse system comprises providing a fuse box with an electrical fuse and providing one of at least two fuse writing voltages to the electrical fuse to program the electrical fuse to one of at least two resistance states. The fuse box comprises at least one electrical fuse, a programming device serially coupled to the electrical fuse, and a variable power supply coupled to the fuse box and configured to generate two or more voltage levels.
摘要翻译：一种用于编程多电平电熔丝系统的方法包括：提供具有电熔丝的保险丝盒，并向所述电熔丝提供至少两个熔丝写入电压中的一个，以将所述电熔丝编程为至少两个电阻状态之一。保险丝盒包括至少一个电熔丝，串联耦合到电熔丝的编程装置，以及耦合到保险丝盒并配置成产生两个或多个电压电平的可变电源。

4. 发明授权

US08233330B2 Sense amplifier used in the write operations of SRAM 有权
标题翻译：读写放大器用于SRAM的写操作
公开(公告)号：US08233330B2
公开(公告)日：2012-07-31
申请号：US12347140
申请日：2008-12-31
申请人： Jui-Jen Wu , Yi-Tzu Chen
发明人： Jui-Jen Wu , Yi-Tzu Chen
IPC分类号： G11C7/00
CPC分类号： G11C7/18 , G11C7/1012 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C11/413
摘要： A static random access memory (SRAM) circuit includes a pair of complementary global bit-lines, and a pair of complementary local bit-lines. A global read/write circuit is coupled to, and configured to write a small-swing signal to, the pair of global bit-lines in a write operation. The SRAM circuit further includes a first multiplexer and a second multiplexer, each having a first input and a second input. The first input of the first multiplexer and the first input of the second multiplexer are coupled to different one of the pair of global bit-lines. A sense amplifier includes a first input coupled to an output of the first multiplexer, and a second input coupled to an output of the second multiplexer. The sense amplifier is configured to amplify the small-swing signal to a full-swing signal, and outputs the full-swing signal to the pair of local bit-lines in the write operation.
摘要翻译：静态随机存取存储器（SRAM）电路包括一对互补的全局位线和一对互补局部位线。在写入操作中，全局读/写电路耦合到并配置成将小摆动信号写入该对全局位线。 SRAM电路还包括第一多路复用器和第二多路复用器，每个具有第一输入和第二输入。第一多路复用器的第一输入和第二多路复用器的第一输入耦合到该对全局位线中的不同的一个。读出放大器包括耦合到第一多路复用器的输出的第一输入和耦合到第二多路复用器的输出的第二输入。读出放大器被配置为将小摆动信号放大到全摆幅信号，并且在写入操作中将全摆幅信号输出到一对局部位线。

5. 发明申请

US20100123505A1 ULTRA-LOW VOLTAGE LEVEL SHIFTING CIRCUIT 有权
标题翻译：超低电压电平移位电路
公开(公告)号：US20100123505A1
公开(公告)日：2010-05-20
申请号：US12273365
申请日：2008-11-18
申请人： Shao-Yu Chou , Yen-Huei Chen , Jui-Jen Wu
发明人： Shao-Yu Chou , Yen-Huei Chen , Jui-Jen Wu
IPC分类号： H03L5/00
CPC分类号： H03K3/356113 , H03K3/356182
摘要： A voltage level shifting circuit for an integrated circuit system having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) is disclosed, the voltage level shifting circuit comprises a pair of cross coupled PMOS transistors connected to the VCCH, a NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a first blocking device coupled between the drain of the first PMOS transistor and a drain of the first NMOS transistor, the first blocking device being configured to conduct active current when the first signal is in static state or transitions from a logic HIGH to a logic LOW, and the first blocking device being configured to shut off active current when the first signal transitions from the logic LOW to the logic HIGH.
摘要翻译：公开了一种具有内部低压电源（VCCL）和外部高压电源（VCCH）的集成电路系统的电压电平移动电路，电压电平移位电路包括一对连接到VCCH的交叉耦合PMOS晶体管，具有连接到地（VSS）的源极和连接到在VCCL和VSS之间摆动的第一信号的栅极的NMOS晶体管，以及耦合在第一PMOS晶体管的漏极和第一PMOS晶体管的漏极之间的第一阻断装置 NMOS晶体管，所述第一阻断装置被配置为当所述第一信号处于静态或者从逻辑高电平转换到逻辑低电平时导通有源电流，并且所述第一阻断装置被配置为当所述第一信号从逻辑低电平为逻辑高电平。

6. 发明授权

US07577052B2 Power switching circuit 有权
标题翻译：电源开关电路
公开(公告)号：US07577052B2
公开(公告)日：2009-08-18
申请号：US11638187
申请日：2006-12-13
申请人： Jui-Jen Wu , Kun-Lung Chen , Hung-Jen Liao , Yung-Lung Lin , Chen Yen-Huei , Dao-Ping Wang
发明人： Jui-Jen Wu , Kun-Lung Chen , Hung-Jen Liao , Yung-Lung Lin , Chen Yen-Huei , Dao-Ping Wang
IPC分类号： G11C5/10
CPC分类号： G11C11/412 , G11C11/413
摘要： A power control circuit for an integrated circuit module includes at least one switch device coupled between a supply voltage and a power node of the integrated circuit module; and a switch control module having a first terminal coupled to the switch device, a second terminal coupled to a control signal, a third terminal coupled to a first storage node of at least one tracking cell, a fourth terminal coupled to a second storage node of the tracking cell, and a fifth terminal coupled to the power node of the integrated circuit module, for controlling the switch device to pass the supply voltage to the power node with or without a substantial voltage drop depending on an operation mode of the integrated circuit module.
摘要翻译：用于集成电路模块的功率控制电路包括耦合在电源电压和集成电路模块的功率节点之间的至少一个开关装置; 以及开关控制模块，其具有耦合到所述开关装置的第一端子，耦合到控制信号的第二端子，耦合到至少一个跟踪单元的第一存储节点的第三端子，耦合到所述至少一个跟踪单元的第二存储节点的第四端子跟踪单元和耦合到集成电路模块的功率节点的第五端子，用于根据集成电路模块的操作模式控制开关装置将电源电压传递到功率节点，具有或不具有实质的电压降。

7. 发明申请

US20080158939A1 MEMORY HAVING IMPROVED POWER DESIGN 有权
标题翻译：具有改进功率设计的记忆
公开(公告)号：US20080158939A1
公开(公告)日：2008-07-03
申请号：US11619103
申请日：2007-01-02
申请人： Yen-Huei Chen , Hung-Jen Liao , Kun-Lung Chen , Jui-Jen Wu , Yung-Lung Lin , Dao-Ping Wang
发明人： Yen-Huei Chen , Hung-Jen Liao , Kun-Lung Chen , Jui-Jen Wu , Yung-Lung Lin , Dao-Ping Wang
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C11/413
摘要： A memory includes a plurality of cells arranged in a matrix having a plurality of rows and a plurality of columns, wherein each cell is capable of storing a bit. Each cell is coupled between a first power supply node that receives a power supply voltage and a second power supply node that receives a second voltage. A plurality of word lines are associated with the memory cells and supplied by a third voltage in read or write operation. The third voltage is a suppressed power supply voltage. The second voltage is negative in read operation and positive in write operation.
摘要翻译：存储器包括以具有多个行和多个列的矩阵的形式排列的多个单元，其中每个单元能够存储位。每个单元耦合在接收电源电压的第一电源节点和接收第二电压的第二电源节点之间。多个字线与存储器单元相关联并且在读或写操作中由第三电压提供。第三电压是抑制电源电压。读操作中的第二电压为负，写操作为正。

8. 发明申请

US20050212527A1 Detecting the status of an electrical fuse 失效
标题翻译：检测电保险丝的状态
公开(公告)号：US20050212527A1
公开(公告)日：2005-09-29
申请号：US10810383
申请日：2004-03-26
申请人： Jui-Jen Wu
发明人： Jui-Jen Wu
IPC分类号： G01R31/02 , G01R31/07 , G11C17/16 , G11C29/02 , H02H7/00
CPC分类号： G11C29/02 , G01R31/07 , G11C17/16 , G11C29/027
摘要： A fuse detection circuit has; a fuse (102) under detection to produce a first voltage in the first arm in response to a read signal; a reference fuse (108) to produce a second voltage in response to the read signal; a sensing circuit (124) to sense the first voltage and the second voltage as status value data of the fuse under detection; a latch circuit (136) to keep the data in the sensing circuit; and a timing control circuit (138) to turn off the fuse bridge circuit independently of the read signal.
摘要翻译：保险丝检测电路具有：检测到的熔丝（102），以响应于读取信号在第一臂中产生第一电压; 参考熔丝（108），用于响应于读取信号产生第二电压; 感测电路（124），用于感测第一电压和第二电压作为被检测的熔丝的状态值数据; 锁存电路（136），用于将数据保持在感测电路中; 以及定时控制电路（138），以独立于读取信号来关断熔丝桥电路。

9. 发明申请

US20130107609A1 Static Random Access Memory Cell 有权
标题翻译：静态随机存取存储单元
公开(公告)号：US20130107609A1
公开(公告)日：2013-05-02
申请号：US13284532
申请日：2011-10-28
申请人： Meng-Fan Chang , Lai-Fu Chen , Jui-Jen Wu , Hiroyuki Yamauchi
发明人： Meng-Fan Chang , Lai-Fu Chen , Jui-Jen Wu , Hiroyuki Yamauchi
IPC分类号： G11C11/40
CPC分类号： G11C11/412
摘要： A static random access memory cell comprising a first inverter, a second inverter, a first transistor, a second transistor, and a third transistor. The first inverter is cross-coupled with the second inverter. The first transistor is connected with a write word line, a write bit line, and a first output node of the first inverter. The second transistor is connected with a complementary write bit line, the write word line, and a second output node of the second inverter. The third transistor is connected with a read bit line, a read word line, and the first input node of the first inverter to form a read port transistor, and a read port is formed. The read port transistor has a feature of asymmetric threshold voltage, and the read bit line swing can be expanded by the decrease of clamping current or the boosted read bit line.
摘要翻译：一种静态随机存取存储单元，包括第一反相器，第二反相器，第一晶体管，第二晶体管和第三晶体管。第一个反相器与第二个反相器交叉耦合。第一晶体管与第一反相器的写字线，写位线和第一输出节点连接。第二晶体管与第二反相器的互补写位线，写字线和第二输出节点连接。第三晶体管与读位线，读字线和第一反相器的第一输入节点连接，形成读端口晶体管，形成读端口。读端口晶体管具有不对称阈值电压的特征，并且可以通过钳位电流或升压读位线的减小来扩展读位线摆幅。

10. 发明授权

US08223575B2 Multi-level electrical fuse using one programming device 有权
标题翻译：使用一个编程设备的多级电气保险丝
公开(公告)号：US08223575B2
公开(公告)日：2012-07-17
申请号：US11715631
申请日：2007-03-08
申请人： Yung-Lung Lin , Jui-Jen Wu , Shine Chung , Fu-Lung Hsuen
发明人： Yung-Lung Lin , Jui-Jen Wu , Shine Chung , Fu-Lung Hsuen
IPC分类号： G11C17/18 , G11C17/14 , G11C17/16 , G11C17/00
CPC分类号： G11C11/5692 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A multi-level electrical fuse system comprises at least one fuse box having at least one electrical fuse, a programming device serially coupled to the electrical fuse, and a variable power supply coupled to the fuse box and configured to generate two or more voltage levels.
摘要翻译：多级电熔丝系统包括至少一个具有至少一个电熔丝的保险丝盒，串联耦合到电熔丝的编程装置，以及耦合到保险丝盒并被配置为产生两个或多个电压电平的可变电源。

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