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1. 发明授权

US08837250B2 Method and apparatus for word line decoder layout 有权
标题翻译：字线解码器布局的方法和装置
公开(公告)号：US08837250B2
公开(公告)日：2014-09-16
申请号：US12839490
申请日：2010-07-20
申请人： You-Cheng Xiao , Hong-Chen Cheng , Chung-Ji Lu , Cheng Hung Lee , Jung-Hsuan Chen , Li-Chun Tien
发明人： You-Cheng Xiao , Hong-Chen Cheng , Chung-Ji Lu , Cheng Hung Lee , Jung-Hsuan Chen , Li-Chun Tien
IPC分类号： G11C8/10
CPC分类号： G11C8/10 , G11C11/413
摘要： A word line decoder comprises a plurality of driver circuits, a plurality of word lines provided at respective outputs of the driver circuits, and a plurality of primary input lines coupled to the driver circuits and oriented in a first direction. The word line decoder also comprises a plurality of secondary input lines coupled to the driver circuits and oriented in the first direction. The word line decoder also comprises a local decode line coupled to each of the primary input lines. The word line decoder also comprises a decode line coupled to the local decode line and oriented in the first direction. A cluster decode line is coupled to the decode line. The word line decoder is configured to select at least one of the word lines based on signals provided by the cluster decode line and the secondary input lines.
摘要翻译：字线解码器包括多个驱动器电路，设置在驱动器电路的各个输出处的多个字线以及耦合到驱动器电路并沿第一方向取向的多个主输入线。字线解码器还包括耦合到驱动器电路并沿第一方向定向的多个次级输入线。字线解码器还包括耦合到每个主输入线的本地解码线。字线解码器还包括耦合到本地解码线并沿第一方向定向的解码线。集群解码线耦合到解码线。字线解码器被配置为基于由群集解码线和辅助输入线提供的信号来选择至少一个字线。

2. 发明授权

US08692333B2 Semiconductor device for word line driver with efficient routing of conductor for decreased gate resistance 有权
标题翻译：用于字线驱动器的半导体器件，具有用于降低栅极电阻的导体的有效布线
公开(公告)号：US08692333B2
公开(公告)日：2014-04-08
申请号：US12855004
申请日：2010-08-12
申请人： Yen-Huei Chen , You-Cheng Xiao , Jung-Hsuan Chen , Shao-Yu Chou
发明人： Yen-Huei Chen , You-Cheng Xiao , Jung-Hsuan Chen , Shao-Yu Chou
IPC分类号： H01L29/76
CPC分类号： H01L21/82385 , G11C8/08 , G11C8/14
摘要： A semiconductor device comprises first, second, and third. The first conductor is a gate conductor formed above an oxide region over a substrate and having a contact. The second conductor is coupled to the contact and extends across a width of the oxide region. The second conductor has a lower resistance than the gate conductor. The third conductor is a word line conductor. The second conductor is routed to not intersect the word line conductor.
摘要翻译：半导体器件包括第一，第二和第三。第一导体是形成在衬底上方并具有接触的氧化物区域上方的栅极导体。第二导体耦合到触点并延伸穿过氧化物区域的宽度。第二导体的电阻低于栅极导体。第三导体是字线导体。第二个导体被路由到不与字线导体相交。

3. 发明授权

US08610236B2 Edge devices layout for improved performance 有权
标题翻译：边缘设备布局，以提高性能
公开(公告)号：US08610236B2
公开(公告)日：2013-12-17
申请号：US12851702
申请日：2010-08-06
申请人： Yen-Huei Chen , Jung-Hsuan Chen , Shao-Yu Chou , Hung-Jen Liao , Li-Chun Tien
发明人： Yen-Huei Chen , Jung-Hsuan Chen , Shao-Yu Chou , Hung-Jen Liao , Li-Chun Tien
IPC分类号： H01L27/08
CPC分类号： H01L21/28008 , H01L21/28123 , H01L21/823425 , H01L21/823481 , H01L27/0207 , H01L29/66628 , H01L29/7848
摘要： A word line driver includes an active area having a length that extends in a first direction over a semiconductor substrate. A plurality of fingers formed over an upper surface of the active area. Each of the plurality of fingers has a length that extends in a second direction and forms a MOS transistor with a portion of the active area. A first dummy structure is disposed between an outer one of the plurality of fingers and an edge of the semiconductor substrate. The first dummy structure includes a portion that is at least partially disposed over a portion of the active area.
摘要翻译：字线驱动器包括具有沿半导体衬底的第一方向延伸的长度的有源区。多个指状物形成在有源区域的上表面上。多个指状物中的每一个具有在第二方向上延伸的长度，并且形成具有有效区域的一部分的MOS晶体管。第一虚设结构设置在多个指状物的外部之一和半导体衬底的边缘之间。第一虚拟结构包括至少部分地设置在有效区域的一部分上的部分。

4. 发明申请

US20120181707A1 Distributed Metal Routing 有权
标题翻译：分布式金属路由
公开(公告)号：US20120181707A1
公开(公告)日：2012-07-19
申请号：US13007235
申请日：2011-01-14
申请人： You-Cheng Xiao , Yen-Huei Chen , Jung-Hsuan Chen , Shao-Yu Chou , Li-Chun Tien , Hung-Jen Liao
发明人： You-Cheng Xiao , Yen-Huei Chen , Jung-Hsuan Chen , Shao-Yu Chou , Li-Chun Tien , Hung-Jen Liao
IPC分类号： H01L23/48 , H01L21/28
CPC分类号： H01L21/76879 , H01L21/768 , H01L21/76832 , H01L23/4824 , H01L23/485 , H01L23/522 , H01L23/528 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias.
摘要翻译：公开了一种用于分布式金属布线的系统和方法。一个实施例包括具有覆盖在metal_0层上的metal_1层的metal_0层。金属层1包括分开的平行线，具有不同信号的线分布在metal_1层上。这样的布局减小了metal_0层内的寄生电阻，因为它减小了电流行进的距离。此外，metal_1中的分布式布局允许连接到metal_2层，而不需要通孔的锤头连接。

5. 发明授权

US08928113B2 Layout scheme and method for forming device cells in semiconductor devices 有权
标题翻译：用于在半导体器件中形成器件单元的布局方案和方法
公开(公告)号：US08928113B2
公开(公告)日：2015-01-06
申请号：US13082497
申请日：2011-04-08
申请人： Hsien-Yu Pan , Jung-Hsuan Chen , Shao-Yu Chou , Yen-Huei Chen , Hung-Jen Liao
发明人： Hsien-Yu Pan , Jung-Hsuan Chen , Shao-Yu Chou , Yen-Huei Chen , Hung-Jen Liao
IPC分类号： H01L23/52 , H01L27/108 , H01L29/94 , H01L21/70 , H01L27/02 , H01L27/11 , H01L27/118
CPC分类号： H01L27/1116 , H01L21/768 , H01L27/0207 , H01L27/11 , H01L2027/11887
摘要： A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.
摘要翻译：用于形成字线解码器装置和具有字线解码器单元的其它装置的方法和布局提供了使用非DPL光刻操作形成金属互连层，并且使用下部或中间金属层或下部导电材料提供了用于缝合的远端布置的晶体管。晶体管可以设置在纵向布置的字线解码器或其他单元中或其附近，并且使用金属或导电材料的导电耦合降低晶体管之间的栅极电阻并避免RC信号延迟。

6. 发明授权

US08816403B2 Efficient semiconductor device cell layout utilizing underlying local connective features 有权
标题翻译：利用潜在的本地连接特征的高效半导体器件单元布局
公开(公告)号：US08816403B2
公开(公告)日：2014-08-26
申请号：US13238294
申请日：2011-09-21
申请人： Jung-Hsuan Chen , May Chang , Chiting Cheng , Li-Chun Tien
发明人： Jung-Hsuan Chen , May Chang , Chiting Cheng , Li-Chun Tien
IPC分类号： H01L27/118 , H01L23/522
CPC分类号： H01L27/0207 , H01L2027/11859
摘要： Provided are semiconductor device cells, methods for forming the semiconductor device cells and a layout style for the semiconductor device cells. The device cells may be repetitive cells used throughout an integrated circuit. The layout style utilizes an area at the polysilicon level that is void of polysilicon and which can accommodate conductive leads therein or thereover. The conductive leads are formed of material typically used for contacts or vias and are disposed beneath the first metal interconnect level which couples device cells to one another. The subjacent local conductive leads may form subjacent signal lines allowing for additional power mesh lines to be included within the limited number of metal tracks that can be accommodated within a device cell and in accordance with metal track design spacing rules.
摘要翻译：提供半导体器件单元，用于形成半导体器件单元的方法和用于半导体器件单元的布局样式。器件单元可以是整个集成电路中使用的重复单元。布局样式利用多晶硅级别的无多晶硅的区域，并且可以容纳其中或其中的导电引线。导电引线由通常用于触点或通孔的材料形成，并且设置在将器件单元彼此耦合的第一金属互连级之下。下面的局部导电引线可以形成下面的信号线，允许额外的功率网线包括在可以容纳在器件单元内并根据金属轨道设计间隔规则的有限数量的金属轨道内。

7. 发明授权

US08482990B2 Memory edge cell 有权
标题翻译：内存边缘单元格
公开(公告)号：US08482990B2
公开(公告)日：2013-07-09
申请号：US13025872
申请日：2011-02-11
申请人： Hong-Chen Cheng , Ming-Yi Lee , Kuo-Hua Pan , Jung-Hsuan Chen , Li-Chun Tien , Cheng Hung Lee , Hung-Jen Liao
发明人： Hong-Chen Cheng , Ming-Yi Lee , Kuo-Hua Pan , Jung-Hsuan Chen , Li-Chun Tien , Cheng Hung Lee , Hung-Jen Liao
IPC分类号： G11C7/10
CPC分类号： G11C5/06 , G11C5/147 , G11C5/148 , G11C11/417
摘要： A circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The PMOS transistors and the NMOS transistors are configured to provide a first voltage reference node having a first reference voltage and a second voltage reference node having a second reference voltage. The first reference voltage and the second reference voltage serve as a first reference voltage and a second reference voltage for a memory cell, respectively.
摘要翻译：电路包括第一PMOS晶体管，第二PMOS晶体管，第一NMOS晶体管，第二NMOS晶体管，第三NMOS晶体管和第四NMOS晶体管。 PMOS晶体管和NMOS晶体管被配置为提供具有第一参考电压的第一电压参考节点和具有第二参考电压的第二参考电压节点。第一参考电压和第二参考电压分别用作存储器单元的第一参考电压和第二参考电压。

8. 发明授权

US08437166B1 Word line driver cell layout for SRAM and other semiconductor devices 有权
标题翻译：用于SRAM和其他半导体器件的字线驱动器单元布局
公开(公告)号：US08437166B1
公开(公告)日：2013-05-07
申请号：US13297296
申请日：2011-11-16
申请人： Shu Cheng Huang , Hsin-Hsin Ko , Jung-Hsuan Chen , Chiting Cheng
发明人： Shu Cheng Huang , Hsin-Hsin Ko , Jung-Hsuan Chen , Chiting Cheng
IPC分类号： G11C5/06
CPC分类号： G11C11/413
摘要： A word line driver cell suitable for RAM devices such as SRAM, static random access memory devices, is provided. The word line driver cell is compatible with double pattern processing techniques and enables the formation of all word lines from a single metal layer which, in turn, enables overlying and underlying metal levels to be used for other features such as signal lines for word line decoders. A power mesh is formed using multiple metal layers and the formation of all the word lines from a single metal layer enables VDD and VSS power lines that are formed from an overlying layer to extend orthogonal to the cell direction and include wider widths reducing metal line resistance and increasing the deliverable power.
摘要翻译：提供了适用于诸如SRAM，静态随机存取存储器件等RAM装置的字线驱动单元。字线驱动器单元与双模式处理技术兼容，并且能够从单个金属层形成所有字线，这又可以使覆盖和下层金属电平用于其他特征，例如用于字线解码器的信号线。使用多个金属层形成功率网，并且从单个金属层形成所有字线使得由上层形成的VDD和VSS电源线能够垂直于电池方向延伸并且包括较宽的宽度，从而减小金属线路电阻并增加可交付的能力。

9. 发明申请

US20120032293A1 EDGE DEVICES LAYOUT FOR IMPROVED PERFORMANCE 有权
标题翻译：边缘设备布局改善性能
公开(公告)号：US20120032293A1
公开(公告)日：2012-02-09
申请号：US12851702
申请日：2010-08-06
申请人： Yen-Huei CHEN , Jung-Hsuan CHEN , Shao-Yu CHOU , Hung-Jen LIAO , Li-Chun TIEN
发明人： Yen-Huei CHEN , Jung-Hsuan CHEN , Shao-Yu CHOU , Hung-Jen LIAO , Li-Chun TIEN
IPC分类号： H01L27/08 , H01L21/822
CPC分类号： H01L21/28008 , H01L21/28123 , H01L21/823425 , H01L21/823481 , H01L27/0207 , H01L29/66628 , H01L29/7848
摘要： A word line driver includes an active area having a length that extends in a first direction over a semiconductor substrate. A plurality of fingers formed over an upper surface of the active area. Each of the plurality of fingers has a length that extends in a second direction and forms a MOS transistor with a portion of the active area. A first dummy structure is disposed between an outer one of the plurality of fingers and an edge of the semiconductor substrate. The first dummy structure includes a portion that is at least partially disposed over a portion of the active area.
摘要翻译：字线驱动器包括具有沿半导体衬底的第一方向延伸的长度的有源区。多个指状物形成在有源区域的上表面上。多个指状物中的每一个具有在第二方向上延伸的长度，并且形成具有有效区域的一部分的MOS晶体管。第一虚设结构设置在多个指状物的外部之一和半导体衬底的边缘之间。第一虚拟结构包括至少部分地设置在有效区域的一部分上的部分。

10. 发明授权

US07960258B2 Method for fabricating nanoscale thermoelectric device 有权
标题翻译：制造纳米级热电装置的方法
公开(公告)号：US07960258B2
公开(公告)日：2011-06-14
申请号：US12117835
申请日：2008-05-09
申请人： Chuen-Guang Chao , Jung-Hsuan Chen , Ta-Wei Yang
发明人： Chuen-Guang Chao , Jung-Hsuan Chen , Ta-Wei Yang
IPC分类号： H01L21/00
CPC分类号： B82Y30/00 , B82Y10/00 , H01L35/32 , H01L35/34 , Y10S977/70 , Y10S977/762 , Y10S977/781 , Y10S977/833 , Y10S977/888
摘要： The present invention discloses a method for fabricating a nanoscale thermoelectric device, which comprises steps: providing at least one template having a group of nanoscale pores; forming a substrate on the bottom of the template; injecting a molten semiconductor material into the nanoscale pores to form a group of semiconductor nanoscale wires; removing the substrate to obtain a semiconductor nanoscale wire array; and using metallic conductors to cascade at least two semiconductor nanoscale wire arrays to form a thermoelectric device having a higher thermoelectric conversion efficiency.
摘要翻译：本发明公开了一种制造纳米尺度热电装置的方法，包括以下步骤：提供至少一个具有一组纳米级孔的模板; 在模板的底部形成衬底; 将熔融的半导体材料注入到纳米尺度的孔中以形成一组半导体纳米线; 去除衬底以获得半导体纳米级线阵列; 并且使用金属导体级联至少两个半导体纳米级线阵列以形成具有较高热电转换效率的热电装置。

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