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1. 发明授权

US09041069B2 Distributed metal routing 有权
标题翻译：分布式金属布线
公开(公告)号：US09041069B2
公开(公告)日：2015-05-26
申请号：US13007235
申请日：2011-01-14
申请人： You-Cheng Xiao , Yen-Huei Chen , Jung-Hsuan Chen , Shao-Yu Chou , Li-Chun Tien , Hung-Jen Liao
发明人： You-Cheng Xiao , Yen-Huei Chen , Jung-Hsuan Chen , Shao-Yu Chou , Li-Chun Tien , Hung-Jen Liao
IPC分类号： H01L23/52 , H01L23/485 , H01L23/528 , H01L23/482 , H01L23/522
CPC分类号： H01L21/76879 , H01L21/768 , H01L21/76832 , H01L23/4824 , H01L23/485 , H01L23/522 , H01L23/528 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias.
摘要翻译：公开了一种用于分布式金属布线的系统和方法。一个实施例包括具有覆盖在metal_0层上的metal_1层的metal_0层。金属层1包括分开的平行线，具有不同信号的线分布在metal_1层上。这样的布局减小了metal_0层内的寄生电阻，因为它减小了电流行进的距离。此外，metal_1中的分布式布局允许连接到metal_2层，而不需要通孔的锤头连接。

2. 发明申请

US20140029358A1 MEMORY DEVICE AND METHOD FOR WRITING THEREFOR 有权
标题翻译：存储器件及其写入方法
公开(公告)号：US20140029358A1
公开(公告)日：2014-01-30
申请号：US13562222
申请日：2012-07-30
申请人： Yen-Huei CHEN , Li-Wen WANG , Chih-Yu LIN
发明人： Yen-Huei CHEN , Li-Wen WANG , Chih-Yu LIN
IPC分类号： G11C7/12
CPC分类号： G11C7/22 , G11C7/12 , G11C11/419
摘要： A method for writing a memory cell in a specific write cycle is provided. The method includes the following steps: providing a first signal having a first transition edge in the specific write cycle; providing a second signal having a second transition edge in the specific write cycle, wherein the second transition edge lags behind the first transition edge; providing a first voltage level to the memory cell; and lowering the first voltage level to a second voltage level in the specific write cycle for writing the memory cell in response to the second transition edge. A memory device is also provided.
摘要翻译：提供了一种用于在特定写入周期中写入存储器单元的方法。该方法包括以下步骤：提供在特定写周期中具有第一过渡边缘的第一信号; 提供在所述特定写周期中具有第二过渡边缘的第二信号，其中所述第二过渡边缘滞后于所述第一过渡边缘; 向所述存储器单元提供第一电压电平; 以及在所述特定写入周期中将所述第一电压电平降低到第二电压电平，以响应于所述第二过渡沿来写入所述存储器单元。还提供存储器件。

3. 发明申请

US20130263066A1 Pre-Colored Methodology of Multiple Patterning 有权
标题翻译：多种图案预色彩方法
公开(公告)号：US20130263066A1
公开(公告)日：2013-10-03
申请号：US13607946
申请日：2012-09-10
申请人： Yen-Huei Chen , Hung-Jen Liao , Jonathan Tsung-Yung Chang
发明人： Yen-Huei Chen , Hung-Jen Liao , Jonathan Tsung-Yung Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： Some embodiments relate to a method of pre-coloring word lines and control lines within an SRAM integrated chip design to avoid timing delays that result from processing variations introduced through multiple patterning lithography processes. The method is performed by generating a graphical IC layout file having an SRAM circuit with a plurality of word lines and Y-control lines. The word lines and Y-control lines are assigned a color during decomposition. The word lines and Y-control lines are further pre-colored in a manner that deliberately assigns the pre-colored data to a same mask. Therefore, during mask building, data associated with pre-colored word and Y-control lines is sent to a same mask, regardless of the colors that are assigned to the data. By assigning word and Y-control lines to a same mask through pre-coloring, processing variations between the word and Y-control lines are minimized, thereby mitigating timing variations in an SRAM circuit.
摘要翻译：一些实施例涉及在SRAM集成芯片设计中预先着色字线和控制线的方法，以避免由通过多次图案化光刻工艺引入的处理变化而产生的定时延迟。该方法通过生成具有多个字线和Y控制线的SRAM电路的图形IC布局文件来执行。在分解过程中，字线和Y控制线被分配一个颜色。字线和Y控制线进一步预先着色，以故意将预色数据分配给相同的掩码。因此，在面具构建期间，与预色彩字和Y控制线相关联的数据被发送到相同的掩码，而不管分配给数据的颜色如何。通过预分色将字和Y控制线分配给相同的掩码，字和Y控制线之间的处理变化被最小化，从而减轻SRAM电路中的定时变化。

4. 发明申请

US20130188433A1 MEMORY CIRCUIT AND METHOD OF WRITING DATUM TO MEMORY CIRCUIT 有权
标题翻译：存储器电路和将数据写入存储器电路的方法
公开(公告)号：US20130188433A1
公开(公告)日：2013-07-25
申请号：US13354884
申请日：2012-01-20
申请人： Chih-Yu LIN , Wei Min CHAN , Yen-Huei CHEN , Hung-Jen LIAO , Jonathan Tsung-Yung CHANG
发明人： Chih-Yu LIN , Wei Min CHAN , Yen-Huei CHEN , Hung-Jen LIAO , Jonathan Tsung-Yung CHANG
IPC分类号： G11C7/00
CPC分类号： G11C11/419
摘要： A circuit includes a first node, a second node, a memory cell, a first data line, a second data line, and a write driver. The memory cell is coupled to the first node and the second node and powered by a first voltage at the first node and a second voltage at the second node. The first data line and the second data line are coupled to the memory cell. The write driver has a third node carrying a third voltage less than the first voltage during a write operation. The write deriver is coupled to the first data line and the second data line and configured to, during a write operation, selectively coupling one of the first data line and the second data line to the third node and coupling the other one of the first data line and the second data line to the first node.
摘要翻译：电路包括第一节点，第二节点，存储器单元，第一数据线，第二数据线和写驱动器。存储器单元耦合到第一节点和第二节点，并由第一节点处的第一电压和第二节点处的第二电压供电。第一数据线和第二数据线耦合到存储器单元。写入驱动器具有在写入操作期间承载小于第一电压的第三电压的第三节点。写引导器耦合到第一数据线和第二数据线，并且被配置为在写操作期间，选择性地将第一数据线和第二数据线之一耦合到第三节点，并将第一数据中的另一个耦合线和第二条数据线到第一个节点。

5. 发明授权

US08363454B2 SRAM bit cell 有权
标题翻译： SRAM位单元
公开(公告)号：US08363454B2
公开(公告)日：2013-01-29
申请号：US13015773
申请日：2011-01-28
申请人： Ping Wang , Hung-Jen Liao , Yen-Huei Chen , Jihi-Yu Lin , Shao-Yu Chou
发明人： Ping Wang , Hung-Jen Liao , Yen-Huei Chen , Jihi-Yu Lin , Shao-Yu Chou
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A semiconductor memory bit cell includes an inverter latch including a pair of cross-coupled inverters. A first transistor has a gate coupled to a first control line and a source coupled to the inverter latch, and a second transistor has a gate coupled to a second control line and a drain coupled to the drain of the first transistor at a first node. A third transistor has a source coupled to the first node and a gate coupled to a word line, and a fourth transistor has a gate coupled to a source of the second transistor and to the inverter latch. A fifth transistor has a gate coupled to the word line and a drain coupled to a read bit line.
摘要翻译：半导体存储器位单元包括具有一对交叉耦合的反相器的反相器锁存器。第一晶体管具有耦合到第一控制线的栅极和耦合到反相器锁存器的源极，并且第二晶体管具有耦合到第二控制线的栅极和在第一节点耦合到第一晶体管的漏极的漏极。第三晶体管具有耦合到第一节点的源极和耦合到字线的栅极，并且第四晶体管具有耦合到第二晶体管的源极和反相器锁存器的栅极。第五晶体管具有耦合到字线的栅极和耦合到读位线的漏极。

6. 发明申请

US20130010544A1 LEAKAGE-AWARE KEEPER FOR SEMICONDUCTOR MEMORY 有权
标题翻译：漏电保护器用于半导体存储器
公开(公告)号：US20130010544A1
公开(公告)日：2013-01-10
申请号：US13177711
申请日：2011-07-07
申请人： Jihi-Yu LIN , Li-Wen Wang , Wei Min Chan , Yen-Huei Chen
发明人： Jihi-Yu LIN , Li-Wen Wang , Wei Min Chan , Yen-Huei Chen
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/04 , G11C11/417
摘要： A circuit includes a first circuit configured to sense a leakage of a first bit line and output a first signal in response, and a second circuit configured to receive the first signal output from the first circuit and in response supply current to a second bit line for maintaining a voltage level of the second bit line.
摘要翻译：电路包括被配置为感测第一位线的泄漏并响应地输出第一信号的第一电路，以及被配置为接收从第一电路输出的第一信号并且响应于向第二位线提供电流的第二电路，维持第二位线的电压电平。

7. 发明授权

US08305832B2 Integrated circuits, systems, and methods for reducing leakage currents in a retention mode 有权
公开(公告)号：US08305832B2
公开(公告)日：2012-11-06
申请号：US13397102
申请日：2012-02-15
申请人： Yen-Huei Chen , Cheng Hung Lee
发明人： Yen-Huei Chen , Cheng Hung Lee
IPC分类号： G11C5/14
CPC分类号： G11C11/413 , G11C11/412
摘要： An integrated circuit includes at least one memory array for storing data. A first switch is coupled with the memory array. A first power line is coupled with the first switch. The first power line is operable to supply a first power voltage. A second switch is coupled with the memory array. A second power line is coupled with the second switch. The second power line is operable to supply a second power voltage for retaining the data during a retention mode. A third power line is coupled with the memory array. The third power line is capable of providing a third power voltage.

8. 发明申请

US20120258592A1 Layouts of POLY Cut Openings Overlapping Active Regions 有权
标题翻译： POLY切割开关重叠活动区域的布局
公开(公告)号：US20120258592A1
公开(公告)日：2012-10-11
申请号：US13081115
申请日：2011-04-06
申请人： Jung-Hsuan Chen , Yen-Huei Chen , Li-Chun Tien , Hung-Jen Liao
发明人： Jung-Hsuan Chen , Yen-Huei Chen , Li-Chun Tien , Hung-Jen Liao
IPC分类号： H01L21/28
CPC分类号： H01L21/32139 , H01L21/76816
摘要： A method of forming integrated circuits includes forming a mask layer over a gate electrode line, wherein the gate electrode line is over a well region of a semiconductor substrate; forming an opening in the mask layer, wherein a portion of the gate electrode line and a well pickup region of the well region are exposed through the opening; and removing the portion of the gate electrode line through the opening.
摘要翻译：形成集成电路的方法包括在栅电极线上形成掩模层，其中栅电极线在半导体衬底的阱区之上; 在所述掩模层中形成开口，其中所述栅电极线的一部分和所述阱区的阱拾取区域通过所述开口露出; 并且通过所述开口去除所述栅电极线的所述部分。

9. 发明申请

US20120256235A1 LAYOUT SCHEME AND METHOD FOR FORMING DEVICE CELLS IN SEMICONDUCTOR DEVICES 有权
标题翻译：用于在半导体器件中形成器件电池的布局方案和方法
公开(公告)号：US20120256235A1
公开(公告)日：2012-10-11
申请号：US13082497
申请日：2011-04-08
申请人： Hsien-Yu Pan , Jung-Hsuan Chen , Shao-Yu Chou , Yen-Huei Chen , Hung-Jen Liao
发明人： Hsien-Yu Pan , Jung-Hsuan Chen , Shao-Yu Chou , Yen-Huei Chen , Hung-Jen Liao
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L27/1116 , H01L21/768 , H01L27/0207 , H01L27/11 , H01L2027/11887
摘要： A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.
摘要翻译：用于形成字线解码器装置和具有字线解码器单元的其它装置的方法和布局提供了使用非DPL光刻操作形成金属互连层，并且使用下部或中间金属层或下部导电材料提供了用于缝合的远端布置的晶体管。晶体管可以设置在纵向布置的字线解码器或其他单元中或其附近，并且使用金属或导电材料的导电耦合降低晶体管之间的栅极电阻并避免RC信号延迟。

10. 发明授权

US08139436B2 Integrated circuits, systems, and methods for reducing leakage currents in a retention mode 有权
标题翻译：用于在保持模式下减少漏电流的集成电路，系统和方法
公开(公告)号：US08139436B2
公开(公告)日：2012-03-20
申请号：US12716363
申请日：2010-03-03
申请人： Yen-Huei Chen , Cheng Hung Lee
发明人： Yen-Huei Chen , Cheng Hung Lee
IPC分类号： G11C5/14
CPC分类号： G11C11/413 , G11C11/412
摘要： An integrated circuit includes at least one memory array for storing data. A first switch is coupled with the memory array. A first power line is coupled with the first switch. The first power line is operable to supply a first power voltage. A second switch is coupled with the memory array. A second power line is coupled with the second switch. The second power line is operable to supply a second power voltage for retaining the data during a retention mode. A third power line is coupled with the memory array. The third power line is capable of providing a third power voltage.
摘要翻译：集成电路包括用于存储数据的至少一个存储器阵列。第一开关与存储器阵列耦合。第一电力线与第一开关耦合。第一电力线可操作以提供第一电力电压。第二开关与存储器阵列耦合。第二电源线与第二开关耦合。第二电源线可操作以在保持模式期间提供用于保留数据的第二电源电压。第三电源线与存储器阵列耦合。第三电源线能够提供第三电源电压。

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