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1. 发明授权

US08990751B2 Computer system and method of preparing a layout 有权
标题翻译：计算机系统及其布局方法
公开(公告)号：US08990751B2
公开(公告)日：2015-03-24
申请号：US12913949
申请日：2010-10-28
申请人： Chen-Lin Yang , Wei Min Chan
发明人： Chen-Lin Yang , Wei Min Chan
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5009 , G06F17/5068
摘要： The present application discloses a method of preparing a layout for manufacturing an integrated circuit chip according to a circuit design. In at least one embodiment, a pattern for the layout based on the circuit design is generated. After the generation of the pattern, it is determined if at least one layout rule is violated in the layout, the at least one layout rule being specified according to a predetermined maximum value for at least one of an estimated voltage drop along a signal path in the layout or an estimated current density on the signal path. If the at least one layout rule is violated, a violation is indicated.
摘要翻译：本申请公开了根据电路设计制备用于制造集成电路芯片的布局的方法。在至少一个实施例中，生成用于基于电路设计的布局的图案。在生成图案之后，确定在布局中是否违反了至少一个布局规则，根据预定的最大值来指定至少一个布局规则，用于沿着信号路径的估计电压降中的至少一个信号路径上的布局或估计的电流密度。如果违反了至少一个布局规则，则会显示违规。

2. 发明授权

US08767493B2 SRAM differential voltage sensing apparatus 有权
标题翻译： SRAM差分电压检测装置
公开(公告)号：US08767493B2
公开(公告)日：2014-07-01
申请号：US13169511
申请日：2011-06-27
申请人： Yen-Huei Chen , Kun-hsi Li , Shao-Yu Chou , Hung-Jen Liao , Wei Min Chan
发明人： Yen-Huei Chen , Kun-hsi Li , Shao-Yu Chou , Hung-Jen Liao , Wei Min Chan
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/062 , G11C11/419
摘要： An SRAM differential voltage sensing apparatus is coupled to a memory circuit. The memory circuit comprises a memory bank, a plurality of bit lines, a plurality of data lines coupled to the plurality of bit lines via a plurality of transmission gates and a sense amplifier. When the sense amplifier operates in a characterization mode, the transmission gates and pre-charge circuits are turned off. The differential voltage sensing apparatus applies a characterization signal to the sense amplifier and obtains the parameters of the memory circuit through a trial and error process.
摘要翻译： SRAM差分电压感测装置耦合到存储器电路。存储器电路包括存储体，多个位线，经由多个传输门和读出放大器耦合到多个位线的多条数据线。当感测放大器在表征模式下工作时，传输门和预充电电路被关断。差分电压感测装置将表征信号应用于感测放大器，并通过试错过程获得存储器电路的参数。

3. 发明授权

US08723265B2 Semiconductor structure with dummy polysilicon lines 有权
标题翻译：具有虚设多晶硅线的半导体结构
公开(公告)号：US08723265B2
公开(公告)日：2014-05-13
申请号：US13158133
申请日：2011-06-10
申请人： Yen-Huei Chen , Wei Min Chan , Shao-Yu Chou , Hung-Jen Liao
发明人： Yen-Huei Chen , Wei Min Chan , Shao-Yu Chou , Hung-Jen Liao
IPC分类号： H01L21/70 , H01L27/32
CPC分类号： H01L27/0207 , H01L27/088 , H01L27/1104
摘要： A multiple finger structure comprises a plurality of active regions placed between a pair of dummy POLY lines. The active regions comprise a plurality of multiple fingered NMOS transistors, which are part of a sense amplifier of an SRAM memory circuit. The drain and source of each multiple fingered NMOS transistor have an SiP/SiC epitaxial growth region. The active regions extend and overlap with the dummy POLY lines. The overlap between the active regions and the dummy POLY lines helps to reduce edge imperfection at the edge of the active regions.
摘要翻译：多指结构包括放置在一对虚拟POLY线之间的多个有源区域。有源区域包括多个多指状NMOS晶体管，它们是SRAM存储器电路的读出放大器的一部分。每个多指尖的NMOS晶体管的漏极和源极具有SiP / SiC外延生长区域。有源区域与虚拟POLY线路延伸并重叠。有源区域和虚拟POLY线之间的重叠有助于减少有源区域边缘处的边缘缺陷。

4. 发明授权

US08644087B2 Leakage-aware keeper for semiconductor memory 有权
标题翻译：用于半导体存储器的漏电保护器
公开(公告)号：US08644087B2
公开(公告)日：2014-02-04
申请号：US13177711
申请日：2011-07-07
申请人： Jihi-Yu Lin , Li-Wen Wang , Wei Min Chan , Yen-Huei Chen
发明人： Jihi-Yu Lin , Li-Wen Wang , Wei Min Chan , Yen-Huei Chen
IPC分类号： G11C7/10
CPC分类号： G11C7/04 , G11C11/417
摘要： A circuit includes a first circuit configured to sense a leakage of a first bit line and output a first signal in response, and a second circuit configured to receive the first signal output from the first circuit and in response supply current to a second bit line for maintaining a voltage level of the second bit line.
摘要翻译：电路包括被配置为感测第一位线的泄漏并响应地输出第一信号的第一电路，以及被配置为接收从第一电路输出的第一信号并响应于向第二位线提供电流的第二电路，维持第二位线的电压电平。

5. 发明授权

US08601411B2 Pre-colored methodology of multiple patterning 有权
公开(公告)号：US08601411B2
公开(公告)日：2013-12-03
申请号：US13586177
申请日：2012-08-15
申请人： Yen-Huei Chen , Wei Min Chan , Hung-Jen Liao , Jonathan Tsung-Yung Chang
发明人： Yen-Huei Chen , Wei Min Chan , Hung-Jen Liao , Jonathan Tsung-Yung Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F17/5068 , G06F2217/12
摘要： Some embodiments relate to a method for pre-coloring data within an integrated chip layout to avoid overlay errors that result from mask misalignment during multiple patterning lithography. The method may be performed by generating a graphical IC layout file containing an integrated chip layout having a plurality of IC shapes. The IC shapes within the graphical IC layout file are assigned a color during decomposition. The IC shapes are further pre-colored in a manner that deliberately assigns the pre-colored data to a same mask. During mask building data associated with IC shapes that have been pre-colored is automatically sent to a same mask, regardless of the colors that are assigned to the shapes. Therefore, the pre-colored shapes are not assigned to a masked based upon a decomposition, but rather based upon the pre-coloring. By assigning IC shapes to a same mask through pre-coloring, overlay errors can be reduced.

6. 发明申请

US20130263065A1 PRE-COLORED METHODOLOGY OF MULTIPLE PATTERNING 有权
标题翻译：多彩图案的预色彩方法
公开(公告)号：US20130263065A1
公开(公告)日：2013-10-03
申请号：US13586177
申请日：2012-08-15
申请人： Yen-Huei Chen , Wei Min Chan , Hung-Jen Liao , Jonathan Tsung-Yung Chang
发明人： Yen-Huei Chen , Wei Min Chan , Hung-Jen Liao , Jonathan Tsung-Yung Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F17/5068 , G06F2217/12
摘要： Some embodiments relate to a method for pre-coloring data within an integrated chip layout to avoid overlay errors that result from mask misalignment during multiple patterning lithography. The method may be performed by generating a graphical IC layout file containing an integrated chip layout having a plurality of IC shapes. The IC shapes within the graphical IC layout file are assigned a color during decomposition. The IC shapes are further pre-colored in a manner that deliberately assigns the pre-colored data to a same mask. During mask building data associated with IC shapes that have been pre-colored is automatically sent to a same mask, regardless of the colors that are assigned to the shapes. Therefore, the pre-colored shapes are not assigned to a masked based upon a decomposition, but rather based upon the pre-coloring. By assigning IC shapes to a same mask through pre-coloring, overlay errors can be reduced.
摘要翻译：一些实施例涉及用于在集成芯片布局内预先着色数据的方法，以避免在多次图案化光刻期间由掩模未对准而产生的重叠误差。该方法可以通过生成包含具有多个IC形状的集成芯片布局的图形IC布局文件来执行。图形IC布局文件中的IC形状在分解过程中会分配一种颜色。 IC形状进一步预先着色，以故意将预色数据分配给相同的掩码。在掩模建立过程中，与预先着色的IC形状相关联的数据将自动发送到相同的掩码，而不管分配给形状的颜色如何。因此，预先着色的形状不是基于分解而分配给掩蔽的，而是基于预着色。通过预先着色将IC形状分配给相同的掩模，可以减少重叠错误。

7. 发明授权

US08477527B2 SRAM timing cell apparatus and methods 有权
标题翻译： SRAM定时单元装置和方法
公开(公告)号：US08477527B2
公开(公告)日：2013-07-02
申请号：US13017793
申请日：2011-01-31
申请人： Li-Wen Wang , Shao-Yu Chou , Jihi-Yu Lin , Wei Min Chan , Yen-Huei Chen , Ping Wang
发明人： Li-Wen Wang , Shao-Yu Chou , Jihi-Yu Lin , Wei Min Chan , Yen-Huei Chen , Ping Wang
IPC分类号： G11C11/00
CPC分类号： G11C7/227 , G11C11/418
摘要： Apparatus and methods for providing SRAM timing tracking cell circuits are disclosed. In an embodiment, an apparatus comprises an SRAM array comprising static random access memory cells arranged in rows and columns; a plurality of word lines each coupled to memory cells along one of the rows; a clock generation circuit for outputting clock signals; a word line generation circuit for generating a pulse on the plurality of word lines responsive to one of the clock signals and for ending the pulse responsive to one of the clock signals; and a tracking cell for receiving a clock signal and for outputting a word line pulse end signal to the clock generation circuit, following an SRAM tracking time; wherein the tracking cell further comprises SRAM tracking circuits positioned in the SRAM array and coupled in series to provide a signal indicating the SRAM tracking time. Methods for SRAM timing are disclosed.
摘要翻译：公开了用于提供SRAM定时跟踪单元电路的装置和方法。在一个实施例中，一种装置包括一个SRAM阵列，它包括排列成行和列的静态随机存取存储单元; 多条字线，每条字线都沿着一条行与存储器单元耦合; 用于输出时钟信号的时钟发生电路; 字线生成电路，用于响应于所述时钟信号中的一个生成在所述多个字线上的脉冲，并响应于所述时钟信号之一来终止所述脉冲; 以及跟踪单元，用于接收时钟信号并用于在SRAM跟踪时间之后将时钟产生电路输出字线脉冲结束信号; 其中所述跟踪单元还包括位于所述SRAM阵列中并且串联耦合的SRAM跟踪电路，以提供指示所述SRAM跟踪时间的信号。公开了SRAM定时的方法。

8. 发明申请

US20120327730A1 SRAM Differential Voltage Sensing Apparatus 有权
标题翻译： SRAM差压检测装置
公开(公告)号：US20120327730A1
公开(公告)日：2012-12-27
申请号：US13169511
申请日：2011-06-27
申请人： Yen-Huei Chen , Kun-hsi Li , Shao-Yu Chou , Hung-Jen Liao , Wei Min Chan
发明人： Yen-Huei Chen , Kun-hsi Li , Shao-Yu Chou , Hung-Jen Liao , Wei Min Chan
IPC分类号： G11C7/00 , G11C7/02
CPC分类号： G11C7/12 , G11C7/062 , G11C11/419
摘要： An SRAM differential voltage sensing apparatus is coupled to a memory circuit. The memory circuit comprises a memory bank, a plurality of bit lines, a plurality of data lines coupled to the plurality of bit lines via a plurality of transmission gates and a sense amplifier. When the sense amplifier operates in a characterization mode, the transmission gates and pre-charge circuits are turned off. The differential voltage sensing apparatus applies a characterization signal to the sense amplifier and obtains the parameters of the memory circuit through a trial and error process.
摘要翻译： SRAM差分电压感测装置耦合到存储器电路。存储器电路包括存储体，多个位线，经由多个传输门和读出放大器耦合到多个位线的多条数据线。当感测放大器在表征模式下工作时，传输门和预充电电路被关断。差分电压感测装置将表征信号应用于感测放大器，并通过试错过程获得存储器电路的参数。

9. 发明授权

US08305829B2 Memory power gating circuit for controlling internal voltage of a memory array, system and method for controlling the same 有权
标题翻译：用于控制存储器阵列的内部电压的存储器电源门控电路，用于控制存储器阵列的系统和方法
公开(公告)号：US08305829B2
公开(公告)日：2012-11-06
申请号：US12707788
申请日：2010-02-18
申请人： Wei Min Chan , Jack Liu , Shao-Yu Chou
发明人： Wei Min Chan , Jack Liu , Shao-Yu Chou
IPC分类号： G11C7/00
CPC分类号： G11C5/147
摘要： A power gating circuit configured to couple with a memory array having an internal voltage, wherein the power gating circuit includes circuitry having an output signal that raises the internal voltage of the memory array if the internal voltage is lower than a first threshold voltage, and lowers the internal voltage if the internal voltage is higher than a second threshold voltage, thereby retaining the internal voltage between the first threshold voltage and the second threshold voltage.
摘要翻译：电源门控电路，被配置为与具有内部电压的存储器阵列耦合，其中所述功率门控电路包括具有输出信号的电路，所述电路具有在内部电压低于第一阈值电压时升高存储器阵列的内部电压，并且降低如果内部电压高于第二阈值电压，则内部电压，从而保持内部电压在第一阈值电压和第二阈值电压之间。

10. 发明申请

US20100214863A1 MEMORY POWER GATING CIRCUIT AND METHODS 有权
标题翻译：存储电力电源电路及方法
公开(公告)号：US20100214863A1
公开(公告)日：2010-08-26
申请号：US12707788
申请日：2010-02-18
申请人： Wei Min Chan , Jack Liu , Shao-Yu Chou
发明人： Wei Min Chan , Jack Liu , Shao-Yu Chou
IPC分类号： G11C5/14
CPC分类号： G11C5/147
摘要： A power gating circuit configured to couple with a memory array having an internal voltage, wherein the power gating circuit includes circuitry having an output signal that raises the internal voltage of the memory array if the internal voltage is lower than a first threshold voltage, and lowers the internal voltage if the internal voltage is higher than a second threshold voltage, thereby retaining the internal voltage between the first threshold voltage and the second threshold voltage.
摘要翻译：电源门控电路，被配置为与具有内部电压的存储器阵列耦合，其中所述功率门控电路包括具有输出信号的电路，所述电路具有在内部电压低于第一阈值电压时升高存储器阵列的内部电压，并且降低如果内部电压高于第二阈值电压，则内部电压，从而保持内部电压在第一阈值电压和第二阈值电压之间。

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