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1. 发明授权

US07034596B2 Adaptive input logic for phase adjustments 有权
标题翻译：用于相位调整的自适应输入逻辑
公开(公告)号：US07034596B2
公开(公告)日：2006-04-25
申请号：US10365083
申请日：2003-02-11
申请人： William B. Andrews , Harold Scholz , Barry K. Britton
发明人： William B. Andrews , Harold Scholz , Barry K. Britton
IPC分类号： H03K3/00
CPC分类号： H03L7/0814 , H03K5/133 , H03K2005/00058 , H03L7/0818 , H04L7/0041 , H04L7/0337
摘要： Systems and methods are disclosed to provide static and/or dynamic phase adjustments to a data signal relative to a clock signal. For example, the data signal may be delayed by a coarse delay and/or a fine delay to match the timing of the clock signal independently for each input path (e.g., per input pad). The delay may be as a function of positive and/or negative clock edges.
摘要翻译：公开了系统和方法以相对于时钟信号为数据信号提供静态和/或动态相位调整。例如，数据信号可以被延迟粗略的延迟和/或精细的延迟，以针对每个输入路径（例如，每个输入焊盘）独立地匹配时钟信号的定时。延迟可以是正和/或负时钟边缘的函数。

2. 发明授权

US06472904B2 Double data rate input and output in a programmable logic device 有权
标题翻译：可编程逻辑器件中的双数据速率输入和输出
公开(公告)号：US06472904B2
公开(公告)日：2002-10-29
申请号：US09864284
申请日：2001-05-25
申请人： William B. Andrews , Barry K. Britton
发明人： William B. Andrews , Barry K. Britton
IPC分类号： H03K19173
CPC分类号： G06F1/10 , H03K5/13 , H03K5/133 , H03K19/017581 , H03K19/17732 , H03K19/17736 , H03K19/1774 , H03K19/17744 , H03K19/17748 , H03K19/1776 , H03K19/17788 , H03K19/17792 , H03L7/081 , H03L7/0996
摘要： A multi-functional programmable I/O buffer in a Field Programmable Gate Array (FPGA) device. The I/O buffer is programmably configurable to meet any of a wide range of I/O standards, be it single ended or differential, 5V, 3.3V, 2.5V or 1.5V logic, without the need for implementing multiple I/O buffers to properly handle each different iteration of I/O requirements. An embedded, internal programmable resistor (e.g., a programmable 100 ohm resistor) is programmably selected for use in differential I/O applications, thus eliminating the conventional requirement for the use of an external resistor connected to each differential receiver I/O pin. The present invention also separates I/O pads into groups in each of a plurality of banks in a programmable device (e.g., PLD, FPGA, etc.), with each group being separately powered by the user. The disclosed multi-functional I/O buffer may be programmably configured by the user to be, e.g., a single ended receiver or transmitter, a reference receiver or transmitter, or a differential receiver or transmitter. The pad logic of the multi-functional I/O buffer may include a double data rate input and output mode, each of which includes two flip-flop devices operating on opposite sides of a data clock signal. One of the two flip-flop devices may be borrowed from another logic element, e.g., from a shift register logic element.
摘要翻译：现场可编程门阵列（FPGA）设备中的多功能可编程I / O缓冲器。 I / O缓冲器可编程配置，可满足任何I / O标准，无论是单端还是差分5V，3.3V，2.5V或1.5V逻辑，无需实现多个I / O缓冲器以适当地处理每个不同的I / O要求的迭代。嵌入式内部可编程电阻器（例如，可编程100欧姆电阻器）可编程选择用于差分I / O应用，从而消除了使用连接到每个差分接收器I / O引脚的外部电阻器的常规要求。本发明还将可编程器件（例如，PLD，FPGA等）中的I / O焊盘分成多个组中的每个组中的每个组，每个组由用户单独供电。所公开的多功能I / O缓冲器可由用户可编程地配置为例如单端接收器或发射器，参考接收器或发射器，或差分接收器或发射器。多功能I / O缓冲器的焊盘逻辑可以包括双数据速率输入和输出模式，每个数据速率输入和输出模式包括在数据时钟信号的相对侧上操作的两个触发器装置。两个触发器装置中的一个可以从另一个逻辑元件借用，例如来自移位寄存器逻辑元件。

3. 发明授权

US6064225A Global signal distribution with reduced routing tracks in an FPGA 失效
标题翻译：全局信号分配与FPGA中的路由跟踪减少
公开(公告)号：US6064225A
公开(公告)日：2000-05-16
申请号：US45128
申请日：1998-03-20
申请人： William B. Andrews , Barry K. Britton , Kai-Kit Ngai , Gary P. Powell , Satwant Singh , Carolyn W. Spivak , Richard G. Stuby, Jr.
发明人： William B. Andrews , Barry K. Britton , Kai-Kit Ngai , Gary P. Powell , Satwant Singh , Carolyn W. Spivak , Richard G. Stuby, Jr.
IPC分类号： H01L21/82 , H03K19/177 , H01L25/00
CPC分类号： H03K19/17736 , H03K19/17792 , H03K19/17796
摘要： The FPGA has an array of programmable logic cells (PLCs) surrounded by a ring of programmable input/output cells (PICs). In one embodiment, the pads of each pair of adjacent PICs, as well as internal routing resources of each of the two PICs, are programmably connected to a single global-signal spine, and the spine is programmably connected directly to only half of the perpendicular branches. Each of the branches can then connect to the cells in two adjacent rows/columns of the array to provide a global signal to any of the cells in the array while only using a branch per every two rows/columns of the device. The reduced number of spine-to-branch connections reduces the capacitive loading on the spines, thereby increasing the speed at which global signals can be transmitted. In addition, sharing spines between adjacent PICs reduces the number of spines in the FPGA by half, thereby providing additional layout space for other resources. Sharing branches also has the same effect as sharing spines in that the number of branches is reduced by half, also increasing global signal speed. These advantages are achieved without reducing the programming flexibility of the FPGA.
摘要翻译： FPGA具有由可编程输入/输出单元（PIC）环形围绕的可编程逻辑单元（PLC）阵列。在一个实施例中，每对相邻PICs的焊盘以及两个PIC中的每一个的内部路由资源可编程地连接到单个全局信号脊柱，并且脊柱可编程地直接连接到垂直的一半分支机构然后，每个分支可以连接到阵列的两个相邻行/列中的单元格，以向阵列中的任何单元提供全局信号，而仅在设备的每两行/列中使用分支。减少数量的脊对分支连接减少了脊柱上的电容负载，从而增加了全局信号可以传输的速度。此外，在相邻PIC之间共享脊椎将FPGA中的脊柱数量减少一半，从而为其他资源提供额外的布局空间。共享分支也具有与共享刺激相同的效果，因为分支数量减少了一半，也增加了全球信号速度。这些优点在不降低FPGA的编程灵活性的情况下实现。

4. 发明授权

US07262630B1 Programmable termination for single-ended and differential schemes 有权
标题翻译：单端和差分方案的可编程终端
公开(公告)号：US07262630B1
公开(公告)日：2007-08-28
申请号：US11194356
申请日：2005-08-01
申请人： William B. Andrews , Barry K. Britton , John Schadt , Mou C. Lin
发明人： William B. Andrews , Barry K. Britton , John Schadt , Mou C. Lin
IPC分类号： H03K19/003
CPC分类号： H03K19/17744 , H04L25/0278
摘要： In one embodiment of the invention, a programmable termination structure has first and second termination circuits for corresponding pads and a programmable connection therebetween. The first termination circuit supports first and second sets of termination schemes. A shared resistor is part of at least one termination scheme in each set. The first termination circuit supports a termination scheme between the first pad and a user-defined node connected to an on-chip capacitor such that first pad is connected via the termination scheme to the on-chip capacitor. Control circuitry automatically turns on and off a termination scheme for bidirectional signaling supported by the first termination circuit, wherein (1) the control circuitry turns off the termination scheme if an output buffer is configured to present outgoing signals at the first pad and (2) the control circuitry turns on the termination scheme if the output buffer is disabled in order to terminate incoming signals received at the first pad.
摘要翻译：在本发明的一个实施例中，可编程终端结构具有用于相应焊盘的第一和第二终端电路以及它们之间的可编程连接。第一终端电路支持第一和第二组终端方案。共享电阻是每组中至少一个终端方案的一部分。第一终端电路支持第一焊盘和连接到片上电容器的用户定义节点之间的终止方案，使得第一焊盘通过端接方案连接到片上电容器。控制电路自动打开和关闭由第一终端电路支持的用于双向信令的终止方案，其中（1）如果输出缓冲器被配置为在第一焊盘处呈现输出信号，则控制电路关闭终止方案，（2）如果禁止输出缓冲器以便终止在第一焊盘处接收到的输入信号，则控制电路接通终止方案。

5. 发明授权

US6020755A Hybrid programmable gate arrays 失效
标题翻译：混合可编程门阵列
公开(公告)号：US6020755A
公开(公告)日：2000-02-01
申请号：US938550
申请日：1997-09-26
申请人： William B. Andrews , Barry K. Britton , Thomas J. Hickey , Ronald T. Modo , Ho T. Nguyen , Lorraine L. Schadt , Satwant Singh
发明人： William B. Andrews , Barry K. Britton , Thomas J. Hickey , Ronald T. Modo , Ho T. Nguyen , Lorraine L. Schadt , Satwant Singh
IPC分类号： H01L21/82 , H03K19/177
CPC分类号： H03K19/17796 , H03K19/17732
摘要： A single integrated circuit (IC) having one or more regions of mask-programmed device (MPD) logic for implementing permanent functions and one or more regions of field-programmable gate-array (FPGA) logic for implementing user-specified functions. The FPGA-type logic provides programming flexibility, while the MPD-type logic provides size, speed, functionality, and dollar cost advantages. In one embodiment, a hybrid IC has an array of programmable logic cells (PLCs) implemented using FPGA-type logic, an application-specific block (ASB) implemented using MPD-type logic, and a ring of pads. Fast interface switch hierarchy (FISH) cells provide the interface between the PLC array and the pads, between the PLC array and the ASB, and between the ASB and the pad ring. Muxes in the FISH cells can be programmed to cause the FISH cells to operate either (1) as programmable interface cells (PICs) that provide a direct interface between the PLC array and the pad ring or (2) as ASB-interface cells (AICs) that (a) provide interfaces between the PLC array and the ASB and (b) control interfaces between the ASB and the pad ring.
摘要翻译：具有用于实现永久功能的一个或多个屏蔽编程设备（MPD）逻辑区域的单个集成电路（IC）和用于实现用户指定功能的现场可编程门阵列（FPGA）逻辑的一个或多个区域。 FPGA型逻辑提供编程灵活性，而MPD型逻辑提供了大小，速度，功能和美元成本优势。在一个实施例中，混合IC具有使用FPGA类型逻辑实现的可编程逻辑单元阵列（PLC）阵列，使用MPD型逻辑实现的特定应用块（ASB）和一个垫环阵列。快速接口交换层次（FISH）单元提供PLC阵列与PLC之间，PLC阵列与ASB之间以及ASB与焊盘环之间的接口。可以对FISH单元中的复用器进行编程，以使FISH单元（1）作为可编程接口单元（PIC）来操作，这些可编程接口单元（PIC）可在PLC阵列和焊盘环之间提供直接接口，或（2）作为ASB接口单元（AIC））（a）提供PLC阵列和ASB之间的接口，（b）控制ASB和焊盘环之间的接口。

6. 发明授权

US5381058A FPGA having PFU with programmable output driver inputs 失效
标题翻译： FPGA具有可编程输出驱动器输入的PFU
公开(公告)号：US5381058A
公开(公告)日：1995-01-10
申请号：US65823
申请日：1993-05-21
申请人： Barry K. Britton , Dwight D. Hill
发明人： Barry K. Britton , Dwight D. Hill
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/17744 , H03K19/1737
摘要： In accordance with the present invention, a field programmable gate array includes at least one programmable function unit. The programmable function unit has first and second logic circuits, each providing an output, and first and second output drivers, each having an input. The input of each output driver is adapted to be selectively coupled to the output of either of the logic circuits. A programmable interconnection is provided to selectively couple the input of the two output drivers to the output of a selective one of the logic circuits.
摘要翻译：根据本发明，现场可编程门阵列包括至少一个可编程功能单元。可编程功能单元具有第一和第二逻辑电路，每个提供输出，第一和第二输出驱动器各自具有输入。每个输出驱动器的输入适于选择性地耦合到任一逻辑电路的输出端。提供可编程互连以选择性地将两个输出驱动器的输入耦合到逻辑电路中的选择性逻辑电路的输出。

7. 发明授权

US6060902A Programmable clock manager for a programmable logic device that can be programmed without reconfiguring the device 失效
标题翻译：可编程逻辑器件的可编程时钟管理器，可以在不重新配置器件的情况下进行编程
公开(公告)号：US6060902A
公开(公告)日：2000-05-09
申请号：US950448
申请日：1997-10-15
申请人： Lucian R. Albu , Barry K. Britton , Wai-Bor Leung , Richard G. Stuby, Jr. , James A. Thompson , Zeljko Zilic
发明人： Lucian R. Albu , Barry K. Britton , Wai-Bor Leung , Richard G. Stuby, Jr. , James A. Thompson , Zeljko Zilic
IPC分类号： H03K19/177 , G06F7/38
CPC分类号： H03K19/1774
摘要： A programmable logic device (PLD), such as a field programmable gate array (FPGA), has a programmable clock manager (PCM) that converts an input clock into at least one output clock and the PCM can be programmed during PLD operations, without reconfiguring the PLD.
摘要翻译：诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）具有可编程时钟管理器（PCM），其将输入时钟转换为至少一个输出时钟，并且可以在PLD操作期间对PCM进行编程，而无需重新配置 PLD。

8. 发明授权

US5986471A Bi-directional buffers and supplemental logic and interconnect cells for programmable logic devices 失效
标题翻译：用于可编程逻辑器件的双向缓冲器和补充逻辑和互连单元
公开(公告)号：US5986471A
公开(公告)日：1999-11-16
申请号：US950446
申请日：1997-10-15
申请人： Barry K. Britton , Kai-Kit Ngai , Ho T. Nguyen , Satwant Singh , Carolyn W. Spivak , Richard G. Stuby, Jr.
发明人： Barry K. Britton , Kai-Kit Ngai , Ho T. Nguyen , Satwant Singh , Carolyn W. Spivak , Richard G. Stuby, Jr.
IPC分类号： H03K19/173 , H03K19/00 , G06F7/38
CPC分类号： H03K19/17736 , H03K19/1736
摘要： The bi-directional (BI-DI) buffers and supplemental logic and interconnect (SLIC) cells are designed to be programmed to operate in different modes in order to implement different kinds of logic circuits. In particular, BI-DI buffers of the present invention support at least five different operational modes. In a first mode (Mode A), the BI-DI buffer generates a logic "1" output, for any input value. In a second mode (Mode B), the BI-DI buffer generates a logic "0" output, for any input value. In a third mode (Mode C), the BI-DI buffer buffers the input signal and generates an output signal equal to the input signal. In a fourth mode (Mode D), the BI-DI buffer buffers the input signal and generates an output signal equal to the inverse of the input signal. In a fifth mode, (Mode E), the BI-DI buffer operates as a conventional tri-state driver. Two or more of the BI-DI buffers can be configured to form more complex logic circuits having two or more inputs. For example, groups of BI-DI buffers can be configured as SLIC cells that are part of the basic logic cells for an FPGA. When used in FPGAs, the BI-DI buffers and SLIC cells make implementation of different kinds of logic circuits more efficient than is the case for conventional FPGAs, including logic circuits like decoders and state machines that have large numbers of inputs. At the same time, the FPGAs retain their efficiencies for implementing logic circuits for which FPGAs have traditionally been very efficient, such as random logic and datapath logic.
摘要翻译：双向（BI-DI）缓冲器和补充逻辑和互连（SLIC）单元被设计为被编程为以不同的模式操作，以便实现不同种类的逻辑电路。特别地，本发明的BI-DI缓冲器支持至少五种不同的操作模式。在第一种模式（模式A）中，BI-DI缓冲区为任何输入值产生逻辑“1”输出。在第二种模式（模式B）中，BI-DI缓冲区为任何输入值产生逻辑“0”输出。在第三种模式（模式C）中，BI-DI缓冲器缓冲输入信号并产生等于输入信号的输出信号。在第四模式（模式D）中，BI-DI缓冲器缓冲输入信号并产生等于输入信号的反相的输出信号。在第五模式（模式E）中，BI-DI缓冲器作为常规三态驱动器工作。可以将两个或更多个BI-DI缓冲器配置成形成具有两个或更多个输入的更复杂的逻辑电路。例如，BI-DI缓冲器的组可以被配置为作为FPGA的基本逻辑单元的一部分的SLIC单元。当在FPGA中使用时，BI-DI缓冲器和SLIC单元使得不同类型的逻辑电路的实现比传统FPGA更为有效，包括具有大量输入的解码器和状态机的逻辑电路。同时，FPGA保留了实现FPGA传统上非常有效的逻辑电路的效率，例如随机逻辑和数据通路逻辑。

9. 发明授权

US5386156A Programmable function unit with programmable fast ripple logic 失效
标题翻译：具有可编程快速纹波逻辑的可编程功能单元
公开(公告)号：US5386156A
公开(公告)日：1995-01-31
申请号：US113154
申请日：1993-08-27
申请人： Barry K. Britton , Wai-Bor Leung
发明人： Barry K. Britton , Wai-Bor Leung
IPC分类号： G06F7/50 , G06F7/503 , H03K19/173
CPC分类号： G06F7/503 , H03K19/1737 , H03K19/17728
摘要： A programmable function unit (PFU) well adapted for use in a field programmable gate array (FPGA) is disclosed. The PFU utilizes programmable fast ripple logic. A programmable generator and/or a programmable propagator are implemented in look up tables in each PFU block. A multiplexer under control of the propagator determines whether to transmit the carry in from the previous block or to transmit the generator signal.
摘要翻译：公开了一种适用于现场可编程门阵列（FPGA）的可编程功能单元（PFU）。 PFU使用可编程快速纹波逻辑。可编程发生器和/或可编程传播器在每个PFU块的查找表中实现。在传播器的控制下的多路复用器确定是从前一块传输进位还是传送发生器信号。

10. 发明授权

US5311080A Field programmable gate array with direct input/output connection 失效
标题翻译：具有直接输入/输出连接的现场可编程门阵列
公开(公告)号：US5311080A
公开(公告)日：1994-05-10
申请号：US037766
申请日：1993-03-26
申请人： Barry K. Britton , Dwight D. Hill , William A. Oswald
发明人： Barry K. Britton , Dwight D. Hill , William A. Oswald
IPC分类号： H01L21/82 , H01L27/118 , H03K19/173 , H03K19/177
CPC分类号： H03K19/17744 , H03K19/1736
摘要： A field programmable gate array that includes a dedicated path that directly connects an I/O pad to a selected register in the array of programmable function units. For example, a direct connection (i.e., without a configurable interconnect point) is provided from an I/O pad, through an input driver, to the input of a selected register in a given PFU. Either this same path, or alternatively a different path, may be used to directly connect a register output from a given PFU to an I/O pad, through an output driver. This technique avoids the need for special I/O registers in the programmable input/output cells, thereby increasing the flexibility of use and ease of design of the FPGA.
摘要翻译：一种现场可编程门阵列，其包括将I / O焊盘直接连接到可编程功能单元阵列中的选定寄存器的专用路径。例如，从I / O焊盘通过输入驱动器将直接连接（即，没有可配置的互连点）提供给给定PFU中所选择的寄存器的输入。通过输出驱动器，可以使用相同的路径或者不同的路径来将给定PFU的寄存器输出直接连接到I / O焊盘。这种技术避免了在可编程输入/输出单元中需要特殊的I / O寄存器，从而增加了FPGA的使用灵活性和易于设计。

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