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1. 发明授权

US6043677A Programmable clock manager for a programmable logic device that can implement delay-locked loop functions 失效
标题翻译：可编程逻辑器件的可编程时钟管理器，可实现延迟锁定环路功能
公开(公告)号：US6043677A
公开(公告)日：2000-03-28
申请号：US951128
申请日：1997-10-15
申请人： Lucian R. Albu , Barry K. Britton , Wai-Bor Leung , Richard G. Stuby, Jr. , James A. Thompson , Zeljko Zilic
发明人： Lucian R. Albu , Barry K. Britton , Wai-Bor Leung , Richard G. Stuby, Jr. , James A. Thompson , Zeljko Zilic
IPC分类号： H03K19/177 , H03L7/081 , G06F7/38
CPC分类号： H03K19/1774 , H03L7/0812
摘要： A programmable logic device (PLD), such as a field programmable gate array (FPGA), has a programmable clock manager (PCM) that converts an input clock into at least one output clock and the PCM can perform one or more delay-locked loop (DLL) functions. In one embodiment, the DLL functions include clock delay, duty-cycle adjustment, and clock doubling, where duty-cycle adjustment can optionally be applied independently to the doubled clock cycles.
摘要翻译：诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）具有可编程时钟管理器（PCM），其将输入时钟转换成至少一个输出时钟，并且PCM可以执行一个或多个延迟锁定环（DLL）功能。在一个实施例中，DLL功能包括时钟延迟，占空比调整和时钟倍增，其中占空比调整可以独立地应用于双倍时钟周期。

2. 发明授权

US6028463A Programmable clock manager for a programmable logic device that can generate at least two different output clocks 失效
标题翻译：可编程逻辑器件的可编程时钟管理器可以生成至少两个不同的输出时钟
公开(公告)号：US6028463A
公开(公告)日：2000-02-22
申请号：US949992
申请日：1997-10-15
申请人： Lucian R. Albu , Barry K. Britton , Wai-Bor Leung , Richard G. Stuby, Jr. , James A. Thompson , Zeljko Zilic
发明人： Lucian R. Albu , Barry K. Britton , Wai-Bor Leung , Richard G. Stuby, Jr. , James A. Thompson , Zeljko Zilic
IPC分类号： G06F1/06 , G06F1/08 , H03K19/173 , H03K19/177 , H03L7/081 , H03L7/089 , H03K7/38
CPC分类号： H03K19/1774 , G06F1/06 , G06F1/08 , H03K19/1733 , H03K19/17704 , H03L7/0812 , H03L7/0891
摘要： A programmable logic device (PLD), such as a field programmable gate array (FPGA), has a programmable clock manager (PCM) that converts an input clock into at least two different output clocks having different clock rates. The different output clocks can be used to control different processes either within or outside the FPGA. For example, one output clock can be used to control the FPGA's input/output registers, while a second, faster output clock can be used to control the FPGA's internal registers.
摘要翻译：诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）具有可编程时钟管理器（PCM），其将输入时钟转换成具有不同时钟速率的至少两个不同的输出时钟。不同的输出时钟可用于控制FPGA内部或外部的不同进程。例如，一个输出时钟可用于控制FPGA的输入/输出寄存器，而第二个更快的输出时钟可用于控制FPGA的内部寄存器。

3. 发明授权

US6060902A Programmable clock manager for a programmable logic device that can be programmed without reconfiguring the device 失效
标题翻译：可编程逻辑器件的可编程时钟管理器，可以在不重新配置器件的情况下进行编程
公开(公告)号：US6060902A
公开(公告)日：2000-05-09
申请号：US950448
申请日：1997-10-15
申请人： Lucian R. Albu , Barry K. Britton , Wai-Bor Leung , Richard G. Stuby, Jr. , James A. Thompson , Zeljko Zilic
发明人： Lucian R. Albu , Barry K. Britton , Wai-Bor Leung , Richard G. Stuby, Jr. , James A. Thompson , Zeljko Zilic
IPC分类号： H03K19/177 , G06F7/38
CPC分类号： H03K19/1774
摘要： A programmable logic device (PLD), such as a field programmable gate array (FPGA), has a programmable clock manager (PCM) that converts an input clock into at least one output clock and the PCM can be programmed during PLD operations, without reconfiguring the PLD.
摘要翻译：诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）具有可编程时钟管理器（PCM），其将输入时钟转换为至少一个输出时钟，并且可以在PLD操作期间对PCM进行编程，而无需重新配置 PLD。

4. 发明授权

US06216191B1 Field programmable gate array having a dedicated processor interface 失效
标题翻译：具有专用处理器接口的现场可编程门阵列
公开(公告)号：US06216191B1
公开(公告)日：2001-04-10
申请号：US08950444
申请日：1997-10-15
申请人： Barry K. Britton , Alan Cunningham , Wai-Bor Leung , Richard G. Stuby, Jr. , James A. Thompson
发明人： Barry K. Britton , Alan Cunningham , Wai-Bor Leung , Richard G. Stuby, Jr. , James A. Thompson
IPC分类号： G06F1300
CPC分类号： G06F13/385
摘要： A field programmable gate array (FPGA) has an interface circuit that allows signals to be transmitted directly between the FPGA and a processor. The processor interface (PI) of the FPGA enables the processor to access data at any time from either programmable logic of the FPGA or system registers of the PI. The present invention eliminates the need for external intermediate logic previously required to interface an FPGA and a processor.
摘要翻译：现场可编程门阵列（FPGA）具有允许在FPGA和处理器之间直接传输信号的接口电路。 FPGA的处理器接口（PI）可使处理器随时从FPGA的可编程逻辑或PI的系统寄存器访问数据。本发明消除了对FPGA和处理器之间的以前需要的外部中间逻辑的需要。

5. 发明授权

US6124732A Signaling voltage range discriminator 失效
标题翻译：信号电压范围鉴别器
公开(公告)号：US6124732A
公开(公告)日：2000-09-26
申请号：US115683
申请日：1998-07-15
申请人： Zeljko Zilic , Ho T. Nguyen , Gary P. Powell , William B. Andrews , Richard G. Stuby, Jr.
发明人： Zeljko Zilic , Ho T. Nguyen , Gary P. Powell , William B. Andrews , Richard G. Stuby, Jr.
IPC分类号： H03K19/0185 , H03K19/0175
CPC分类号： H03K19/018585
摘要： The invention provides an input/output (I/O) signaling voltage range discriminator (and corresponding method) which is used to control a configurable logic device such as a configurable I/O buffer in a second electronic circuit in response to a detected signaling voltage range of a first electronic circuit. The discriminator outputs an indication of the signaling voltage range of the first electronic circuit to a configurable I/O buffer enabling it to adapt to the signaling levels used by the first electronic circuit. The I/O buffer, based on the indication provided by the discriminator, can then configure its logic to become tolerant and/or compatible with digital signals transferred to and from the first electronic circuit.
摘要翻译：本发明提供了一种输入/输出（I / O）信令电压范围鉴别器（和相应的方法），其用于响应于检测到的信号电压来控制可配置逻辑器件，例如第二电子电路中的可配置I / O缓冲器第一电子电路的范围。鉴别器将第一电子电路的信号电压范围的指示输出到可配置的I / O缓冲器，使其能够适应第一电子电路使用的信号电平。然后，基于鉴别器提供的指示，I / O缓冲器可以将它的逻辑配置成容忍和/或与传送到第一电子电路的数字信号兼容。

6. 发明授权

US6064225A Global signal distribution with reduced routing tracks in an FPGA 失效
标题翻译：全局信号分配与FPGA中的路由跟踪减少
公开(公告)号：US6064225A
公开(公告)日：2000-05-16
申请号：US45128
申请日：1998-03-20
申请人： William B. Andrews , Barry K. Britton , Kai-Kit Ngai , Gary P. Powell , Satwant Singh , Carolyn W. Spivak , Richard G. Stuby, Jr.
发明人： William B. Andrews , Barry K. Britton , Kai-Kit Ngai , Gary P. Powell , Satwant Singh , Carolyn W. Spivak , Richard G. Stuby, Jr.
IPC分类号： H01L21/82 , H03K19/177 , H01L25/00
CPC分类号： H03K19/17736 , H03K19/17792 , H03K19/17796
摘要： The FPGA has an array of programmable logic cells (PLCs) surrounded by a ring of programmable input/output cells (PICs). In one embodiment, the pads of each pair of adjacent PICs, as well as internal routing resources of each of the two PICs, are programmably connected to a single global-signal spine, and the spine is programmably connected directly to only half of the perpendicular branches. Each of the branches can then connect to the cells in two adjacent rows/columns of the array to provide a global signal to any of the cells in the array while only using a branch per every two rows/columns of the device. The reduced number of spine-to-branch connections reduces the capacitive loading on the spines, thereby increasing the speed at which global signals can be transmitted. In addition, sharing spines between adjacent PICs reduces the number of spines in the FPGA by half, thereby providing additional layout space for other resources. Sharing branches also has the same effect as sharing spines in that the number of branches is reduced by half, also increasing global signal speed. These advantages are achieved without reducing the programming flexibility of the FPGA.
摘要翻译： FPGA具有由可编程输入/输出单元（PIC）环形围绕的可编程逻辑单元（PLC）阵列。在一个实施例中，每对相邻PICs的焊盘以及两个PIC中的每一个的内部路由资源可编程地连接到单个全局信号脊柱，并且脊柱可编程地直接连接到垂直的一半分支机构然后，每个分支可以连接到阵列的两个相邻行/列中的单元格，以向阵列中的任何单元提供全局信号，而仅在设备的每两行/列中使用分支。减少数量的脊对分支连接减少了脊柱上的电容负载，从而增加了全局信号可以传输的速度。此外，在相邻PIC之间共享脊椎将FPGA中的脊柱数量减少一半，从而为其他资源提供额外的布局空间。共享分支也具有与共享刺激相同的效果，因为分支数量减少了一半，也增加了全球信号速度。这些优点在不降低FPGA的编程灵活性的情况下实现。

7. 发明授权

US5986471A Bi-directional buffers and supplemental logic and interconnect cells for programmable logic devices 失效
标题翻译：用于可编程逻辑器件的双向缓冲器和补充逻辑和互连单元
公开(公告)号：US5986471A
公开(公告)日：1999-11-16
申请号：US950446
申请日：1997-10-15
申请人： Barry K. Britton , Kai-Kit Ngai , Ho T. Nguyen , Satwant Singh , Carolyn W. Spivak , Richard G. Stuby, Jr.
发明人： Barry K. Britton , Kai-Kit Ngai , Ho T. Nguyen , Satwant Singh , Carolyn W. Spivak , Richard G. Stuby, Jr.
IPC分类号： H03K19/173 , H03K19/00 , G06F7/38
CPC分类号： H03K19/17736 , H03K19/1736
摘要： The bi-directional (BI-DI) buffers and supplemental logic and interconnect (SLIC) cells are designed to be programmed to operate in different modes in order to implement different kinds of logic circuits. In particular, BI-DI buffers of the present invention support at least five different operational modes. In a first mode (Mode A), the BI-DI buffer generates a logic "1" output, for any input value. In a second mode (Mode B), the BI-DI buffer generates a logic "0" output, for any input value. In a third mode (Mode C), the BI-DI buffer buffers the input signal and generates an output signal equal to the input signal. In a fourth mode (Mode D), the BI-DI buffer buffers the input signal and generates an output signal equal to the inverse of the input signal. In a fifth mode, (Mode E), the BI-DI buffer operates as a conventional tri-state driver. Two or more of the BI-DI buffers can be configured to form more complex logic circuits having two or more inputs. For example, groups of BI-DI buffers can be configured as SLIC cells that are part of the basic logic cells for an FPGA. When used in FPGAs, the BI-DI buffers and SLIC cells make implementation of different kinds of logic circuits more efficient than is the case for conventional FPGAs, including logic circuits like decoders and state machines that have large numbers of inputs. At the same time, the FPGAs retain their efficiencies for implementing logic circuits for which FPGAs have traditionally been very efficient, such as random logic and datapath logic.
摘要翻译：双向（BI-DI）缓冲器和补充逻辑和互连（SLIC）单元被设计为被编程为以不同的模式操作，以便实现不同种类的逻辑电路。特别地，本发明的BI-DI缓冲器支持至少五种不同的操作模式。在第一种模式（模式A）中，BI-DI缓冲区为任何输入值产生逻辑“1”输出。在第二种模式（模式B）中，BI-DI缓冲区为任何输入值产生逻辑“0”输出。在第三种模式（模式C）中，BI-DI缓冲器缓冲输入信号并产生等于输入信号的输出信号。在第四模式（模式D）中，BI-DI缓冲器缓冲输入信号并产生等于输入信号的反相的输出信号。在第五模式（模式E）中，BI-DI缓冲器作为常规三态驱动器工作。可以将两个或更多个BI-DI缓冲器配置成形成具有两个或更多个输入的更复杂的逻辑电路。例如，BI-DI缓冲器的组可以被配置为作为FPGA的基本逻辑单元的一部分的SLIC单元。当在FPGA中使用时，BI-DI缓冲器和SLIC单元使得不同类型的逻辑电路的实现比传统FPGA更为有效，包括具有大量输入的解码器和状态机的逻辑电路。同时，FPGA保留了实现FPGA传统上非常有效的逻辑电路的效率，例如随机逻辑和数据通路逻辑。

8. 发明授权

US06483342B2 Multi-master multi-slave system bus in a field programmable gate array (FPGA) 有权
标题翻译：多主机多从系统总线在现场可编程门阵列（FPGA）
公开(公告)号：US06483342B2
公开(公告)日：2002-11-19
申请号：US09864277
申请日：2001-05-25
申请人： Barry K. Britton , Ravikumar Charath , Zheng Chen , James F. Hoff , Cort D. Lansenderfer , Don McCarley , Richard G. Stuby, Jr. , Ju-Yuan D. Yang
发明人： Barry K. Britton , Ravikumar Charath , Zheng Chen , James F. Hoff , Cort D. Lansenderfer , Don McCarley , Richard G. Stuby, Jr. , Ju-Yuan D. Yang
IPC分类号： H03K19177
CPC分类号： G06F1/10 , H03K5/13 , H03K5/133 , H03K19/017581 , H03K19/17732 , H03K19/17736 , H03K19/1774 , H03K19/17744 , H03K19/17748 , H03K19/1776 , H03K19/17788 , H03K19/17792 , H03L7/081 , H03L7/0996
摘要： An embedded system bus is woven between a plurality of embedded master elements and at least one slave element within the FPGA device, and provides an external processor interface allowing direct access to any of the plurality of embedded slave elements. Using the embedded system bus, any of a plurality of masters may be allowed to program an embedded element, e.g., embedded FPGA logic, whereas conventional FPGAs allowed only a single master (e.g., a processor) to program the embedded FPGA logic. The embedded system bus is a group of signals, typically data, address and control, that connects system elements together and provides a basic protocol for the flow of data. The embedded system bus allows for control, configuration and status determination of the FPGA device. The embedded system bus is preferably a dedicated function available at all times for arbitrated access to allow communication between the various embedded system components.
摘要翻译：嵌入式系统总线在多个嵌入式主元件和FPGA器件内的至少一个从属元件之间编织，并提供允许直接访问多个嵌入式从属元件中的任一个的外部处理器接口。使用嵌入式系统总线，可以允许多个主机中的任何一个主机对嵌入式元件（例如，嵌入式FPGA逻辑）进行编程，而常规FPGA只允许单个主机（例如，处理器）编程嵌入式FPGA逻辑。嵌入式系统总线是一组信号，通常是数据，地址和控制，将系统元件连接在一起，并为数据流提供基本协议。嵌入式系统总线允许FPGA器件的控制，配置和状态确定。嵌入式系统总线优选地是可随时用于仲裁访问的专用功能，以允许各种嵌入式系统组件之间的通信。

9. 发明授权

US6049224A Programmable logic device with logic cells having a flexible input structure 失效
标题翻译：具有逻辑单元的可编程逻辑器件具有灵活的输入结构
公开(公告)号：US6049224A
公开(公告)日：2000-04-11
申请号：US950624
申请日：1997-10-15
申请人： Barry K. Britton , Ian L. McEwen , Ho T. Nguyen , Satwant Singh , Carolyn W. Spivak , Richard G. Stuby, Jr.
发明人： Barry K. Britton , Ian L. McEwen , Ho T. Nguyen , Satwant Singh , Carolyn W. Spivak , Richard G. Stuby, Jr.
IPC分类号： H03K19/177 , H01L25/00 , H03K19/173
CPC分类号： H03K19/17728
摘要： A programmable logic device, such as an FPGA, is implemented using logic cells that have configurable connection schemes between routing resources and logic element input pins. For example, in one embodiment, each logic cell in the device has a flexible input structure that supports two or more different connection schemes, which may or may not involve input sharing, where each logic cell can be individually programmed for any of the available connection schemes when the device is configured. As such, the device can be efficiently programmed to implement the user's specific circuitry. The invention balances the competing goals of (1) reducing routing requirements by limiting the number of connections between routing resources and logic element input pins and (2) providing minimally constrained programming of logic elements.
摘要翻译：使用在路由资源和逻辑元件输入引脚之间具有可配置连接方案的逻辑单元来实现可编程逻辑器件，例如FPGA。例如，在一个实施例中，设备中的每个逻辑单元具有灵活的输入结构，其支持两个或多个不同的连接方案，其可以或可以不涉及输入共享，其中每个逻辑单元可以针对任何可用连接进行单独编程配置设备时的方案。因此，可以有效地对设备进行编程以实现用户的特定电路。本发明平衡了（1）通过限制路由资源和逻辑元件输入引脚之间的连接数来减少路由需求的竞争目标，以及（2）提供逻辑元件的最小约束编程。

10. 发明授权

US06772230B2 Field programmable gate array (FPGA) bit stream format 有权
标题翻译：现场可编程门阵列（FPGA）位流格式
公开(公告)号：US06772230B2
公开(公告)日：2004-08-03
申请号：US09864290
申请日：2001-05-25
申请人： Zheng Chen , Richard G. Stuby, Jr.
发明人： Zheng Chen , Richard G. Stuby, Jr.
IPC分类号： G06F1314
CPC分类号： G06F1/10 , H03K5/13 , H03K5/133 , H03K19/017581 , H03K19/17732 , H03K19/17736 , H03K19/1774 , H03K19/17744 , H03K19/17748 , H03K19/1776 , H03K19/17788 , H03K19/17792 , H03L7/081 , H03L7/0996
摘要： An embedded system bus is woven between a plurality of embedded master elements and at least one slave element within the FPGA device, and provides an external processor interface allowing direct access to any of the plurality of embedded slave elements. Using the embedded system bus, any of a plurality of masters may be allowed to program an embedded element, e.g., embedded FPGA logic, whereas conventional FPGAs allowed only a single master (e.g., a processor) to program the embedded FPGA logic. The embedded system bus is a group of signals, typically data, address and control, that connects system elements together and provides a basic protocol for the flow of data. The embedded system bus allows for control, configuration and status determination of the FPGA device. The embedded system bus is preferably a dedicated function available at all times for arbitrated access to allow communication between the various embedded system components.
摘要翻译：嵌入式系统总线在多个嵌入式主元件和FPGA器件内的至少一个从属元件之间编织，并提供允许直接访问多个嵌入式从属元件中的任一个的外部处理器接口。使用嵌入式系统总线，可以允许多个主机中的任何一个主机对嵌入式元件（例如，嵌入式FPGA逻辑）进行编程，而常规FPGA只允许单个主机（例如，处理器）编程嵌入式FPGA逻辑。嵌入式系统总线是一组信号，通常是数据，地址和控制，将系统元件连接在一起，并为数据流提供基本协议。嵌入式系统总线允许FPGA器件的控制，配置和状态确定。嵌入式系统总线优选地是可随时用于仲裁访问的专用功能，以允许各种嵌入式系统组件之间的通信。

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