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1. 发明授权

US6064225A Global signal distribution with reduced routing tracks in an FPGA 失效
标题翻译：全局信号分配与FPGA中的路由跟踪减少
公开(公告)号：US6064225A
公开(公告)日：2000-05-16
申请号：US45128
申请日：1998-03-20
申请人： William B. Andrews , Barry K. Britton , Kai-Kit Ngai , Gary P. Powell , Satwant Singh , Carolyn W. Spivak , Richard G. Stuby, Jr.
发明人： William B. Andrews , Barry K. Britton , Kai-Kit Ngai , Gary P. Powell , Satwant Singh , Carolyn W. Spivak , Richard G. Stuby, Jr.
IPC分类号： H01L21/82 , H03K19/177 , H01L25/00
CPC分类号： H03K19/17736 , H03K19/17792 , H03K19/17796
摘要： The FPGA has an array of programmable logic cells (PLCs) surrounded by a ring of programmable input/output cells (PICs). In one embodiment, the pads of each pair of adjacent PICs, as well as internal routing resources of each of the two PICs, are programmably connected to a single global-signal spine, and the spine is programmably connected directly to only half of the perpendicular branches. Each of the branches can then connect to the cells in two adjacent rows/columns of the array to provide a global signal to any of the cells in the array while only using a branch per every two rows/columns of the device. The reduced number of spine-to-branch connections reduces the capacitive loading on the spines, thereby increasing the speed at which global signals can be transmitted. In addition, sharing spines between adjacent PICs reduces the number of spines in the FPGA by half, thereby providing additional layout space for other resources. Sharing branches also has the same effect as sharing spines in that the number of branches is reduced by half, also increasing global signal speed. These advantages are achieved without reducing the programming flexibility of the FPGA.
摘要翻译： FPGA具有由可编程输入/输出单元（PIC）环形围绕的可编程逻辑单元（PLC）阵列。在一个实施例中，每对相邻PICs的焊盘以及两个PIC中的每一个的内部路由资源可编程地连接到单个全局信号脊柱，并且脊柱可编程地直接连接到垂直的一半分支机构然后，每个分支可以连接到阵列的两个相邻行/列中的单元格，以向阵列中的任何单元提供全局信号，而仅在设备的每两行/列中使用分支。减少数量的脊对分支连接减少了脊柱上的电容负载，从而增加了全局信号可以传输的速度。此外，在相邻PIC之间共享脊椎将FPGA中的脊柱数量减少一半，从而为其他资源提供额外的布局空间。共享分支也具有与共享刺激相同的效果，因为分支数量减少了一半，也增加了全球信号速度。这些优点在不降低FPGA的编程灵活性的情况下实现。

2. 发明授权

US6124732A Signaling voltage range discriminator 失效
标题翻译：信号电压范围鉴别器
公开(公告)号：US6124732A
公开(公告)日：2000-09-26
申请号：US115683
申请日：1998-07-15
申请人： Zeljko Zilic , Ho T. Nguyen , Gary P. Powell , William B. Andrews , Richard G. Stuby, Jr.
发明人： Zeljko Zilic , Ho T. Nguyen , Gary P. Powell , William B. Andrews , Richard G. Stuby, Jr.
IPC分类号： H03K19/0185 , H03K19/0175
CPC分类号： H03K19/018585
摘要： The invention provides an input/output (I/O) signaling voltage range discriminator (and corresponding method) which is used to control a configurable logic device such as a configurable I/O buffer in a second electronic circuit in response to a detected signaling voltage range of a first electronic circuit. The discriminator outputs an indication of the signaling voltage range of the first electronic circuit to a configurable I/O buffer enabling it to adapt to the signaling levels used by the first electronic circuit. The I/O buffer, based on the indication provided by the discriminator, can then configure its logic to become tolerant and/or compatible with digital signals transferred to and from the first electronic circuit.
摘要翻译：本发明提供了一种输入/输出（I / O）信令电压范围鉴别器（和相应的方法），其用于响应于检测到的信号电压来控制可配置逻辑器件，例如第二电子电路中的可配置I / O缓冲器第一电子电路的范围。鉴别器将第一电子电路的信号电压范围的指示输出到可配置的I / O缓冲器，使其能够适应第一电子电路使用的信号电平。然后，基于鉴别器提供的指示，I / O缓冲器可以将它的逻辑配置成容忍和/或与传送到第一电子电路的数字信号兼容。

3. 发明授权

US6020755A Hybrid programmable gate arrays 失效
标题翻译：混合可编程门阵列
公开(公告)号：US6020755A
公开(公告)日：2000-02-01
申请号：US938550
申请日：1997-09-26
申请人： William B. Andrews , Barry K. Britton , Thomas J. Hickey , Ronald T. Modo , Ho T. Nguyen , Lorraine L. Schadt , Satwant Singh
发明人： William B. Andrews , Barry K. Britton , Thomas J. Hickey , Ronald T. Modo , Ho T. Nguyen , Lorraine L. Schadt , Satwant Singh
IPC分类号： H01L21/82 , H03K19/177
CPC分类号： H03K19/17796 , H03K19/17732
摘要： A single integrated circuit (IC) having one or more regions of mask-programmed device (MPD) logic for implementing permanent functions and one or more regions of field-programmable gate-array (FPGA) logic for implementing user-specified functions. The FPGA-type logic provides programming flexibility, while the MPD-type logic provides size, speed, functionality, and dollar cost advantages. In one embodiment, a hybrid IC has an array of programmable logic cells (PLCs) implemented using FPGA-type logic, an application-specific block (ASB) implemented using MPD-type logic, and a ring of pads. Fast interface switch hierarchy (FISH) cells provide the interface between the PLC array and the pads, between the PLC array and the ASB, and between the ASB and the pad ring. Muxes in the FISH cells can be programmed to cause the FISH cells to operate either (1) as programmable interface cells (PICs) that provide a direct interface between the PLC array and the pad ring or (2) as ASB-interface cells (AICs) that (a) provide interfaces between the PLC array and the ASB and (b) control interfaces between the ASB and the pad ring.
摘要翻译：具有用于实现永久功能的一个或多个屏蔽编程设备（MPD）逻辑区域的单个集成电路（IC）和用于实现用户指定功能的现场可编程门阵列（FPGA）逻辑的一个或多个区域。 FPGA型逻辑提供编程灵活性，而MPD型逻辑提供了大小，速度，功能和美元成本优势。在一个实施例中，混合IC具有使用FPGA类型逻辑实现的可编程逻辑单元阵列（PLC）阵列，使用MPD型逻辑实现的特定应用块（ASB）和一个垫环阵列。快速接口交换层次（FISH）单元提供PLC阵列与PLC之间，PLC阵列与ASB之间以及ASB与焊盘环之间的接口。可以对FISH单元中的复用器进行编程，以使FISH单元（1）作为可编程接口单元（PIC）来操作，这些可编程接口单元（PIC）可在PLC阵列和焊盘环之间提供直接接口，或（2）作为ASB接口单元（AIC））（a）提供PLC阵列和ASB之间的接口，（b）控制ASB和焊盘环之间的接口。

4. 发明授权

US07034596B2 Adaptive input logic for phase adjustments 有权
标题翻译：用于相位调整的自适应输入逻辑
公开(公告)号：US07034596B2
公开(公告)日：2006-04-25
申请号：US10365083
申请日：2003-02-11
申请人： William B. Andrews , Harold Scholz , Barry K. Britton
发明人： William B. Andrews , Harold Scholz , Barry K. Britton
IPC分类号： H03K3/00
CPC分类号： H03L7/0814 , H03K5/133 , H03K2005/00058 , H03L7/0818 , H04L7/0041 , H04L7/0337
摘要： Systems and methods are disclosed to provide static and/or dynamic phase adjustments to a data signal relative to a clock signal. For example, the data signal may be delayed by a coarse delay and/or a fine delay to match the timing of the clock signal independently for each input path (e.g., per input pad). The delay may be as a function of positive and/or negative clock edges.
摘要翻译：公开了系统和方法以相对于时钟信号为数据信号提供静态和/或动态相位调整。例如，数据信号可以被延迟粗略的延迟和/或精细的延迟，以针对每个输入路径（例如，每个输入焊盘）独立地匹配时钟信号的定时。延迟可以是正和/或负时钟边缘的函数。

5. 发明授权

US07262630B1 Programmable termination for single-ended and differential schemes 有权
标题翻译：单端和差分方案的可编程终端
公开(公告)号：US07262630B1
公开(公告)日：2007-08-28
申请号：US11194356
申请日：2005-08-01
申请人： William B. Andrews , Barry K. Britton , John Schadt , Mou C. Lin
发明人： William B. Andrews , Barry K. Britton , John Schadt , Mou C. Lin
IPC分类号： H03K19/003
CPC分类号： H03K19/17744 , H04L25/0278
摘要： In one embodiment of the invention, a programmable termination structure has first and second termination circuits for corresponding pads and a programmable connection therebetween. The first termination circuit supports first and second sets of termination schemes. A shared resistor is part of at least one termination scheme in each set. The first termination circuit supports a termination scheme between the first pad and a user-defined node connected to an on-chip capacitor such that first pad is connected via the termination scheme to the on-chip capacitor. Control circuitry automatically turns on and off a termination scheme for bidirectional signaling supported by the first termination circuit, wherein (1) the control circuitry turns off the termination scheme if an output buffer is configured to present outgoing signals at the first pad and (2) the control circuitry turns on the termination scheme if the output buffer is disabled in order to terminate incoming signals received at the first pad.
摘要翻译：在本发明的一个实施例中，可编程终端结构具有用于相应焊盘的第一和第二终端电路以及它们之间的可编程连接。第一终端电路支持第一和第二组终端方案。共享电阻是每组中至少一个终端方案的一部分。第一终端电路支持第一焊盘和连接到片上电容器的用户定义节点之间的终止方案，使得第一焊盘通过端接方案连接到片上电容器。控制电路自动打开和关闭由第一终端电路支持的用于双向信令的终止方案，其中（1）如果输出缓冲器被配置为在第一焊盘处呈现输出信号，则控制电路关闭终止方案，（2）如果禁止输出缓冲器以便终止在第一焊盘处接收到的输入信号，则控制电路接通终止方案。

6. 发明授权

US06472904B2 Double data rate input and output in a programmable logic device 有权
标题翻译：可编程逻辑器件中的双数据速率输入和输出
公开(公告)号：US06472904B2
公开(公告)日：2002-10-29
申请号：US09864284
申请日：2001-05-25
申请人： William B. Andrews , Barry K. Britton
发明人： William B. Andrews , Barry K. Britton
IPC分类号： H03K19173
CPC分类号： G06F1/10 , H03K5/13 , H03K5/133 , H03K19/017581 , H03K19/17732 , H03K19/17736 , H03K19/1774 , H03K19/17744 , H03K19/17748 , H03K19/1776 , H03K19/17788 , H03K19/17792 , H03L7/081 , H03L7/0996
摘要： A multi-functional programmable I/O buffer in a Field Programmable Gate Array (FPGA) device. The I/O buffer is programmably configurable to meet any of a wide range of I/O standards, be it single ended or differential, 5V, 3.3V, 2.5V or 1.5V logic, without the need for implementing multiple I/O buffers to properly handle each different iteration of I/O requirements. An embedded, internal programmable resistor (e.g., a programmable 100 ohm resistor) is programmably selected for use in differential I/O applications, thus eliminating the conventional requirement for the use of an external resistor connected to each differential receiver I/O pin. The present invention also separates I/O pads into groups in each of a plurality of banks in a programmable device (e.g., PLD, FPGA, etc.), with each group being separately powered by the user. The disclosed multi-functional I/O buffer may be programmably configured by the user to be, e.g., a single ended receiver or transmitter, a reference receiver or transmitter, or a differential receiver or transmitter. The pad logic of the multi-functional I/O buffer may include a double data rate input and output mode, each of which includes two flip-flop devices operating on opposite sides of a data clock signal. One of the two flip-flop devices may be borrowed from another logic element, e.g., from a shift register logic element.
摘要翻译：现场可编程门阵列（FPGA）设备中的多功能可编程I / O缓冲器。 I / O缓冲器可编程配置，可满足任何I / O标准，无论是单端还是差分5V，3.3V，2.5V或1.5V逻辑，无需实现多个I / O缓冲器以适当地处理每个不同的I / O要求的迭代。嵌入式内部可编程电阻器（例如，可编程100欧姆电阻器）可编程选择用于差分I / O应用，从而消除了使用连接到每个差分接收器I / O引脚的外部电阻器的常规要求。本发明还将可编程器件（例如，PLD，FPGA等）中的I / O焊盘分成多个组中的每个组中的每个组，每个组由用户单独供电。所公开的多功能I / O缓冲器可由用户可编程地配置为例如单端接收器或发射器，参考接收器或发射器，或差分接收器或发射器。多功能I / O缓冲器的焊盘逻辑可以包括双数据速率输入和输出模式，每个数据速率输入和输出模式包括在数据时钟信号的相对侧上操作的两个触发器装置。两个触发器装置中的一个可以从另一个逻辑元件借用，例如来自移位寄存器逻辑元件。

7. 发明授权

US6028447A FPGA having predictable open-drain drive mode 失效
标题翻译： FPGA具有可预测的开漏驱动模式
公开(公告)号：US6028447A
公开(公告)日：2000-02-22
申请号：US899428
申请日：1997-07-24
申请人： William B. Andrews , James F. Hoff , Satwant Singh
发明人： William B. Andrews , James F. Hoff , Satwant Singh
IPC分类号： H01L21/82 , H03K19/173 , H03K19/177 , G06F7/38 , H01L25/00
CPC分类号： H03K19/1736
摘要： A field-programmable gate array (FPGA) having at least one programmable cell (e.g., an input/output (I/O) cell) having an output node circuit (e.g., a pad circuit) in which the output data signal and the tri-state signal are applied to a multiplexer that drives the tri-state port of an output buffer in the output node circuit. This configuration enables the output node circuit to be configured for open drain drive mode operations in a fast, predictable manner that does not need to rely on the FPGA's general routing resources.
摘要翻译：具有至少一个可编程单元（例如，输入/输出（I / O）单元）的现场可编程门阵列（FPGA）具有输出节点电路（例如，pad电路），其中输出数据信号和三状态信号被施加到驱动输出节点电路中的输出缓冲器的三态端口的多路复用器。该配置使得输出节点电路能够以不需要依赖于FPGA的通用路由资源的快速，可预测的方式配置为开漏驱动模式操作。

8. 发明授权

US07495467B2 Temperature-independent, linear on-chip termination resistance 有权
标题翻译：温度独立，线性片上终端电阻
公开(公告)号：US07495467B2
公开(公告)日：2009-02-24
申请号：US11300886
申请日：2005-12-15
申请人： Mou C. Lin , William B. Andrews , John A. Schadt
发明人： Mou C. Lin , William B. Andrews , John A. Schadt
IPC分类号： H03K17/16
CPC分类号： H04L25/0298 , H01L28/20
摘要： In one embodiment of the invention, an integrated circuit, such as an FPGA, has one or more programmable termination schemes, each having a plurality of resistive termination legs connected in parallel, and a calibration circuit designed to control each termination scheme for process, voltage, and temperature (PVT) variations. The sense element in the calibration circuit and each resistive leg in each termination scheme has a transistor-based transmission gate connected in series with a non-silicided poly (NSP) resistor. The negative temperature coefficient of resistivity of each NSP resistor offsets the positive temperature coefficient of resistivity of the corresponding transmission gate to provide a temperature-independent sense element and temperature-independent termination legs. The temperature-independence and constant IV characteristic of the sense element and termination legs enable a single calibration circuit to simultaneously control multiple termination schemes operating at different termination voltage levels.
摘要翻译：在本发明的一个实施例中，诸如FPGA的集成电路具有一个或多个可编程端接方案，每个可编程端接方案具有并联连接的多个电阻端接支路，以及被设计成控制每个端接方案用于处理电压的校准电路，和温度（PVT）变化。校准电路中的感测元件和每个端接方案中的每个电阻支路具有与非硅化聚（NSP）电阻器串联连接的基于晶体管的传输栅极。每个NSP电阻器的负温度系数抵消相应传输门的电阻率的正温度系数，以提供与温度无关的感测元件和温度独立的端接脚。感测元件和终端支路的温度独立性和恒定IV特性使得单个校准电路能够同时控制在不同终端电压电平下工作的多个终端方案。

9. 发明授权

US07714608B1 Temperature-independent, linear on-chip termination resistance 有权
标题翻译：温度独立，线性片上终端电阻
公开(公告)号：US07714608B1
公开(公告)日：2010-05-11
申请号：US12370039
申请日：2009-02-12
申请人： Mou C. Lin , William B. Andrews , John A. Schadt
发明人： Mou C. Lin , William B. Andrews , John A. Schadt
IPC分类号： H03K17/16
CPC分类号： H04L25/0298 , H01L28/20
摘要： In one embodiment, an integrated circuit, such as an FPGA, has one or more programmable termination schemes, each having a plurality of resistive termination legs connected in parallel, and a calibration circuit designed to control each termination scheme for process, voltage, and temperature (PVT) variations. A sense element in the calibration circuit and each resistive leg in each termination scheme has a transistor-based transmission gate connected in series with a non-silicided poly (NSP) resistor. The negative temperature coefficient of resistivity of each NSP resistor offsets the positive temperature coefficient of resistivity of the corresponding transmission gate to provide a temperature-independent sense element and temperature-independent termination legs. The temperature-independence and constant IV characteristic of the sense element and termination legs enable a single calibration circuit to simultaneously control multiple termination schemes operating at different termination voltage levels.
摘要翻译：在一个实施例中，诸如FPGA的集成电路具有一个或多个可编程端接方案，每个可编程端接方案具有并联连接的多个电阻端接支路，以及设计成控制处理，电压和温度的每个端接方案的校准电路（PVT）变化。校准电路中的感测元件和每个端接方案中的每个电阻支路具有与非硅化聚（NSP）电阻器串联连接的基于晶体管的传输栅极。每个NSP电阻器的负温度系数抵消相应传输门的电阻率的正温度系数，以提供与温度无关的感测元件和温度独立的端接脚。感测元件和终端支路的温度独立性和恒定IV特性使得单个校准电路能够同时控制在不同终端电压电平下工作的多个终端方案。

10. 发明授权

US07616029B1 Hysteresis-based processing for applications such as signal bias monitors 有权
标题翻译：用于诸如信号偏置监视器的应用的基于滞后的处理
公开(公告)号：US07616029B1
公开(公告)日：2009-11-10
申请号：US11869019
申请日：2007-10-09
申请人： William B. Andrews , Phillip Johnson , John Schadt , Harold Scholz
发明人： William B. Andrews , Phillip Johnson , John Schadt , Harold Scholz
IPC分类号： H03K5/22
CPC分类号： H03K19/20
摘要： In one embodiment of the invention, a bias signal monitor has two signal comparators that compare two (power supply) voltages at two different bias points and a logic circuit that processes the outputs from the two signal monitors to generate a bias signal monitor output signal. The logic circuit implements hysteresis-based processing such that (1) if both signal comparators are active (indicating that a first voltage is greater than the second voltage relative to both bias points), then the monitor output is active, (2) if both signal comparators are inactive (indicating that the first voltage is not greater than the second voltage relative to either bias point), then the monitor output is inactive, and (3) if one signal comparator is active and the other is inactive, then the monitor output keeps its previous value. This hysteresis characteristic prevents relatively small oscillations between the voltages from changing the monitor output.
摘要翻译：在本发明的一个实施例中，偏置信号监视器具有两个信号比较器，其比较两个不同偏置点处的两个（电源）电压;以及逻辑电路，其处理来自两个信号监视器的输出以产生偏置信号监视输出信号。逻辑电路实现基于滞后的处理，使得（1）如果两个信号比较器都是有效的（指示第一个电压相对于两个偏置点大于第二个电压），则监视器输出是有效的，（2）如果两个信号比较器无效（表示第一个电压不大于相对于任一偏置点的第二个电压），则监视器输出无效，（3）如果一个信号比较器处于活动状态，另一个不起作用，则监视器输出保持其以前的值。这种滞后特性防止了改变监视器输出的电压之间的相对小的振荡。

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