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1. 发明授权

US07714608B1 Temperature-independent, linear on-chip termination resistance 有权
标题翻译：温度独立，线性片上终端电阻
公开(公告)号：US07714608B1
公开(公告)日：2010-05-11
申请号：US12370039
申请日：2009-02-12
申请人： Mou C. Lin , William B. Andrews , John A. Schadt
发明人： Mou C. Lin , William B. Andrews , John A. Schadt
IPC分类号： H03K17/16
CPC分类号： H04L25/0298 , H01L28/20
摘要： In one embodiment, an integrated circuit, such as an FPGA, has one or more programmable termination schemes, each having a plurality of resistive termination legs connected in parallel, and a calibration circuit designed to control each termination scheme for process, voltage, and temperature (PVT) variations. A sense element in the calibration circuit and each resistive leg in each termination scheme has a transistor-based transmission gate connected in series with a non-silicided poly (NSP) resistor. The negative temperature coefficient of resistivity of each NSP resistor offsets the positive temperature coefficient of resistivity of the corresponding transmission gate to provide a temperature-independent sense element and temperature-independent termination legs. The temperature-independence and constant IV characteristic of the sense element and termination legs enable a single calibration circuit to simultaneously control multiple termination schemes operating at different termination voltage levels.
摘要翻译：在一个实施例中，诸如FPGA的集成电路具有一个或多个可编程端接方案，每个可编程端接方案具有并联连接的多个电阻端接支路，以及设计成控制处理，电压和温度的每个端接方案的校准电路（PVT）变化。校准电路中的感测元件和每个端接方案中的每个电阻支路具有与非硅化聚（NSP）电阻器串联连接的基于晶体管的传输栅极。每个NSP电阻器的负温度系数抵消相应传输门的电阻率的正温度系数，以提供与温度无关的感测元件和温度独立的端接脚。感测元件和终端支路的温度独立性和恒定IV特性使得单个校准电路能够同时控制在不同终端电压电平下工作的多个终端方案。

2. 发明授权

US07443192B1 Output buffer with digital slew control 有权
标题翻译：输出缓冲器，带数字转换控制
公开(公告)号：US07443192B1
公开(公告)日：2008-10-28
申请号：US11643288
申请日：2006-12-21
申请人： William B. Andrews , Mou C. Lin , John A. Schadt
发明人： William B. Andrews , Mou C. Lin , John A. Schadt
IPC分类号： H03K19/003
CPC分类号： H03K19/00369
摘要： An improved output buffer having a digital output slew control and compensation for manufacturing process variations. Output slewing is accomplished by sequencing digital drive signals to paralleled output transistors. In one embodiment, a pre-driver sequences the drive signals by using the propagation delays of serially coupled digital logic gates to reduce power supply droop and/or ground bounce. The output transistors are turned off substantially simultaneously to avoid undesirable power supply DC current flow when the output buffer changes state. Programmably configuring the number of paralleled transistors that may be turned on at any given time allows a user to compensate for manufacturing process variations and determine the output impedance/drive capacity of the buffer.
摘要翻译：一种改进的输出缓冲器，具有数字输出摆幅控制和补偿制造工艺变化。输出回转是通过将数字驱动信号排列成并联的输出晶体管来实现的。在一个实施例中，预驱动器通过使用串行数字逻辑门的传播延迟来排序驱动信号，以减少电源下降和/或地面反弹。输出晶体管基本上同时截止，以避免在输出缓冲器改变状态时不期望的电源DC电流流动。可编程地配置可以在任何给定时间导通的并联晶体管的数量允许用户补偿制造工艺变化并确定缓冲器的输出阻抗/驱动能力。

3. 发明授权

US06877667B1 Integrated circuit and associated design method with antenna error control using spare gates 有权
标题翻译：集成电路及相关设计方法，采用备用门控进行天线误差控制
公开(公告)号：US06877667B1
公开(公告)日：2005-04-12
申请号：US10640804
申请日：2003-08-13
申请人： Jay H. Angle , Christopher D. Gorsuch , Oscar G. Mercado , Anthony K. Myers , John A. Schadt , Brian W. Yeager
发明人： Jay H. Angle , Christopher D. Gorsuch , Oscar G. Mercado , Anthony K. Myers , John A. Schadt , Brian W. Yeager
IPC分类号： G06F17/50 , G06K19/06 , H01L21/8238 , H01L27/118
CPC分类号： G06F17/5068 , H01L27/11807
摘要： Antenna errors are corrected in an integrated circuit design utilizing spare gates distributed throughout the integrated circuit. An integrated circuit in accordance with the invention includes standard cells interspersed with spare gates. For example, the circuit may include one or more rows of spare gates arranged between groups of rows of standard cells, or islands of spare gates arranged between groups of rows of standard cells. A signal line of the integrated circuit having a detected antenna error associated therewith is coupled via one or more conductors associated with at least one metal layer of the integrated circuit to a diode or other antenna error control circuitry formed using at least one of the spare gates. The standard cells and spare gates are preferably placed in accordance with a placement operation of an automated place and route process of a standard cell computer-aided design (CAD) tool. The coupling of the signal line having the detected antenna error associated therewith to the antenna error control circuitry formed using at least one of the spare gates is preferably determined as part of a routing operation of the automated place and route process of the standard cell CAD tool. The spare gates are preferably implemented as spare gate cells using a base transistor structure compatible with the standard cell CAD tool.
摘要翻译：在利用分布在整个集成电路中的备用门的集成电路设计中校正天线误差。根据本发明的集成电路包括散布有备用门的标准单元。例如，电路可以包括布置在标准单元行的行之间的一行或多行备用门，或者排列在标准单元行的组之间的备用栅岛。具有与其相关联的检测到的天线误差的集成电路的信号线经由与集成电路的至少一个金属层相关联的一个或多个导体耦合到使用至少一个备用栅极形成的二极管或其他天线误差控制电路。标准电池和备用门优选地根据标准电池计算机辅助设计（CAD）工具的自动化位置和路线过程的放置操作放置。具有与之相关的检测到的天线误差的信号线与使用至少一个备用门形成的天线误差控制电路的耦合优选地被确定为标准单元CAD工具的自动化位置和路线过程的路由操作的一部分。备用门优选地实现为使用与标准单元CAD工具兼容的基本晶体管结构的备用栅极单元。

4. 发明授权

US06822477B1 Integrated circuit and associated design method using spare gate islands 有权
标题翻译：使用备用栅极岛的集成电路和相关设计方法
公开(公告)号：US06822477B1
公开(公告)日：2004-11-23
申请号：US10600042
申请日：2003-06-20
申请人： Craig Bingert , Christopher D. Gorsuch , Oscar G. Mercado , Anthony K. Myers , John A. Schadt , Brian W. Yeager
发明人： Craig Bingert , Christopher D. Gorsuch , Oscar G. Mercado , Anthony K. Myers , John A. Schadt , Brian W. Yeager
IPC分类号： H03K19117
CPC分类号： H01L27/11807
摘要： An integrated circuit includes standard cells interspersed with islands of spare gates. The spare gates are arranged in multiple groups of spare gates, with each group of spare gates within a corresponding designated spare gate area of a standard cell portion of the integrated circuit. At least a given one of the groups of spare gates is arranged between first and second rows of the standard cells and includes one or more rows of spare gates. The spare gate islands may be distributed throughout the standard cell portion of the integrated circuit in a substantially uniform manner, for example, in accordance with a predetermined geometric pattern. The spare gates may be converted to active gates in conjunction with the automated place and route process using only conductors in one or more metal layers of the integrated circuit.
摘要翻译：集成电路包括散布有备用栅极岛的标准单元。备用门被布置在多组备用门中，每组备用门位于集成电路的标准单元部分的对应的指定备用栅极区域内。这些备用门组中的至少一个组被布置在标准单元的第一行和第二行之间，并且包括一行或多行备用门。备用栅极岛可以以基本上均匀的方式分布在集成电路的整个标准单元部分，例如根据预定的几何图形。结合仅使用集成电路的一个或多个金属层中的导体的自动化位置和布线处理，可将备用栅极转换为有源栅极。

5. 发明授权

US06814296B2 Integrated circuit and associated design method with antenna error control using spare gates 失效
标题翻译：集成电路及相关设计方法，采用备用门控进行天线误差控制
公开(公告)号：US06814296B2
公开(公告)日：2004-11-09
申请号：US10135308
申请日：2002-04-30
申请人： Jay H. Angle , Christopher D. Gorsuch , Oscar G. Mercado , Anthony K. Myers , John A. Schadt , Brian W. Yeager
发明人： Jay H. Angle , Christopher D. Gorsuch , Oscar G. Mercado , Anthony K. Myers , John A. Schadt , Brian W. Yeager
IPC分类号： G06K1906
CPC分类号： G06F17/5068 , H01L27/11807
摘要： Antenna errors are corrected in an integrated circuit design utilizing spare gates distributed throughout the integrated circuit. An integrated circuit in accordance with the invention includes standard cells interspersed with spare gates. For example, the circuit may include one or more rows of spare gates arranged between groups of rows of standard cells, or islands of spare gates arranged between groups of rows of standard cells. A signal line of the integrated circuit having a detected antenna error associated therewith is coupled via one or more conductors associated with at least one metal layer of the integrated circuit to a diode or other antenna error control circuitry formed using at least one of the spare gates. The standard cells and spare gates are preferably placed in accordance with a placement operation of an automated place and route process of a standard cell computer-aided design (CAD) tool. The coupling of the signal line having the detected antenna error associated therewith to the antenna error control circuitry formed using at least one of the spare gates is preferably determined as part of a routing operation of the automated place and route process of the standard cell CAD tool. The spare gates are preferably implemented as spare gate cells using a base transistor structure compatible with the standard cell CAD tool.
摘要翻译：在利用分布在整个集成电路中的备用门的集成电路设计中校正天线误差。根据本发明的集成电路包括散布有备用门的标准单元。例如，电路可以包括布置在标准单元行的行之间的一行或多行备用门，或者排列在标准单元行的组之间的备用栅岛。具有与其相关联的检测到的天线误差的集成电路的信号线经由与集成电路的至少一个金属层相关联的一个或多个导体耦合到使用至少一个备用栅极形成的二极管或其他天线误差控制电路。标准电池和备用门优选地根据标准电池计算机辅助设计（CAD）工具的自动化位置和路线过程的放置操作放置。具有与之相关的检测到的天线误差的信号线与使用至少一个备用门形成的天线误差控制电路的耦合优选地被确定为标准单元CAD工具的自动化位置和路线过程的路由操作的一部分。备用门优选地实现为使用与标准单元CAD工具兼容的基本晶体管结构的备用栅极单元。

6. 发明授权

US06600341B2 Integrated circuit and associated design method using spare gate islands 有权
公开(公告)号：US06600341B2
公开(公告)日：2003-07-29
申请号：US10135325
申请日：2002-04-30
申请人： Craig Bingert , Christopher D. Gorsuch , Oscar G. Mercado , Anthony K. Myers , John A. Schadt , Brian W. Yeager
发明人： Craig Bingert , Christopher D. Gorsuch , Oscar G. Mercado , Anthony K. Myers , John A. Schadt , Brian W. Yeager
IPC分类号： H03K1900
CPC分类号： H01L27/11807
摘要： An integrated circuit includes standard cells interspersed with islands of spare gates. The spare gates are arranged in multiple groups of spare gates, with each group of spare gates within a corresponding designated spare gate area of a standard cell portion of the integrated circuit. At least a given one of the groups of spare gates is arranged between first and second rows of the standard cells and includes one or more rows of spare gates, with each row of spare gates including multiple base transistor structures arranged adjacent to one another along longitudinal dimensions of the structures. The standard cells and spare gates are preferably placed in accordance with a placement operation of an automated place and route process of a standard cell computer-aided design (CAD) tool. The spare gates may be implemented using a base transistor structure compatible with the standard cell CAD tool. The spare gate islands may be distributed throughout the standard cell portion of the integrated circuit in a substantially uniform manner, for example, in accordance with a predetermined geometric pattern. The spare gates may be converted to active gates in conjunction with the automated place and route process using only conductors in one or more metal layers of the integrated circuit.

7. 发明授权

US1783675A School desk and seat cover 失效
标题翻译：书桌和座椅套
公开(公告)号：US1783675A
公开(公告)日：1930-12-02
申请号：US33222329
申请日：1929-01-12
申请人： JOHN A SCHADT
发明人： ROBERTS SAMUEL J
IPC分类号： A47B41/02
CPC分类号： A47B41/02

8. 发明授权

US07547995B1 Dynamic over-voltage protection scheme for interface circuitry 有权
标题翻译：接口电路的动态过压保护方案
公开(公告)号：US07547995B1
公开(公告)日：2009-06-16
申请号：US11345713
申请日：2006-02-02
申请人： William B. Andrews , Larry R Fenstermaker , John A. Schadt , Mou C. Lin
发明人： William B. Andrews , Larry R Fenstermaker , John A. Schadt , Mou C. Lin
IPC分类号： H01H9/54
CPC分类号： H03K19/00315 , Y10T307/944
摘要： In one embodiment of the invention, an integrated device has interface circuitry that includes a dynamic monitor that monitors the relative potential between (at least) two different power supplies to enable the device to react to over-voltage conditions such that appropriate selections can be made for which power supplies are selected for different components in the interface circuitry, such as output drivers and input receivers. The dynamic monitor enables over-voltage protection to be automatically implemented before the device has been configured, such as during the device's power-on state.
摘要翻译：在本发明的一个实施例中，集成器件具有接口电路，该接口电路包括监视（至少）两个不同电源之间的相对电位的动态监视器，以使器件能够对过电压条件作出反应，从而可以进行适当的选择为接口电路中的不同组件选择哪个电源，例如输出驱动器和输入接收器。动态监视器可以在设备配置之前自动实现过电压保护，例如在设备通电状态期间。

9. 发明授权

US07129749B1 Programmable logic device having a configurable DRAM with transparent refresh 有权
标题翻译：具有可配置DRAM和可透明刷新的可编程逻辑器件
公开(公告)号：US07129749B1
公开(公告)日：2006-10-31
申请号：US10974305
申请日：2004-10-27
申请人： Larry R. Fenstermaker , John A. Schadt , Mou C. Lin
发明人： Larry R. Fenstermaker , John A. Schadt , Mou C. Lin
IPC分类号： H03K19/177
CPC分类号： H03K19/17748 , H03K19/1776 , H03K19/17764 , H03K19/1778
摘要： A programmable logic device (PLD) having a programmable routing structure that employs non-static memory cells, such as dynamic random access memory (DRAM) cells, to control configurable circuit elements, such as pass-transistors and/or MUXes. In a representative embodiment, each DRAM cell is connected to its corresponding configurable circuit element using a buffer adapted to stabilize the output voltage generated by the cell and offset the effect of charge leakage from the cell capacitor. In addition, refresh circuitry associated with the DRAM cell periodically restores the charge in the cell capacitor using a refresh operation that is performed in the background, without disturbing the user functions of the PLD. Advantageously, a relatively large capacitance associated with a DRAM cell makes a PLD of the invention less susceptible to soft errors than a prior-art PLD that relies on SRAM cells for configuration control of its routing structure.
摘要翻译：具有可编程路由结构的可编程逻辑器件（PLD），其使用诸如动态随机存取存储器（DRAM）单元的非静态存储器单元来控制可配置的电路元件，例如传输晶体管和/或MUX。在代表性的实施例中，每个DRAM单元使用缓冲器连接到其对应的可配置电路元件，该缓冲器适于稳定由单元产生的输出电压并抵消来自单元电容器的电荷泄漏的影响。此外，与DRAM单元相关联的刷新电路使用在后台执行的刷新操作来周期性地恢复单元电容器中的电荷，而不会干扰PLD的用户功能。有利地，与DRAM单元相关联的相对大的电容使得本发明的PLD比依赖于SRAM单元的现有技术的PLD更不易受软错误的影响，用于其路由结构的配置控制。

10. 发明授权

US07495467B2 Temperature-independent, linear on-chip termination resistance 有权
标题翻译：温度独立，线性片上终端电阻
公开(公告)号：US07495467B2
公开(公告)日：2009-02-24
申请号：US11300886
申请日：2005-12-15
申请人： Mou C. Lin , William B. Andrews , John A. Schadt
发明人： Mou C. Lin , William B. Andrews , John A. Schadt
IPC分类号： H03K17/16
CPC分类号： H04L25/0298 , H01L28/20
摘要： In one embodiment of the invention, an integrated circuit, such as an FPGA, has one or more programmable termination schemes, each having a plurality of resistive termination legs connected in parallel, and a calibration circuit designed to control each termination scheme for process, voltage, and temperature (PVT) variations. The sense element in the calibration circuit and each resistive leg in each termination scheme has a transistor-based transmission gate connected in series with a non-silicided poly (NSP) resistor. The negative temperature coefficient of resistivity of each NSP resistor offsets the positive temperature coefficient of resistivity of the corresponding transmission gate to provide a temperature-independent sense element and temperature-independent termination legs. The temperature-independence and constant IV characteristic of the sense element and termination legs enable a single calibration circuit to simultaneously control multiple termination schemes operating at different termination voltage levels.
摘要翻译：在本发明的一个实施例中，诸如FPGA的集成电路具有一个或多个可编程端接方案，每个可编程端接方案具有并联连接的多个电阻端接支路，以及被设计成控制每个端接方案用于处理电压的校准电路，和温度（PVT）变化。校准电路中的感测元件和每个端接方案中的每个电阻支路具有与非硅化聚（NSP）电阻器串联连接的基于晶体管的传输栅极。每个NSP电阻器的负温度系数抵消相应传输门的电阻率的正温度系数，以提供与温度无关的感测元件和温度独立的端接脚。感测元件和终端支路的温度独立性和恒定IV特性使得单个校准电路能够同时控制在不同终端电压电平下工作的多个终端方案。

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