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1. 发明授权

US6124732A Signaling voltage range discriminator 失效
标题翻译：信号电压范围鉴别器
公开(公告)号：US6124732A
公开(公告)日：2000-09-26
申请号：US115683
申请日：1998-07-15
申请人： Zeljko Zilic , Ho T. Nguyen , Gary P. Powell , William B. Andrews , Richard G. Stuby, Jr.
发明人： Zeljko Zilic , Ho T. Nguyen , Gary P. Powell , William B. Andrews , Richard G. Stuby, Jr.
IPC分类号： H03K19/0185 , H03K19/0175
CPC分类号： H03K19/018585
摘要： The invention provides an input/output (I/O) signaling voltage range discriminator (and corresponding method) which is used to control a configurable logic device such as a configurable I/O buffer in a second electronic circuit in response to a detected signaling voltage range of a first electronic circuit. The discriminator outputs an indication of the signaling voltage range of the first electronic circuit to a configurable I/O buffer enabling it to adapt to the signaling levels used by the first electronic circuit. The I/O buffer, based on the indication provided by the discriminator, can then configure its logic to become tolerant and/or compatible with digital signals transferred to and from the first electronic circuit.
摘要翻译：本发明提供了一种输入/输出（I / O）信令电压范围鉴别器（和相应的方法），其用于响应于检测到的信号电压来控制可配置逻辑器件，例如第二电子电路中的可配置I / O缓冲器第一电子电路的范围。鉴别器将第一电子电路的信号电压范围的指示输出到可配置的I / O缓冲器，使其能够适应第一电子电路使用的信号电平。然后，基于鉴别器提供的指示，I / O缓冲器可以将它的逻辑配置成容忍和/或与传送到第一电子电路的数字信号兼容。

2. 发明授权

US6043677A Programmable clock manager for a programmable logic device that can implement delay-locked loop functions 失效
标题翻译：可编程逻辑器件的可编程时钟管理器，可实现延迟锁定环路功能
公开(公告)号：US6043677A
公开(公告)日：2000-03-28
申请号：US951128
申请日：1997-10-15
申请人： Lucian R. Albu , Barry K. Britton , Wai-Bor Leung , Richard G. Stuby, Jr. , James A. Thompson , Zeljko Zilic
发明人： Lucian R. Albu , Barry K. Britton , Wai-Bor Leung , Richard G. Stuby, Jr. , James A. Thompson , Zeljko Zilic
IPC分类号： H03K19/177 , H03L7/081 , G06F7/38
CPC分类号： H03K19/1774 , H03L7/0812
摘要： A programmable logic device (PLD), such as a field programmable gate array (FPGA), has a programmable clock manager (PCM) that converts an input clock into at least one output clock and the PCM can perform one or more delay-locked loop (DLL) functions. In one embodiment, the DLL functions include clock delay, duty-cycle adjustment, and clock doubling, where duty-cycle adjustment can optionally be applied independently to the doubled clock cycles.
摘要翻译：诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）具有可编程时钟管理器（PCM），其将输入时钟转换成至少一个输出时钟，并且PCM可以执行一个或多个延迟锁定环（DLL）功能。在一个实施例中，DLL功能包括时钟延迟，占空比调整和时钟倍增，其中占空比调整可以独立地应用于双倍时钟周期。

3. 发明授权

US6028463A Programmable clock manager for a programmable logic device that can generate at least two different output clocks 失效
标题翻译：可编程逻辑器件的可编程时钟管理器可以生成至少两个不同的输出时钟
公开(公告)号：US6028463A
公开(公告)日：2000-02-22
申请号：US949992
申请日：1997-10-15
申请人： Lucian R. Albu , Barry K. Britton , Wai-Bor Leung , Richard G. Stuby, Jr. , James A. Thompson , Zeljko Zilic
发明人： Lucian R. Albu , Barry K. Britton , Wai-Bor Leung , Richard G. Stuby, Jr. , James A. Thompson , Zeljko Zilic
IPC分类号： G06F1/06 , G06F1/08 , H03K19/173 , H03K19/177 , H03L7/081 , H03L7/089 , H03K7/38
CPC分类号： H03K19/1774 , G06F1/06 , G06F1/08 , H03K19/1733 , H03K19/17704 , H03L7/0812 , H03L7/0891
摘要： A programmable logic device (PLD), such as a field programmable gate array (FPGA), has a programmable clock manager (PCM) that converts an input clock into at least two different output clocks having different clock rates. The different output clocks can be used to control different processes either within or outside the FPGA. For example, one output clock can be used to control the FPGA's input/output registers, while a second, faster output clock can be used to control the FPGA's internal registers.
摘要翻译：诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）具有可编程时钟管理器（PCM），其将输入时钟转换成具有不同时钟速率的至少两个不同的输出时钟。不同的输出时钟可用于控制FPGA内部或外部的不同进程。例如，一个输出时钟可用于控制FPGA的输入/输出寄存器，而第二个更快的输出时钟可用于控制FPGA的内部寄存器。

4. 发明授权

US6060902A Programmable clock manager for a programmable logic device that can be programmed without reconfiguring the device 失效
标题翻译：可编程逻辑器件的可编程时钟管理器，可以在不重新配置器件的情况下进行编程
公开(公告)号：US6060902A
公开(公告)日：2000-05-09
申请号：US950448
申请日：1997-10-15
申请人： Lucian R. Albu , Barry K. Britton , Wai-Bor Leung , Richard G. Stuby, Jr. , James A. Thompson , Zeljko Zilic
发明人： Lucian R. Albu , Barry K. Britton , Wai-Bor Leung , Richard G. Stuby, Jr. , James A. Thompson , Zeljko Zilic
IPC分类号： H03K19/177 , G06F7/38
CPC分类号： H03K19/1774
摘要： A programmable logic device (PLD), such as a field programmable gate array (FPGA), has a programmable clock manager (PCM) that converts an input clock into at least one output clock and the PCM can be programmed during PLD operations, without reconfiguring the PLD.
摘要翻译：诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）具有可编程时钟管理器（PCM），其将输入时钟转换为至少一个输出时钟，并且可以在PLD操作期间对PCM进行编程，而无需重新配置 PLD。

5. 发明授权

US08024691B2 Automata unit, a tool for designing checker circuitry and a method of manufacturing hardware circuitry incorporating checker circuitry 有权
标题翻译：自动机单元，一种用于设计检查器电路的工具，以及一种制造结合校验电路的硬件电路的制造方法
公开(公告)号：US08024691B2
公开(公告)日：2011-09-20
申请号：US11864030
申请日：2007-09-28
申请人： Zeljko Zilic , Marc Boulé
发明人： Zeljko Zilic , Marc Boulé
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： The present invention relates to an automata unit, a tool for designing circuitry and/or checker circuitry, and a method for manufacturing hardware circuitry. The automata unit includes an input unit for receiving assertions using Boolean expressions, an automata generator for translating the assertions into automata, and an automata adaptor. The automata generator uses a dual layer symbolic alphabet for representing the assertions, and the automata adaptor adapts automata algorithms so as to support the symbolic alphabet in the generated automata. The tools for designing circuitry and checker circuitry rely on the automata unit, and further include an assertion unit and either a circuit generator or a checker generator.
摘要翻译：本发明涉及自动机单元，用于设计电路和/或检查器电路的工具，以及用于制造硬件电路的方法。自动机单元包括用于使用布尔表达式接收断言的输入单元，用于将断言转换为自动机的自动机发生器和自动机适配器。自动机发生器使用双层符号字母表来表示断言，并且自动机适配器适应自动机算法，以支持生成的自动机中的符号字母表。用于设计电路和检查电路的工具依赖于自动机单元，并且还包括断言单元和电路发生器或检验发生器。

6. 发明申请

US20160166195A1 Energy and Food Consumption Tracking for Weight and Blood Glucose Control 审中-公开
标题翻译：能量和食物消耗跟踪重量和血糖控制
公开(公告)号：US20160166195A1
公开(公告)日：2016-06-16
申请号：US14570070
申请日：2014-12-15
申请人： Katarzyna Radecka , Zeljko Zilic
发明人： Katarzyna Radecka , Zeljko Zilic
IPC分类号： A61B5/00 , G09B19/00 , A61B5/11
CPC分类号： A61B5/486 , A61B5/112 , A61B5/4866 , A61B5/743 , A61B5/7475 , G06F19/3475 , G06F19/3481 , G09B19/0092
摘要： The present invention relates to the area of lifestyle devices and applications, particularly to daily trackers of activities, such as pedometers used for exercise monitoring, and working in collaboration with tools analyzing and planning the food intake and amount of exercises to keep or obtain the desired weight. This invention aims at better controlling: fitness level, food consumption, blood glucose level and weight of a person throughout the day. For daily and weekly tracking of the weight, the ingested and expended calories are reported. Calories meal goals are adjusting daily reflecting the over the goal exercise levels as well as mismatch in food consumed and meal goals. The method for better blood glucose control predicts the effects of the food ingested on raising a post-meal blood glucose level, and suggests a suitable timing and the duration of the exercise following the food intake to minimize a post-meal blood glucose peak.
摘要翻译：本发明涉及生活方式装置和应用的领域，特别是涉及活动的日常跟踪器，例如用于运动监测的计步器，以及与分析和规划食物摄取量和锻炼量的工具协同工作以保持或获得期望的重量。本发明旨在更好地控制一天中的健身水平，食物消耗，血糖水平和体重。对于每天和每周的重量跟踪，报告摄入和消耗的卡路里。卡路里膳食目标每天都在调整，反映了目标运动水平以及食物消耗和膳食目标的不匹配。用于更好的血糖控制的方法预测摄入的食物对提高餐后血糖水平的影响，并且建议适当的时间和食物摄入后的运动持续时间以使餐后血糖峰值最小化。

7. 发明申请

US20160001131A1 Accurate Step Counting Pedometer for Children, Adults and Elderly 审中-公开
标题翻译：儿童，成人和老年人的精确步数计步器
公开(公告)号：US20160001131A1
公开(公告)日：2016-01-07
申请号：US14324055
申请日：2014-07-03
申请人： Katarzyna Radecka , Zeljko Zilic
发明人： Katarzyna Radecka , Zeljko Zilic
IPC分类号： A63B24/00 , G01C22/00
CPC分类号： G01C22/006 , A61B5/1118 , G06F19/3481
摘要： The present invention related to the area of lifestyle devices, particularly to pedometers used for exercise tracking. This invention aims at accurate recording of steps, speeds, distances, type of motion (walk and run) and calories expenditure, independently of the personal characteristics (age, gender, weight and height). The invention uses sub-band decomposition filters that produce non-distorted sine wave regardless of personal traits and the type of walking or running. Low-complexity zero-crossing step detection is subsequently applied, and the step length and energy expenditure information is then extracted. The method for goals tracking is included for independent types of goals: steps, energy, distance and duration.
摘要翻译：本发明涉及生活方式装置的面积，特别是涉及用于锻炼跟踪的计步器。本发明旨在精确地记录步骤，速度，距离，运动类型（步行和跑步）和卡路里消耗，独立于个人特征（年龄，性别，体重和身高）。本发明使用产生非扭曲正弦波的子带分解滤波器，而不管个人特征和步行或跑步的类型。随后应用低复杂度零交叉步骤检测，然后提取步长和能量消耗信息。针对目标跟踪的方法包括用于独立类型的目标：步骤，能量，距离和持续时间。

8. 发明申请

US20080082946A1 AUTOMATA UNIT, A TOOL FOR DESIGNING CHECKER CIRCUITRY AND A METHOD OF MANUFACTURING HARDWARE CIRCUITRY INCORPORATING CHECKER CIRCUITRY 有权
标题翻译： AUTOMATA UNIT，用于设计检查电路的工具和制造检查电路的硬件电路的制造方法
公开(公告)号：US20080082946A1
公开(公告)日：2008-04-03
申请号：US11864030
申请日：2007-09-28
申请人： Zeljko Zilic , Marc Boule
发明人： Zeljko Zilic , Marc Boule
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： The present invention relates to an automata unit, a tool for designing circuitry and/or checker circuitry, and a method for manufacturing hardware circuitry. The automata unit includes an input unit for receiving assertions using Boolean expressions, an automata generator for translating the assertions into automata, and an automata adaptor. The automata generator uses a dual layer symbolic alphabet for representing the assertions, and the automata adaptor adapts automata algorithms so as to support the symbolic alphabet in the generated automata. The tools for designing circuitry and checker circuitry rely on the automata unit, and further include an assertion unit and either a circuit generator or a checker generator.
摘要翻译：本发明涉及自动机单元，用于设计电路和/或检查器电路的工具，以及用于制造硬件电路的方法。自动机单元包括用于使用布尔表达式接收断言的输入单元，用于将断言转换为自动机的自动机发生器和自动机适配器。自动机发生器使用双层符号字母表来表示断言，并且自动机适配器适应自动机算法，以支持生成的自动机中的符号字母表。用于设计电路和检查电路的工具依赖于自动机单元，并且还包括断言单元和电路发生器或检验发生器。

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