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1. 发明授权

US4354228A Flexible processor on a single semiconductor substrate using a plurality of arrays 失效
标题翻译：使用多个阵列的单个半导体衬底上的柔性处理器
公开(公告)号：US4354228A
公开(公告)日：1982-10-12
申请号：US105711
申请日：1979-12-20
申请人： Victor S. Moore , Wayne R. Kraft , Joseph C. Rhodes, Jr. , William L. Stahl, Jr.
发明人： Victor S. Moore , Wayne R. Kraft , Joseph C. Rhodes, Jr. , William L. Stahl, Jr.
IPC分类号： G06F7/00 , G06F9/22 , G06F15/78
CPC分类号： G06F9/223
摘要： A processor is provided that is fabricated on a single semiconductor substrate. The processor includes an AND array for receiving program instructions from input sources external of the processor and for generating product signals. An OR array is provided and interconnected to the AND array for receiving the product signals and for generating a plurality of control signals. A register array receives ones of the plurality of control signals and transfers data between the processor and data sources external of the processor. An arithmetic and logic unit array is also provided on the semiconductor substrate and interconnected to the register array and the OR array for executing operations on data received from the register array in accordance with ones of the plurality of control signals to generate output data. A control register is further provided and is interconnected to the OR array and the AND array for receiving ones of the plurality of control signals for controlling execution of the program instructions within the AND array.
摘要翻译：提供了制造在单个半导体衬底上的处理器。处理器包括用于从处理器外部的输入源接收程序指令并用于产生乘积信号的AND阵列。提供OR阵列并将其互连到AND阵列，用于接收产品信号并产生多个控制信号。寄存器阵列接收多个控制信号中的一个并且在处理器和处理器外部的数据源之间传送数据。还在半导体衬底上提供了一个算术和逻辑单元阵列，并将其与寄存器阵列和OR阵列互连，以根据多个控制信号中的一个从寄存器阵列接收的数据执行操作，以产生输出数据。进一步提供控制寄存器，并且与OR阵列和AND阵列互连，用于接收多个控制信号中的一个，以控制AND阵列内的程序指令的执行。

2. 发明授权

US4594661A Microword control system utilizing multiplexed programmable logic arrays 失效
标题翻译：微控制系统利用多路复用可编程逻辑阵列
公开(公告)号：US4594661A
公开(公告)日：1986-06-10
申请号：US350660
申请日：1982-02-22
申请人： Victor S. Moore , Gerard A. Veneski , Tony E. Parker , Joseph C. Rhodes, Jr. , Wayne R. Kraft , William L. Stahl, Jr.
发明人： Victor S. Moore , Gerard A. Veneski , Tony E. Parker , Joseph C. Rhodes, Jr. , Wayne R. Kraft , William L. Stahl, Jr.
IPC分类号： G06F9/22 , G06F9/28
CPC分类号： G06F9/223 , G06F9/28
摘要： A microword control system is provided for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed digital data processor. This microword control system includes a plurality of programmable logic array mechanisms responsive to the processor instruction to be executed for individually producing different ones of the microwords needed to execute such instruction. This microword control system also includes microword-responsive control circuitry for controlling the operation of the data processor. This microword control system further includes multiplexing circuitry for supplying microwords from different ones of the programmable logic array mechanisms to the control circuitry during different time intervals.
摘要翻译：提供了一种微词控制系统，用于产生用于控制微程序数字数据处理器中处理器指令执行的微词序列。该微词控制系统包括多个可编程逻辑阵列机构，其响应于要执行的处理器指令来单独产生执行该指令所需的不同的微剑。该微词控制系统还包括用于控制数据处理器的操作的微字响应控制电路。该微词控制系统还包括用于在不同的时间间隔期间将不同的可编程逻辑阵列机构的微词提供给控制电路的多路复用电路。

3. 发明授权

US4660171A Apparatus and method using a programmable logic array for decoding an operation code and providing a plurality of sequential output states 失效
标题翻译：一种使用可编程逻辑阵列解码操作码并提供多个顺序输出状态的装置和方法
公开(公告)号：US4660171A
公开(公告)日：1987-04-21
申请号：US332585
申请日：1981-12-21
申请人： Victor S. Moore , Wayne R. Kraft , Joseph C. Rhodes, Jr.
发明人： Victor S. Moore , Wayne R. Kraft , Joseph C. Rhodes, Jr.
IPC分类号： H03K19/177 , G06F9/22 , H03M7/00 , H03K19/20 , H03K13/00
CPC分类号： G06F9/223
摘要： Apparatus and method for decoding computer operation codes. The operation code is decoded into a single product term in the AND array of a programmable logic array. That single product term is then processed through a clock driven sequencer to generate a plurality of sequential product terms. These sequential product terms are decoded by the OR array of the programmable logic array to generate a plurality of sequential time states comprising the decoded operation code.
摘要翻译：用于解码计算机操作码的装置和方法。操作码被解码成可编程逻辑阵列的AND阵列中的单个乘积项。然后通过时钟驱动的定序器处理单个产品术语，以产生多个顺序产品术语。这些顺序乘积项由可编程逻辑阵列的OR阵列解码，以产生包括解码的操作码的多个连续时间状态。

4. 发明授权

US4685080A Microword generation mechanism utilizing separate programmable logic arrays for first and second microwords 失效
标题翻译：微剑生成机制采用独立的可编程逻辑阵列的第一和第二个微词
公开(公告)号：US4685080A
公开(公告)日：1987-08-04
申请号：US350663
申请日：1982-02-22
申请人： Joseph C. Rhodes, Jr. , Victor S. Moore , Wayne R. Kraft , John W. Barrs
发明人： Joseph C. Rhodes, Jr. , Victor S. Moore , Wayne R. Kraft , John W. Barrs
IPC分类号： G06F9/22 , G06F9/28 , G06F9/00
CPC分类号： G06F9/28
摘要： A microword generation mechanism is provided for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed digital data processor. This microword generation mechanism includes a first programmable logic array mechanism responsive to the processor instruction to be executed for providing the first microword needed in the execution of such instruction. This microword generation mechanism also includes a second programmable logic array mechanism responsive to the processor instruction to be executed for providing the second microword needed in the execution of such instruction. This microword generation mechanism further includes at least one additional programmable logic array mechanism responsive to the processor instruction to be executed for providing the remainder of the microwords needed to execute such instruction.
摘要翻译：提供了一种微词生成机制，用于产生用于控制微程序数字数据处理器中的处理器指令的执行的微词序列。该微字生成机构包括响应于要执行的处理器指令以提供执行这样的指令所需的第一微字的第一可编程逻辑阵列机构。该微字生成机构还包括响应于要执行的处理器指令以提供执行这样的指令所需的第二微字的第二可编程逻辑阵列机制。该微字生成机构进一步包括至少一个额外的可编程逻辑阵列机构，其响应于要执行的处理器指令，以提供执行这样的指令所需的其余的微核。

5. 发明授权

US4931989A Microword generation mechanism utilizing a separate programmable logic array for first microwords 失效
标题翻译：微剑生成机制利用单独的可编程逻辑阵列为第一个微词
公开(公告)号：US4931989A
公开(公告)日：1990-06-05
申请号：US38556
申请日：1987-04-15
申请人： Joseph C. Rhodes, Jr. , Victor S. Moore , Wayne R. Kraft , John W. Barrs
发明人： Joseph C. Rhodes, Jr. , Victor S. Moore , Wayne R. Kraft , John W. Barrs
IPC分类号： G06F9/28 , H04N5/225
CPC分类号： G06F9/28 , H04N5/2253
摘要： A microword generation mechanism is provided for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed digital data processor. This microword generation mechanism includes a first programmable logic array mechanism responsive to the processor instruction to be executed for providing the first microword needed in the execution of such instruction. This microword generation mechanism also includes a second programmable logic array mechanism responsive to the processor instruction to be executed for providing the second microword needed in the execution of such instruction. This microword generation mechanism further includes at least one additional programmable logic array mechanism responsive to the processor instruction to be executed for providing the remainder of the microwords needed to execute such instruction.
摘要翻译：提供了一种微词生成机制，用于产生用于控制微程序数字数据处理器中的处理器指令的执行的微词序列。该微字生成机构包括响应于要执行的处理器指令以提供执行这样的指令所需的第一微字的第一可编程逻辑阵列机构。该微字生成机构还包括响应于要执行的处理器指令以提供执行这样的指令所需的第二微字的第二可编程逻辑阵列机制。该微字生成机构进一步包括至少一个额外的可编程逻辑阵列机构，其响应于要执行的处理器指令，以提供执行这样的指令所需的其余的微核。

6. 发明授权

US4531068A Bus line precharging tristate driver circuit 失效
标题翻译：总线预充电三态驱动电路
公开(公告)号：US4531068A
公开(公告)日：1985-07-23
申请号：US533393
申请日：1983-09-19
申请人： Wayne R. Kraft , Victor S. Moore , William L. Stahl, Jr. , Nandor G. Thoma
发明人： Wayne R. Kraft , Victor S. Moore , William L. Stahl, Jr. , Nandor G. Thoma
IPC分类号： H03K19/0175 , H03K5/02 , H03K19/094 , H03K19/20 , H03K19/003
CPC分类号： H03K5/023 , H03K19/09425 , H03K19/09429
摘要： A tristate driver circuit is provided on an integrated circuit chip for driving a bus line or signal line located off of the chip. This circuit very rapidly charges the bus line or signal line to positive voltage level each time and just before it switches to its tristate or high impedance output condition. This eliminates the need for a pull-up resistor or pull-up transistor to be connected to the off-chip bus line or signal line.
摘要翻译：在用于驱动位于芯片外的总线或信号线的集成电路芯片上提供三态驱动器电路。该电路非常快速地将总线或信号线充电至正电压电平，并且恰好在其切换到其三态或高阻抗输出条件之前。这样就不需要连接到片外总线或信号线的上拉电阻或上拉晶体管。

7. 发明授权

US4395646A Logic performing cell for use in array structures 失效
标题翻译：用于阵列结构的逻辑执行单元
公开(公告)号：US4395646A
公开(公告)日：1983-07-26
申请号：US203170
申请日：1980-11-03
申请人： Moises Cases , Wayne R. Kraft , Victor S. Moore , William L. Stahl, Jr. , Nandor G. Thoma
发明人： Moises Cases , Wayne R. Kraft , Victor S. Moore , William L. Stahl, Jr. , Nandor G. Thoma
IPC分类号： H01L27/088 , H01L27/112 , H03K19/0944 , H03K19/177 , H03K19/017 , H03K19/094
CPC分类号： H03K19/1778 , H01L27/0883 , H01L27/112 , H03K19/09445 , H03K19/1772 , H03K19/17728
摘要： A logic performing cell for use in array structures is provided which allows greater density fabrication in integrated circuits and reduces operational delays. The array has a plurality of output lines intercepted by a plurality of orthogonally oriented input lines, with elements in the form of a three terminal device located at each of the intersections of the input and output lines so that logical functions are performed on interrogation signals placed on the input lines and the responses thereto placed on the output lines. The three terminal device transfer gates are connected in groups of series strings which are connected in parallel to a recombination line. These groups of series connected transfer gates comprise a programmed mix of enhancement and depletion devices. Each logic function of each group of transfer gates establishes an output which, when coupled to the recombining output circuit line, provides an overall logic function for the logic performing cell.
摘要翻译：提供了用于阵列结构的逻辑执行单元，其允许在集成电路中进行更大的密度制造并且减少操作延迟。阵列具有由多个正交取向的输入线截取的多个输出线，其中三个终端装置形式的元件位于输入和输出线的每个交叉点处，使得在放置的询问信号上执行逻辑功能在输入线上和对输出线上的响应。三个端子器件传输门以串联串联的方式连接，并联到复合线。这些串联连接的传输门组包括增强和耗尽装置的编程组合。每组传输门的每个逻辑功能建立一个输出，当耦合到重新组合的输出电路线时，该逻辑执行单元提供总逻辑功能。

8. 发明授权

US4488067A Tristate driver circuit with low standby power consumption 失效
标题翻译：三态驱动电路具有低待机功耗
公开(公告)号：US4488067A
公开(公告)日：1984-12-11
申请号：US533392
申请日：1983-09-19
申请人： Wayne R. Kraft , Victor S. Moore , William L. Stahl, Jr. , Nandor G. Thoma
发明人： Wayne R. Kraft , Victor S. Moore , William L. Stahl, Jr. , Nandor G. Thoma
IPC分类号： H03K19/0175 , H03K19/094 , H03K19/20 , H03K19/017
CPC分类号： H03K19/09429
摘要： Improved tristate control circuitry is provided for a driver circuit formed on an integrated circuit chip. A parallel-connected combination of a depletion mode transistor and an enhancement mode transistor is connected in series in the voltage supply path for the driver circuit for controlling whether the driver circuit is in an active mode or a standby mode by controlling the supplying of operating voltage thereto. A further enhancement mode transistor provides a shunting action between the driver circuit side of the parallel-connected transistors and circuit ground to further aid in the control of the driver circuit operating mode.
摘要翻译：为在集成电路芯片上形成的驱动电路提供改进的三态控制电路。耗尽型晶体管和增强型晶体管的并联组合串联连接在用于驱动电路的电压供给路径中，用于通过控制提供工作电压来控制驱动电路是处于活动模式还是待机模式到此。另外的增强模式晶体管在并联晶体管的驱动器电路侧和电路接地之间提供分流动作，以进一步有助于控制驱动器电路工作模式。

9. 发明授权

US4583193A Integrated circuit mechanism for coupling multiple programmable logic arrays to a common bus 失效
标题翻译：用于将多个可编程逻辑阵列耦合到公共总线的集成电路机制
公开(公告)号：US4583193A
公开(公告)日：1986-04-15
申请号：US350681
申请日：1982-02-22
申请人： Wayne R. Kraft , Moises Cases , William L. Stahl, Jr. , Nandor G. Thoma , Virgil D. Wyatt
发明人： Wayne R. Kraft , Moises Cases , William L. Stahl, Jr. , Nandor G. Thoma , Virgil D. Wyatt
IPC分类号： H01L21/822 , G06F9/22 , G06F9/26 , G06F9/28 , H01L21/82 , H01L27/04 , H03K19/173 , H03K19/177 , G06F13/38
CPC分类号： G06F9/28 , G06F9/223 , G06F9/267
摘要： An integrated circuit mechanism is provided for coupling the separate sets of output lines from a plurality of programmable logic arrays to the same set of bus lines of plural-line signal transfer bus. This coupling mechanism includes precharge circuitry for precharging each of the bus lines during a first time interval. This coupling mechanism also includes a separate strobe signal line for each programmable logic array and circuitry for activating one of the strobe signal lines during a second time interval for selecting a particular programmable logic array. This coupling mechanism further includes a separate output buffer for each programmable logic array. Each such output buffer includes a plurality of buffer stages for individually coupling the different ones of the programmable logic array output lines to their respective bus lines. The buffer stages for each programmable logic array are responsive to the strobe signal for its programmable logic array for discharging during the second time interval those bus lines for which its programmable logic array output lines are at a particular binary value.
摘要翻译：提供了一种集成电路机制，用于将分离的输出线组从多个可编程逻辑阵列耦合到多行信号传输总线的同一组总线。该耦合机构包括用于在第一时间间隔期间预充电每个总线的预充电电路。该耦合机构还包括用于每个可编程逻辑阵列的单独选通信号线和用于在用于选择特定可编程逻辑阵列的第二时间间隔期间激活选通信号线之一的电路。该耦合机构还包括用于每个可编程逻辑阵列的单独的输出缓冲器。每个这样的输出缓冲器包括用于将不同的可编程逻辑阵列输出线分别耦合到它们各自的总线的多个缓冲级。每个可编程逻辑阵列的缓冲级响应于其可编程逻辑阵列的选通信号，用于在第二时间间隔期间对其可编程逻辑阵列输出线处于特定二进制值的总线进行放电。

10. 发明授权

US4500800A Logic performing cell for use in array structures 失效
标题翻译：用于阵列结构的逻辑执行单元
公开(公告)号：US4500800A
公开(公告)日：1985-02-19
申请号：US413043
申请日：1982-08-30
申请人： Moises Cases , Wayne R. Kraft , William L. Stahl, Jr. , Nandor G. Thoma
发明人： Moises Cases , Wayne R. Kraft , William L. Stahl, Jr. , Nandor G. Thoma
IPC分类号： H03K19/096 , H03K19/177 , H03K19/017 , H03K17/16
CPC分类号： H03K19/1772 , H03K19/096
摘要： As a specific improvement to a previously known PLA (Programmed Logic Array) structure, formed by FET devices in serially chained charge transfer circuits, the presently disclosed "modified" PLA structure comprises a combination of: (a) level shifting circuitry, integrated into bit partitioning stages of the known structure, for reducing voltage swings in the outputs of those stages and thereby reducing spurious couplings to the following AND array stage as well as decreasing operational delays of the latter stage; (b) discrete capacitance, added at the output end of the OR array stage of the known structure, for sustaining and reinforcing charge conditions accumulated in that stage prior to readout (validation clocking) of that stage; and (c) a source of time related clocking functions coupled to stages of the modified structure, with the timing relationships selected so as to reduce operational delays of the entire structure while improving its integrity of operation.
摘要翻译：作为对先前已知的PLA（编程逻辑阵列）结构的具体改进，由串联链式电荷转移电路中的FET器件形成，目前公开的“修改”PLA结构包括以下组合：（a）电平移位电路，集成到位已知结构的分级级，用于减小这些级的输出中的电压摆幅，从而减少到后续阵列级的寄生耦合，并减少后级的运行延迟; （b）在已知结构的OR阵列阶段的输出端处添加的离散电容，用于在该级的读出（验证时钟）之前维持和加强在该级中累积的充电条件; 以及（c）与所述经修改的结构的阶段耦合的时间相关时钟功能源，选择所述定时关系以便减少整个结构的运行延迟，同时提高其操作的完整性。

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