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1. 发明公开

CN103560782A 与非门电路、显示器背板和显示器有权
公开(公告)号：CN103560782A
公开(公告)日：2014-02-05
申请号：CN201310573352.1
申请日：2013-11-15
申请人：京东方科技集团股份有限公司
发明人：吴仲远 , 宋丹娜 , 段立业
IPC分类号： H03K19/20 , G09G3/20
CPC分类号： H03K19/018507 , H03K19/09441 , H03K19/09445 , H03K19/20
摘要：本发明提供了一种与非门电路、显示器背板和显示器。所述与非门电路包括至少两输入晶体管、至少两个上拉模块和至少两输入控制晶体管；每一输入晶体管的第一极通过该上拉模块与第二电平输出端连接；输入控制晶体管用于当其栅极接入的输入信号为第二电平时，控制使得与该输入晶体管的第一极连接的上拉模块的控制端的电位为第一电平；至少两个上拉模块，用于当所有的输入信号都为第二电平时，断开第二电平输出端与与非门输出端之间的连接，并用于当所有的输入信号不都为第二电平时，导通第二电平输出端与与非门输出端之间的连接。本发明使得当采用耗尽型TFT晶体管时，与非门输出能无损传输，实现与非门输出轨到轨。

2. 发明授权

CN103560782B 与非门电路、显示器背板和显示器有权
公开(公告)号：CN103560782B
公开(公告)日：2015-04-22
申请号：CN201310573352.1
申请日：2013-11-15
申请人：京东方科技集团股份有限公司
发明人：吴仲远 , 宋丹娜 , 段立业
IPC分类号： H03K19/20 , G09G3/20
CPC分类号： H03K19/018507 , H03K19/09441 , H03K19/09445 , H03K19/20
摘要：本发明提供了一种与非门电路、显示器背板和显示器。所述与非门电路包括至少两输入晶体管、至少两个上拉模块和至少两输入控制晶体管；每一输入晶体管的第一极通过该上拉模块与第二电平输出端连接；输入控制晶体管用于当其栅极接入的输入信号为第二电平时，控制使得与该输入晶体管的第一极连接的上拉模块的控制端的电位为第一电平；至少两个上拉模块，用于当所有的输入信号都为第二电平时，断开第二电平输出端与与非门输出端之间的连接，并用于当所有的输入信号不都为第二电平时，导通第二电平输出端与与非门输出端之间的连接。本发明使得当采用耗尽型TFT晶体管时，与非门输出能无损传输，实现与非门输出轨到轨。

3. 发明申请

WO1982004364A1 SPLIT LOAD CIRCUIT 审中-公开
标题翻译：分路负载电路
公开(公告)号：WO1982004364A1
公开(公告)日：1982-12-09
申请号：PCT/US1981000698
申请日：1981-05-26
申请人： MOSTEK CORP , PROEBSTING ROBERT JAMES
发明人： MOSTEK CORP
IPC分类号： H03K19/094
CPC分类号： H03K19/017 , H03K19/09445
摘要： A split load circuit (44) for driving a high speed load (72) and a low speed load (74) to the same logic state in response to one or more input signals. One input signal is provided to the gate terminals of pull-down transistors (48, 50, 52). The inverse of the input signal is provided to the gate terminals of pull-up transistors (64, 66). The high speed load (72) is connected between the pull-up transistor (64) and the pull-down transistor (50) and the low speed load (74) is connected between the pull-up transistor (66) and the pull-down transistor (52). When the input signal at the input node (46) is driven from one voltage state to another, the loads (72, 74) will be driven at different rates depending upon the capacitance and impedance of the load and the sizes of the pull-up transistors (64, 66) and the pull-down transistors (50, 52). The loads (72, 74) are driven independently such that much smaller pull-up and pull-down transistors can be utilized in place of a single pull-up and single pull-down transistor which would need to be fabricated much larger in order to meet the speed requirement of the high speed load (72) and to charge the high capacitance of the low speed load (74). Further, the power consumption is substantially reduced due to the reduced area of the transistors.
摘要翻译：一种用于响应于一个或多个输入信号将高速负载（72）和低速负载（74）驱动到相同逻辑状态的分流负载电路（44）。一个输入信号被提供给下拉晶体管（48,50,52）的栅极端子。输入信号的反相被提供给上拉晶体管（64,66）的栅极端。高速负载（72）连接在上拉晶体管（64）和下拉晶体管（50）之间，低速负载（74）连接在上拉晶体管（66）和上拉晶体管下降晶体管（52）。当输入节点（46）处的输入信号从一个电压状态驱动到另一个时，负载（72,74）将以不同的速率被驱动，这取决于负载的电容和阻抗以及上拉的大小晶体管（64,66）和下拉晶体管（50,52）。负载（72,74）被独立地驱动，使得可以使用更小的上拉和下拉晶体管代替单个上拉和单个下拉晶体管，这将需要被制造得更大，以便满足高速负载（72）的速度要求，并对低速负载（74）的高电容充电。此外，由于晶体管的面积减小，功耗大幅降低。

4. 发明授权

US09325315B2 Nand gate circuit, display back plate, display device and electronic device 有权
标题翻译：南门电路，显示背板，显示设备和电子设备
公开(公告)号：US09325315B2
公开(公告)日：2016-04-26
申请号：US14420880
申请日：2014-08-05
申请人： BOE TECHNOLOGY GROUP CO., LTD.
发明人： Zhongyuan Wu , Danna Song , Liye Duan
IPC分类号： H03K19/094 , H03K19/20 , H03K3/012 , H03K19/0185 , H03K19/0944
CPC分类号： H03K19/018507 , H03K19/09441 , H03K19/09445 , H03K19/20
摘要： The NAND gate circuit includes at least two input transistors, at least two pull-up modules and at least two input control transistors. A first electrode of each input transistor is connected to a second level output end via the pull-up module. The input control transistor is configured to enable a potential of the control end of the pull-up module connected to the first electrode of the input transistor to be the first level when the input signal connected to the gate electrode of the input control transistor is at a second level. The at least two pull-up modules are configured to cut off the connection between the second level output end and the NAND gate output end when all the input signals are at the second level, and enable the connection therebetween when none of the input signals is at the second level.
摘要翻译： NAND门电路包括至少两个输入晶体管，至少两个上拉模块和至少两个输入控制晶体管。每个输入晶体管的第一电极通过上拉模块连接到第二电平输出端。输入控制晶体管被配置为当连接到输入控制晶体管的栅电极的输入信号处于第一电平时，使连接到输入晶体管的第一电极的上拉模块的控制端的电位成为第一电平第二级。所述至少两个上拉模块被配置为当所有输入信号处于第二电平时切断第二电平输出端与NAND门输出端之间的连接，并且当没有输入信号为在第二级。

5. 发明授权

US4767950A MOS inverter circuit having two different supply voltages 失效
标题翻译： MOS反相器电路具有两个不同的电源电压
公开(公告)号：US4767950A
公开(公告)日：1988-08-30
申请号：US883003
申请日：1986-07-07
申请人： Hartmut Schrenk
发明人： Hartmut Schrenk
IPC分类号： H03K19/094 , H03K19/00 , H03K19/0944 , H03K19/0952 , H03K17/687 , G11C11/40 , H03K17/10
CPC分类号： H03K19/09445 , H03K19/0013 , H03K19/09443
摘要： A MOS inverter circuit includes a first supply voltage source, a second supply voltage source being higher than the first supply voltage source, a control MOS FET of the enhancement type, a first load MOS FET of the depletion type connected to the control MOS FET, a parallel circuit of a second load MOS FET of the depletion type and a third MOS FET, the parallel circuit being connected in series with the first load MOS FET, the third MOS FET having a controlled path connected to the first supply voltage source, and the first and second load MOS FET's having controlled paths interconnected in series and connected to the second supply voltage source.
摘要翻译： MOS逆变电路包括第一电源电压源，高于第一电源电压源的第二电源电压源，增强型控制MOS FET，与控制MOS FET连接的耗尽型第一负载MOS FET，所述耗尽型的第二负载MOS FET和第三MOS FET的并联电路，所述并联电路与所述第一负载MOS FET串联连接，所述第三MOS FET具有连接到所述第一电源电压源的受控通路，以及第一和第二负载MOS FET具有串联互连并连接到第二电源电压源的受控通路。

6. 发明授权

US4614882A Bus transceiver including compensation circuit for variations in electrical characteristics of components 失效
标题翻译：总线收发器包括用于元件电气特性变化的补偿电路
公开(公告)号：US4614882A
公开(公告)日：1986-09-30
申请号：US554493
申请日：1983-11-22
申请人： Wayne C. Parker , John W. May
发明人： Wayne C. Parker , John W. May
IPC分类号： G06F13/40 , H03K19/003 , H03K19/0185 , H03K19/0944 , H04L25/02 , H04L25/08 , H03K17/14 , H03K17/687
CPC分类号： H04L25/028 , G06F13/4072 , H03K19/00384 , H03K19/018507 , H03K19/09445 , H04L25/0292 , H04L25/08
摘要： A bus transceiver having a driver with charging/discharging characteristics that are device-independent and a receiver that provides adequate noise immunity is described. The transceiver uses a reference network to modulate the conductance of a depletion device as a function of device parameter variations in order to maintain a constant response time for the driver and optimize peak current. The receiver uses a modified differential amplifier to provide high gain and hysteresis sufficient for a desired level of noise immunity.
摘要翻译：描述具有与设备无关的充电/放电特性的驱动器和提供足够的抗噪声能力的接收器的总线收发器。收发器使用参考网络作为设备参数变化的函数来调制耗尽设备的电导，以便为驱动器保持恒定的响应时间并优化峰值电流。接收机使用经修改的差分放大器来提供足够高的抗噪声能力的高增益和滞后。

7. 发明授权

US4568844A Field effect transistor inverter-level shifter circuitry 失效
标题翻译：场效应晶体管反相器电平移位电路
公开(公告)号：US4568844A
公开(公告)日：1986-02-04
申请号：US467215
申请日：1983-02-17
申请人： Kevin J. O'Connor
发明人： Kevin J. O'Connor
IPC分类号： H03K5/02 , H03K19/0185 , H03K19/0944 , H03K19/003 , H03K17/10 , H03K19/094
CPC分类号： H03K19/09445 , H03K19/018507
摘要： A field effect transistor inverter-level shifter circuit which accepts TTL input level signals and generates MOS output level signals consists of the series combination of a load device, an enhancement mode transistor, and a depletion mode transistor. The gates of the enhancement and depletion mode transistors are connected to an input terminal. The source of the enhancement transistor is connected to the drain of the depletion transistor. The depletion transistor acts to control the potential of the source of the enhancement transistor so as to allow it to tolerate worse case TTL input potential "0" levels while not becoming more than only weakly biased on.
摘要翻译：接收TTL输入电平信号并产生MOS输出电平信号的场效应晶体管反相器电平移位器电路由负载器件，增强型晶体管和耗尽型晶体管的串联组合构成。增强型和耗尽型晶体管的栅极连接到输入端。增强晶体管的源极连接到耗尽晶体管的漏极。耗尽晶体管用于控制增强晶体管的源极的电位，以便允许其容忍更差的TTL输入电位“0”电平，同时不会变得仅仅被弱偏置。

8. 发明申请

US20160028398A1 NAND GATE CIRCUIT, DISPLAY BACK PLATE, DISPLAY DEVICE AND ELECTRONIC DEVICE 有权
标题翻译： NAND门电路，显示背板，显示设备和电子设备
公开(公告)号：US20160028398A1
公开(公告)日：2016-01-28
申请号：US14420880
申请日：2014-08-05
申请人： BOE TECHNOLOGY GROUP CO., LTD.
发明人： Zhongyuan WU , Danna SONG , Liye DUAN
IPC分类号： H03K19/0185 , H03K19/0944 , H03K19/20
CPC分类号： H03K19/018507 , H03K19/09441 , H03K19/09445 , H03K19/20
摘要： The NAND gate circuit includes at least two input transistors, at least two pull-up modules and at least two input control transistors. A first electrode of each input transistor is connected to a second level output end via the pull-up module. The input control transistor is configured to enable a potential of the control end of the pull-up module connected to the first electrode of the input transistor to be the first level when the input signal connected to the gate electrode of the input control transistor is at a second level. The at least two pull-up modules are configured to cut off the connection between the second level output end and the NAND gate output end when all the input signals are at the second level, and enable the connection therebetween when none of the input signals is at the second level.
摘要翻译： NAND门电路包括至少两个输入晶体管，至少两个上拉模块和至少两个输入控制晶体管。每个输入晶体管的第一电极通过上拉模块连接到第二电平输出端。输入控制晶体管被配置为当连接到输入控制晶体管的栅电极的输入信号处于第一电平时，使连接到输入晶体管的第一电极的上拉模块的控制端的电位成为第一电平第二级。所述至少两个上拉模块被配置为当所有输入信号处于第二电平时切断第二电平输出端与NAND门输出端之间的连接，并且当没有输入信号为在第二级。

9. 发明授权

US4533841A MOS logic circuit responsive to an irreversible control voltage for permanently varying its signal transfer characteristic 失效
标题翻译： MOS逻辑电路响应于不可逆控制电压，用于永久改变其信号传输特性
公开(公告)号：US4533841A
公开(公告)日：1985-08-06
申请号：US414832
申请日：1982-09-03
申请人： Satoshi Konishi
发明人： Satoshi Konishi
IPC分类号： H03K19/094 , H03K19/0944 , H03K19/0948 , H03K19/21 , H03K19/173 , H03K19/20
CPC分类号： H03K19/09425 , H03K19/09443 , H03K19/09445 , H03K19/0948 , H03K19/215
摘要： A MOS logic circuit including a known MOS logic circuit arrangement having a particular input/output signal transfer characteristic and a control gating circuit including an FET connected to the known MOS logic circuit arrangement, the gate of which gating circuit receives a control voltage derived from an irreversible control voltage generator utilizing a fuse. Under the control of the irreversible control voltage, the MOS logic circuit can permanently change the known logic circuit arrangement's signal transfer characteristic without varying its logic function.
摘要翻译：包括具有特定输入/输出信号传递特性的已知MOS逻辑电路装置和包括连接到已知MOS逻辑电路装置的FET的控制选通电路的MOS逻辑电路，门控电路接收来自使用保险丝的不可逆控制电压发生器。在不可逆控制电压的控制下，MOS逻辑电路可以永久地改变已知逻辑电路布置的信号传递特性而不改变其逻辑功能。

10. 发明授权

US4525640A High performance and gate having an "natural" or zero threshold transistor for providing a faster rise time for the output 失效
标题翻译：高性能和门极具有“自然”或零阈值晶体管，为输出提供更快的上升时间
公开(公告)号：US4525640A
公开(公告)日：1985-06-25
申请号：US481033
申请日：1983-03-31
申请人： David H. Boyle , Daniel J. Kouba
发明人： David H. Boyle , Daniel J. Kouba
IPC分类号： H03K5/02 , H03K17/06 , H03K19/017 , H03K19/094 , H03K19/0944 , H03K19/20 , H03K17/04 , H03K17/693
CPC分类号： H03K19/09445 , H03K19/01714
摘要： A "natural" threshold device is serially connected between the gate of an output depletion mode FET device and the input node to an FET device so as to provide current flow from the input node to the gate of the FET device as the input waveform begins to rise, and yet to provide sufficient resistance in the gate circuit of the depletion mode device so as to prevent backward flow of current from the gate as the potential of the output node rises. This increases the conductivity of the output load device, thereby providing a faster rise time for the output waveform.
摘要翻译：在输出耗尽型FET器件的栅极和FET器件的输入节点之间串联连接“自然”阈值器件，以便当输入波形开始时，提供从输入节点到FET器件的栅极的电流并且在耗尽型器件的栅极电路中提供足够的电阻，以便当输出节点的电位升高时防止来自栅极的电流的反向流动。这增加了输出负载装置的电导率，从而为输出波形提供了更快的上升时间。

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