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1. 发明授权

US4488067A Tristate driver circuit with low standby power consumption 失效
标题翻译：三态驱动电路具有低待机功耗
公开(公告)号：US4488067A
公开(公告)日：1984-12-11
申请号：US533392
申请日：1983-09-19
申请人： Wayne R. Kraft , Victor S. Moore , William L. Stahl, Jr. , Nandor G. Thoma
发明人： Wayne R. Kraft , Victor S. Moore , William L. Stahl, Jr. , Nandor G. Thoma
IPC分类号： H03K19/0175 , H03K19/094 , H03K19/20 , H03K19/017
CPC分类号： H03K19/09429
摘要： Improved tristate control circuitry is provided for a driver circuit formed on an integrated circuit chip. A parallel-connected combination of a depletion mode transistor and an enhancement mode transistor is connected in series in the voltage supply path for the driver circuit for controlling whether the driver circuit is in an active mode or a standby mode by controlling the supplying of operating voltage thereto. A further enhancement mode transistor provides a shunting action between the driver circuit side of the parallel-connected transistors and circuit ground to further aid in the control of the driver circuit operating mode.
摘要翻译：为在集成电路芯片上形成的驱动电路提供改进的三态控制电路。耗尽型晶体管和增强型晶体管的并联组合串联连接在用于驱动电路的电压供给路径中，用于通过控制提供工作电压来控制驱动电路是处于活动模式还是待机模式到此。另外的增强模式晶体管在并联晶体管的驱动器电路侧和电路接地之间提供分流动作，以进一步有助于控制驱动器电路工作模式。

2. 发明授权

US4531068A Bus line precharging tristate driver circuit 失效
标题翻译：总线预充电三态驱动电路
公开(公告)号：US4531068A
公开(公告)日：1985-07-23
申请号：US533393
申请日：1983-09-19
申请人： Wayne R. Kraft , Victor S. Moore , William L. Stahl, Jr. , Nandor G. Thoma
发明人： Wayne R. Kraft , Victor S. Moore , William L. Stahl, Jr. , Nandor G. Thoma
IPC分类号： H03K19/0175 , H03K5/02 , H03K19/094 , H03K19/20 , H03K19/003
CPC分类号： H03K5/023 , H03K19/09425 , H03K19/09429
摘要： A tristate driver circuit is provided on an integrated circuit chip for driving a bus line or signal line located off of the chip. This circuit very rapidly charges the bus line or signal line to positive voltage level each time and just before it switches to its tristate or high impedance output condition. This eliminates the need for a pull-up resistor or pull-up transistor to be connected to the off-chip bus line or signal line.
摘要翻译：在用于驱动位于芯片外的总线或信号线的集成电路芯片上提供三态驱动器电路。该电路非常快速地将总线或信号线充电至正电压电平，并且恰好在其切换到其三态或高阻抗输出条件之前。这样就不需要连接到片外总线或信号线的上拉电阻或上拉晶体管。

3. 发明授权

US4395646A Logic performing cell for use in array structures 失效
标题翻译：用于阵列结构的逻辑执行单元
公开(公告)号：US4395646A
公开(公告)日：1983-07-26
申请号：US203170
申请日：1980-11-03
申请人： Moises Cases , Wayne R. Kraft , Victor S. Moore , William L. Stahl, Jr. , Nandor G. Thoma
发明人： Moises Cases , Wayne R. Kraft , Victor S. Moore , William L. Stahl, Jr. , Nandor G. Thoma
IPC分类号： H01L27/088 , H01L27/112 , H03K19/0944 , H03K19/177 , H03K19/017 , H03K19/094
CPC分类号： H03K19/1778 , H01L27/0883 , H01L27/112 , H03K19/09445 , H03K19/1772 , H03K19/17728
摘要： A logic performing cell for use in array structures is provided which allows greater density fabrication in integrated circuits and reduces operational delays. The array has a plurality of output lines intercepted by a plurality of orthogonally oriented input lines, with elements in the form of a three terminal device located at each of the intersections of the input and output lines so that logical functions are performed on interrogation signals placed on the input lines and the responses thereto placed on the output lines. The three terminal device transfer gates are connected in groups of series strings which are connected in parallel to a recombination line. These groups of series connected transfer gates comprise a programmed mix of enhancement and depletion devices. Each logic function of each group of transfer gates establishes an output which, when coupled to the recombining output circuit line, provides an overall logic function for the logic performing cell.
摘要翻译：提供了用于阵列结构的逻辑执行单元，其允许在集成电路中进行更大的密度制造并且减少操作延迟。阵列具有由多个正交取向的输入线截取的多个输出线，其中三个终端装置形式的元件位于输入和输出线的每个交叉点处，使得在放置的询问信号上执行逻辑功能在输入线上和对输出线上的响应。三个端子器件传输门以串联串联的方式连接，并联到复合线。这些串联连接的传输门组包括增强和耗尽装置的编程组合。每组传输门的每个逻辑功能建立一个输出，当耦合到重新组合的输出电路线时，该逻辑执行单元提供总逻辑功能。

4. 发明授权

US4583193A Integrated circuit mechanism for coupling multiple programmable logic arrays to a common bus 失效
标题翻译：用于将多个可编程逻辑阵列耦合到公共总线的集成电路机制
公开(公告)号：US4583193A
公开(公告)日：1986-04-15
申请号：US350681
申请日：1982-02-22
申请人： Wayne R. Kraft , Moises Cases , William L. Stahl, Jr. , Nandor G. Thoma , Virgil D. Wyatt
发明人： Wayne R. Kraft , Moises Cases , William L. Stahl, Jr. , Nandor G. Thoma , Virgil D. Wyatt
IPC分类号： H01L21/822 , G06F9/22 , G06F9/26 , G06F9/28 , H01L21/82 , H01L27/04 , H03K19/173 , H03K19/177 , G06F13/38
CPC分类号： G06F9/28 , G06F9/223 , G06F9/267
摘要： An integrated circuit mechanism is provided for coupling the separate sets of output lines from a plurality of programmable logic arrays to the same set of bus lines of plural-line signal transfer bus. This coupling mechanism includes precharge circuitry for precharging each of the bus lines during a first time interval. This coupling mechanism also includes a separate strobe signal line for each programmable logic array and circuitry for activating one of the strobe signal lines during a second time interval for selecting a particular programmable logic array. This coupling mechanism further includes a separate output buffer for each programmable logic array. Each such output buffer includes a plurality of buffer stages for individually coupling the different ones of the programmable logic array output lines to their respective bus lines. The buffer stages for each programmable logic array are responsive to the strobe signal for its programmable logic array for discharging during the second time interval those bus lines for which its programmable logic array output lines are at a particular binary value.
摘要翻译：提供了一种集成电路机制，用于将分离的输出线组从多个可编程逻辑阵列耦合到多行信号传输总线的同一组总线。该耦合机构包括用于在第一时间间隔期间预充电每个总线的预充电电路。该耦合机构还包括用于每个可编程逻辑阵列的单独选通信号线和用于在用于选择特定可编程逻辑阵列的第二时间间隔期间激活选通信号线之一的电路。该耦合机构还包括用于每个可编程逻辑阵列的单独的输出缓冲器。每个这样的输出缓冲器包括用于将不同的可编程逻辑阵列输出线分别耦合到它们各自的总线的多个缓冲级。每个可编程逻辑阵列的缓冲级响应于其可编程逻辑阵列的选通信号，用于在第二时间间隔期间对其可编程逻辑阵列输出线处于特定二进制值的总线进行放电。

5. 发明授权

US4500800A Logic performing cell for use in array structures 失效
标题翻译：用于阵列结构的逻辑执行单元
公开(公告)号：US4500800A
公开(公告)日：1985-02-19
申请号：US413043
申请日：1982-08-30
申请人： Moises Cases , Wayne R. Kraft , William L. Stahl, Jr. , Nandor G. Thoma
发明人： Moises Cases , Wayne R. Kraft , William L. Stahl, Jr. , Nandor G. Thoma
IPC分类号： H03K19/096 , H03K19/177 , H03K19/017 , H03K17/16
CPC分类号： H03K19/1772 , H03K19/096
摘要： As a specific improvement to a previously known PLA (Programmed Logic Array) structure, formed by FET devices in serially chained charge transfer circuits, the presently disclosed "modified" PLA structure comprises a combination of: (a) level shifting circuitry, integrated into bit partitioning stages of the known structure, for reducing voltage swings in the outputs of those stages and thereby reducing spurious couplings to the following AND array stage as well as decreasing operational delays of the latter stage; (b) discrete capacitance, added at the output end of the OR array stage of the known structure, for sustaining and reinforcing charge conditions accumulated in that stage prior to readout (validation clocking) of that stage; and (c) a source of time related clocking functions coupled to stages of the modified structure, with the timing relationships selected so as to reduce operational delays of the entire structure while improving its integrity of operation.
摘要翻译：作为对先前已知的PLA（编程逻辑阵列）结构的具体改进，由串联链式电荷转移电路中的FET器件形成，目前公开的“修改”PLA结构包括以下组合：（a）电平移位电路，集成到位已知结构的分级级，用于减小这些级的输出中的电压摆幅，从而减少到后续阵列级的寄生耦合，并减少后级的运行延迟; （b）在已知结构的OR阵列阶段的输出端处添加的离散电容，用于在该级的读出（验证时钟）之前维持和加强在该级中累积的充电条件; 以及（c）与所述经修改的结构的阶段耦合的时间相关时钟功能源，选择所述定时关系以便减少整个结构的运行延迟，同时提高其操作的完整性。

6. 发明授权

US4484268A Apparatus and method for decoding an operation code using a plurality of multiplexed programmable logic arrays 失效
标题翻译：使用多个可复用可编程逻辑阵列对操作码进行解码的装置和方法
公开(公告)号：US4484268A
公开(公告)日：1984-11-20
申请号：US350661
申请日：1982-02-22
申请人： Nandor G. Thoma , Victor S. Moore , Wayne R. Kraft
发明人： Nandor G. Thoma , Victor S. Moore , Wayne R. Kraft
IPC分类号： G06F9/22 , G06F9/26 , G06F9/30 , H03K19/177 , G06F9/00
CPC分类号： G06F9/267
摘要： A plurality of programmable logic arrays (PLA's) operate in parallel, each to decode an operation code (OP code). A portion of the OP code is decoded to select one of the PLA's, and the decoded OP code from the selected PLA is gated through a multiplexer to provide the control code corresponding to the OP code.
摘要翻译：多个可编程逻辑阵列（PLA）并行操作，每个解码操作码（OP代码）。对OP代码的一部分进行解码以选择PLA中的一个，并且通过多路复用器选择来自所选择的PLA的解码的OP代码以提供对应于OP代码的控制代码。

7. 发明授权

US4947369A Microword generation mechanism utilizing a separate branch decision programmable logic array 失效
标题翻译：微剑生成机制利用单独的分支决策可编程逻辑阵列
公开(公告)号：US4947369A
公开(公告)日：1990-08-07
申请号：US416881
申请日：1989-10-04
申请人： Nandor G. Thoma , Victor S. Moore , Wayne R. Kraft
发明人： Nandor G. Thoma , Victor S. Moore , Wayne R. Kraft
IPC分类号： G06F9/26 , G06F9/42
CPC分类号： G06F9/264
摘要： A microword generation mechanism is provided for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed digital data processor. This microword generation mechanism includes programmable logic array means responsive to the processor instructions for producing the appropriate microword sequences. The microword generation mechanism also includes condition indicator circuitry for supplying indicator signals indicating whether the results of arithmetic and logic operations in the processor meet certain types of conditions. The microword generation mechanism further includes a condition testing programmable logic array responsive to the condition field of a conditional branch type processor instruction for testing the appropriate indicator signal or signals and causing a branch type microword sequence to be produced if the specified condition is met.
摘要翻译：提供了一种微词生成机制，用于产生用于控制微程序数字数据处理器中的处理器指令的执行的微词序列。该微词生成机制包括响应于处理器指令以产生适当的微词序列的可编程逻辑阵列装置。微字生成机构还包括用于提供指示信号的条件指示器电路，其指示处理器中的算术和逻辑运算的结果是否符合某些类型的条件。微字生成机构还包括响应于条件分支型处理器指令的条件字段的条件测试可编程逻辑阵列，用于测试适当的指示符信号或者如果满足指定条件则产生分支型微字序列。

8. 发明授权

US4567561A Large scale integration data processor signal transfer mechanism 失效
标题翻译：大规模集成数据处理器信号传递机制
公开(公告)号：US4567561A
公开(公告)日：1986-01-28
申请号：US334185
申请日：1981-12-24
申请人： Virgil D. Wyatt , Wayne R. Kraft , Nandor G. Thoma
发明人： Virgil D. Wyatt , Wayne R. Kraft , Nandor G. Thoma
IPC分类号： G06F7/00 , G06F9/30 , G06F13/40 , G06F15/78 , G06F9/00
CPC分类号： G06F13/4077 , G06F15/7864 , Y02B60/1225 , Y02B60/1228 , Y02B60/1235
摘要： A digital data signal transfer mechanism is provided for use in large scale integration digital data processor circuitry formed on an integrated circuit chip. The signal transfer mechanism includes a plural-bit data bus formed on the integrated circuit chip for transferring plural-bit binary data signals between different locations on the chip. The signal transfer mechanism also includes plural-bit signal source circuitry and plural-bit signal destination circuitry formed on the integrated circuit chip and coupled to the plural-bit data bus for respectively supplying plural-bit data signals to and receiving plural-bit data signals from the bus. The signal transfer mechanism further includes processor control circuitry coupled to the signal source and signal destination circuitry for enabling the signal source circuitry to put a plural-bit data signal onto the data bus during a first processor control cycle and for enabling the signal destination circuitry to take in this plural-bit data signal from the bus during a second and different processor control cycle. The inherent capacitance of the plural-bit data bus serves to store the plural-bit data signal during the first and second and any intervening processor control cycles.
摘要翻译：提供数字数据信号传送机制，用于形成在集成电路芯片上的大规模集成数字数据处理器电路。信号传送机构包括形成在集成电路芯片上用于在芯片上的不同位置之间传送多位二进制数据信号的多位数据总线。信号传送机构还包括形成在集成电路芯片上并耦合到多位数据总线的多位信号源电路和多位信号目的地电路，用于分别向多位数据信号提供多位数据信号并接收多位数据信号从公共汽车。信号传送机构还包括耦合到信号源和信号目的地电路的处理器控制电路，用于使信号源电路在第一处理器控制周期期间将多位数据信号放入数据总线上，并使信号目的地电路能够在第二和不同的处理器控制周期期间从总线接收该多位数据信号。多位数据总线的固有电容用于在第一和第二和任何中间处理器控制周期期间存储多位数据信号。

9. 发明授权

US4608649A Differential cascode voltage switch (DCVS) master slice for high efficiency/custom density physical design 失效
标题翻译：差分共源共栅电压开关（DCVS）主片用于高效率/定制密度物理设计
公开(公告)号：US4608649A
公开(公告)日：1986-08-26
申请号：US508451
申请日：1983-06-27
申请人： James W. Davis , Victor S. Moore , Nandor G. Thoma
发明人： James W. Davis , Victor S. Moore , Nandor G. Thoma
IPC分类号： G06F17/50 , H01L27/118 , H03K19/173 , H03K19/094
CPC分类号： H01L27/11803 , G06F17/5068 , H03K19/1738
摘要： A topological physical circuit design is utilized for the support of a Differential Cascode Voltage Switch circuit/logic technology in an Automated Placement-Wiring environment. This physical entity takes the form of a "brickwall" set of transistors in a Master Slice image which may be stored and later personalized.
摘要翻译：拓扑物理电路设计用于在自动放置布线环境中支持差分串联电压开关电路/逻辑技术。该物理实体采用可以存储和稍后个性化的主切片图像中的“砖墙”一组晶体管的形式。

10. 发明授权

US5619158A Hierarchical clocking system using adaptive feedback 失效
标题翻译：使用自适应反馈的分层计时系统
公开(公告)号：US5619158A
公开(公告)日：1997-04-08
申请号：US516704
申请日：1995-08-18
申请人： Humberto F. Casal , Joel R. Davidson , Hehching H. Li , Yuan C. Lo , Trong D. Nguyen , Campbell H. Snyder , Nandor G. Thoma
发明人： Humberto F. Casal , Joel R. Davidson , Hehching H. Li , Yuan C. Lo , Trong D. Nguyen , Campbell H. Snyder , Nandor G. Thoma
IPC分类号： G06F1/10 , H03K5/13
CPC分类号： G06F1/10
摘要： A clocking system for complex electronic devices is created in an hierarchial manner whereby the master clock pulse is provided to a plurality of digital pulse aligners which in turn provide phase aligned clock signals at the field replaceable unit level to either a slave clock or a digital phase aligner. The slave clock or the digital phase aligner at the field replaceable unit level in turn provides an aligned clock pulse to a timing node on respective chips. A third level of the hierarchy provides similarly aligned pulses to individual using-circuits on the chips of the system. The digital phase aligner, aligning the output pulse at the timing node of the next level with the reference pulses being provided to the digital phase aligner at each level, insures that the timing pulses arriving at the utilizing circuits are synchronously aligned with clock pulses of the master clock. The system provides dramatic simplification of replacement of either field replaceable units or individual components within field replaceable units. The system is self-phasing and self-correcting to accommodate timing misalignments caused by any variations in the timing delays at all levels, thereby reducing the jitter that must be accommodated.
摘要翻译：以分层方式创建用于复杂电子设备的时钟系统，由此主时钟脉冲被提供给多个数字脉冲对准器，这些数字脉冲对准器又将现场可更换单元级的相位对准时钟信号提供给从时钟或数字相位对准器在现场可更换单元级别的从时钟或数字相位对准器又向相应芯片上的定时节点提供对准的时钟脉冲。层次结构的第三级向系统芯片上的各个使用电路提供类似的对齐脉冲。数字相位对准器将下一级的定时节点处的输出脉冲与在每个电平处提供给数字相位对准器的参考脉冲对准，确保到达利用电路的定时脉冲与时钟脉冲同步地对准主时钟。该系统显着简化了现场可更换单元中现场可更换单元或单个组件的更换。该系统是自相位和自校正，以适应由于各级定时延迟的任何变化引起的定时未对准，从而减少必须适应的抖动。

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